diff --git a/Reciver/Reciver.atsuo b/Reciver/Reciver.atsuo
index 4134013..bd08528 100644
Binary files a/Reciver/Reciver.atsuo and b/Reciver/Reciver.atsuo differ
diff --git a/Reciver/Reciver/Debug/Reciver.elf b/Reciver/Reciver/Debug/Reciver.elf
index 3ad46a6..d554f84 100644
Binary files a/Reciver/Reciver/Debug/Reciver.elf and b/Reciver/Reciver/Debug/Reciver.elf differ
diff --git a/Reciver/Reciver/Debug/Reciver.hex b/Reciver/Reciver/Debug/Reciver.hex
index 0d97ab3..b8867c2 100644
--- a/Reciver/Reciver/Debug/Reciver.hex
+++ b/Reciver/Reciver/Debug/Reciver.hex
@@ -1,112 +1,112 @@
 :100000000C942A000C9447000C9447000C94470071
 :100010000C9447000C9447000C9447000C94470044
-:100020000C9447000C94E3000C9447000C94470098
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 :100030000C9447000C9447000C9447000C94470024
 :100040000C9447000C9447000C9447000C94470014
 :100050000C94470011241FBECFE5D4E0DEBFCDBF16
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+:10068000661F771F881F991F1A9469F760957095E8
+:10069000809590959B01AC01BD01CF01089597FB1A
+:1006A000092E05260ED057FD04D0D7DF0AD0001C36
+:1006B00038F450954095309521953F4F4F4F5F4FFF
+:1006C0000895F6F790958095709561957F4F8F4FBF
+:0806D0009F4F0895F894FFCF3D
+:0406D800CA00020052
 :00000001FF
diff --git a/Reciver/Reciver/Debug/Reciver.lss b/Reciver/Reciver/Debug/Reciver.lss
index e62979e..eb5a93c 100644
--- a/Reciver/Reciver/Debug/Reciver.lss
+++ b/Reciver/Reciver/Debug/Reciver.lss
@@ -3,29 +3,29 @@ Reciver.elf:     file format elf32-avr
 
 Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         000006d4  00000000  00000000  00000094  2**1
+  0 .text         000006d8  00000000  00000000  00000094  2**1
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  1 .data         00000002  00800060  000006d4  00000768  2**0
+  1 .data         00000004  00800060  000006d8  0000076c  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000004  00800062  00800062  0000076a  2**0
+  2 .bss          00000002  00800064  00800064  00000770  2**0
                   ALLOC
-  3 .stab         000006cc  00000000  00000000  0000076c  2**2
+  3 .stab         000006cc  00000000  00000000  00000770  2**2
                   CONTENTS, READONLY, DEBUGGING
-  4 .stabstr      00000085  00000000  00000000  00000e38  2**0
+  4 .stabstr      00000085  00000000  00000000  00000e3c  2**0
                   CONTENTS, READONLY, DEBUGGING
-  5 .debug_aranges 000000e0  00000000  00000000  00000ec0  2**3
+  5 .debug_aranges 000000e0  00000000  00000000  00000ec8  2**3
                   CONTENTS, READONLY, DEBUGGING
-  6 .debug_info   00000c22  00000000  00000000  00000fa0  2**0
+  6 .debug_info   00000c22  00000000  00000000  00000fa8  2**0
                   CONTENTS, READONLY, DEBUGGING
-  7 .debug_abbrev 00000388  00000000  00000000  00001bc2  2**0
+  7 .debug_abbrev 00000388  00000000  00000000  00001bca  2**0
                   CONTENTS, READONLY, DEBUGGING
-  8 .debug_line   000006ff  00000000  00000000  00001f4a  2**0
+  8 .debug_line   000006ff  00000000  00000000  00001f52  2**0
                   CONTENTS, READONLY, DEBUGGING
-  9 .debug_frame  000001c8  00000000  00000000  0000264c  2**2
+  9 .debug_frame  000001c8  00000000  00000000  00002654  2**2
                   CONTENTS, READONLY, DEBUGGING
- 10 .debug_str    0000024b  00000000  00000000  00002814  2**0
+ 10 .debug_str    0000024b  00000000  00000000  0000281c  2**0
                   CONTENTS, READONLY, DEBUGGING
- 11 .debug_loc    00000562  00000000  00000000  00002a5f  2**0
+ 11 .debug_loc    00000562  00000000  00000000  00002a67  2**0
                   CONTENTS, READONLY, DEBUGGING
 
 Disassembly of section .text:
@@ -40,7 +40,7 @@ Disassembly of section .text:
   18:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   1c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   20:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
-  24:	0c 94 e3 00 	jmp	0x1c6	; 0x1c6 <__vector_9>
+  24:	0c 94 e5 00 	jmp	0x1ca	; 0x1ca <__vector_9>
   28:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   2c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   30:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
@@ -65,18 +65,18 @@ Disassembly of section .text:
   60:	10 e0       	ldi	r17, 0x00	; 0
   62:	a0 e6       	ldi	r26, 0x60	; 96
   64:	b0 e0       	ldi	r27, 0x00	; 0
-  66:	e4 ed       	ldi	r30, 0xD4	; 212
+  66:	e8 ed       	ldi	r30, 0xD8	; 216
   68:	f6 e0       	ldi	r31, 0x06	; 6
   6a:	02 c0       	rjmp	.+4      	; 0x70 <__do_copy_data+0x10>
   6c:	05 90       	lpm	r0, Z+
   6e:	0d 92       	st	X+, r0
-  70:	a2 36       	cpi	r26, 0x62	; 98
+  70:	a4 36       	cpi	r26, 0x64	; 100
   72:	b1 07       	cpc	r27, r17
   74:	d9 f7       	brne	.-10     	; 0x6c <__do_copy_data+0xc>
 
 00000076 <__do_clear_bss>:
   76:	10 e0       	ldi	r17, 0x00	; 0
-  78:	a2 e6       	ldi	r26, 0x62	; 98
+  78:	a4 e6       	ldi	r26, 0x64	; 100
   7a:	b0 e0       	ldi	r27, 0x00	; 0
   7c:	01 c0       	rjmp	.+2      	; 0x80 <.do_clear_bss_start>
 
@@ -87,8 +87,8 @@ Disassembly of section .text:
   80:	a6 36       	cpi	r26, 0x66	; 102
   82:	b1 07       	cpc	r27, r17
   84:	e1 f7       	brne	.-8      	; 0x7e <.do_clear_bss_loop>
-  86:	0e 94 7b 01 	call	0x2f6	; 0x2f6 <main>
-  8a:	0c 94 68 03 	jmp	0x6d0	; 0x6d0 <_exit>
+  86:	0e 94 7d 01 	call	0x2fa	; 0x2fa <main>
+  8a:	0c 94 6a 03 	jmp	0x6d4	; 0x6d4 <_exit>
 
 0000008e <__bad_interrupt>:
   8e:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>
@@ -96,26 +96,26 @@ Disassembly of section .text:
 00000092 <turn>:
 volatile int pwm_led = 0;
 
-volatile int servopos = 0;
+volatile int servopos = RIGHT;
 
 void turn() {
 	if(status == RUN)
-  92:	80 91 60 00 	lds	r24, 0x0060
-  96:	90 91 61 00 	lds	r25, 0x0061
+  92:	80 91 62 00 	lds	r24, 0x0062
+  96:	90 91 63 00 	lds	r25, 0x0063
   9a:	86 30       	cpi	r24, 0x06	; 6
   9c:	91 05       	cpc	r25, r1
-  9e:	11 f1       	breq	.+68     	; 0xe4 <turn+0x52>
+  9e:	21 f1       	breq	.+72     	; 0xe8 <turn+0x56>
 		return;
 	status = RUN;
   a0:	86 e0       	ldi	r24, 0x06	; 6
   a2:	90 e0       	ldi	r25, 0x00	; 0
-  a4:	90 93 61 00 	sts	0x0061, r25
-  a8:	80 93 60 00 	sts	0x0060, r24
-	servopos = RIGHT;
-  ac:	8a ec       	ldi	r24, 0xCA	; 202
+  a4:	90 93 63 00 	sts	0x0063, r25
+  a8:	80 93 62 00 	sts	0x0062, r24
+	servopos = RIGHT-60;
+  ac:	8e e8       	ldi	r24, 0x8E	; 142
   ae:	90 e0       	ldi	r25, 0x00	; 0
-  b0:	90 93 63 00 	sts	0x0063, r25
-  b4:	80 93 62 00 	sts	0x0062, r24
+  b0:	90 93 61 00 	sts	0x0061, r25
+  b4:	80 93 60 00 	sts	0x0060, r24
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
@@ -132,1093 +132,1095 @@ void turn() {
   c6:	00 c0       	rjmp	.+0      	; 0xc8 <turn+0x36>
   c8:	00 00       	nop
 	_delay_ms(700);
-	servopos = 0;
-  ca:	10 92 63 00 	sts	0x0063, r1
-  ce:	10 92 62 00 	sts	0x0062, r1
-  d2:	8f ef       	ldi	r24, 0xFF	; 255
-  d4:	96 e1       	ldi	r25, 0x16	; 22
-  d6:	a1 e1       	ldi	r26, 0x11	; 17
-  d8:	81 50       	subi	r24, 0x01	; 1
-  da:	90 40       	sbci	r25, 0x00	; 0
-  dc:	a0 40       	sbci	r26, 0x00	; 0
-  de:	e1 f7       	brne	.-8      	; 0xd8 <turn+0x46>
-  e0:	00 c0       	rjmp	.+0      	; 0xe2 <turn+0x50>
-  e2:	00 00       	nop
-  e4:	08 95       	ret
+	servopos = RIGHT;
+  ca:	8a ec       	ldi	r24, 0xCA	; 202
+  cc:	90 e0       	ldi	r25, 0x00	; 0
+  ce:	90 93 61 00 	sts	0x0061, r25
+  d2:	80 93 60 00 	sts	0x0060, r24
+  d6:	8f ef       	ldi	r24, 0xFF	; 255
+  d8:	96 e1       	ldi	r25, 0x16	; 22
+  da:	a1 e1       	ldi	r26, 0x11	; 17
+  dc:	81 50       	subi	r24, 0x01	; 1
+  de:	90 40       	sbci	r25, 0x00	; 0
+  e0:	a0 40       	sbci	r26, 0x00	; 0
+  e2:	e1 f7       	brne	.-8      	; 0xdc <turn+0x4a>
+  e4:	00 c0       	rjmp	.+0      	; 0xe6 <turn+0x54>
+  e6:	00 00       	nop
+  e8:	08 95       	ret
 
-000000e6 <poll>:
+000000ea <poll>:
 	_delay_ms(700);
 }
 
 void poll() {
 	DDRD &= ~(1<<PIND1);
-  e6:	89 98       	cbi	0x11, 1	; 17
+  ea:	89 98       	cbi	0x11, 1	; 17
 	if(status == ACTIVE) {
-  e8:	80 91 60 00 	lds	r24, 0x0060
-  ec:	90 91 61 00 	lds	r25, 0x0061
-  f0:	83 30       	cpi	r24, 0x03	; 3
-  f2:	91 05       	cpc	r25, r1
-  f4:	41 f4       	brne	.+16     	; 0x106 <poll+0x20>
+  ec:	80 91 62 00 	lds	r24, 0x0062
+  f0:	90 91 63 00 	lds	r25, 0x0063
+  f4:	83 30       	cpi	r24, 0x03	; 3
+  f6:	91 05       	cpc	r25, r1
+  f8:	41 f4       	brne	.+16     	; 0x10a <poll+0x20>
 		if(PIND & (1<<PIND1)) {
-  f6:	81 9b       	sbis	0x10, 1	; 16
-  f8:	06 c0       	rjmp	.+12     	; 0x106 <poll+0x20>
+  fa:	81 9b       	sbis	0x10, 1	; 16
+  fc:	06 c0       	rjmp	.+12     	; 0x10a <poll+0x20>
 			rf12_endasyncrx();
-  fa:	0e 94 58 02 	call	0x4b0	; 0x4b0 <rf12_endasyncrx>
+  fe:	0e 94 5a 02 	call	0x4b4	; 0x4b4 <rf12_endasyncrx>
 			turn();
-  fe:	0e 94 49 00 	call	0x92	; 0x92 <turn>
+ 102:	0e 94 49 00 	call	0x92	; 0x92 <turn>
 			rf12_beginasyncrx();
- 102:	0e 94 41 02 	call	0x482	; 0x482 <rf12_beginasyncrx>
- 106:	08 95       	ret
+ 106:	0e 94 43 02 	call	0x486	; 0x486 <rf12_beginasyncrx>
+ 10a:	08 95       	ret
 
-00000108 <recive>:
+0000010c <recive>:
 		}
 	}
 }
 
 void recive() {
- 108:	cf 93       	push	r28
+ 10c:	cf 93       	push	r28
 	rf12_beginasyncrx();
- 10a:	0e 94 41 02 	call	0x482	; 0x482 <rf12_beginasyncrx>
+ 10e:	0e 94 43 02 	call	0x486	; 0x486 <rf12_beginasyncrx>
 	while(rf12_hasdata()) {
- 10e:	02 c0       	rjmp	.+4      	; 0x114 <recive+0xc>
+ 112:	02 c0       	rjmp	.+4      	; 0x118 <recive+0xc>
 		poll();
- 110:	0e 94 73 00 	call	0xe6	; 0xe6 <poll>
+ 114:	0e 94 75 00 	call	0xea	; 0xea <poll>
 	}
 }
 
 void recive() {
 	rf12_beginasyncrx();
 	while(rf12_hasdata()) {
- 114:	0e 94 4e 02 	call	0x49c	; 0x49c <rf12_hasdata>
- 118:	88 23       	and	r24, r24
- 11a:	d1 f7       	brne	.-12     	; 0x110 <recive+0x8>
+ 118:	0e 94 50 02 	call	0x4a0	; 0x4a0 <rf12_hasdata>
+ 11c:	88 23       	and	r24, r24
+ 11e:	d1 f7       	brne	.-12     	; 0x114 <recive+0x8>
 		poll();
 	}
 	uint8_t addr = rf12_rxbyte();
- 11c:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_rxbyte>
+ 120:	0e 94 55 02 	call	0x4aa	; 0x4aa <rf12_rxbyte>
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
- 120:	88 23       	and	r24, r24
- 122:	41 f0       	breq	.+16     	; 0x134 <recive+0x2c>
- 124:	8a 30       	cpi	r24, 0x0A	; 10
- 126:	31 f0       	breq	.+12     	; 0x134 <recive+0x2c>
- 128:	80 3f       	cpi	r24, 0xF0	; 240
- 12a:	09 f0       	breq	.+2      	; 0x12e <recive+0x26>
- 12c:	42 c0       	rjmp	.+132    	; 0x1b2 <recive+0xaa>
- 12e:	02 c0       	rjmp	.+4      	; 0x134 <recive+0x2c>
+ 124:	88 23       	and	r24, r24
+ 126:	41 f0       	breq	.+16     	; 0x138 <recive+0x2c>
+ 128:	8a 30       	cpi	r24, 0x0A	; 10
+ 12a:	31 f0       	breq	.+12     	; 0x138 <recive+0x2c>
+ 12c:	80 3f       	cpi	r24, 0xF0	; 240
+ 12e:	09 f0       	breq	.+2      	; 0x132 <recive+0x26>
+ 130:	42 c0       	rjmp	.+132    	; 0x1b6 <recive+0xaa>
+ 132:	02 c0       	rjmp	.+4      	; 0x138 <recive+0x2c>
 		while(rf12_hasdata()) {
 			poll();
- 130:	0e 94 73 00 	call	0xe6	; 0xe6 <poll>
+ 134:	0e 94 75 00 	call	0xea	; 0xea <poll>
 	while(rf12_hasdata()) {
 		poll();
 	}
 	uint8_t addr = rf12_rxbyte();
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
 		while(rf12_hasdata()) {
- 134:	0e 94 4e 02 	call	0x49c	; 0x49c <rf12_hasdata>
- 138:	88 23       	and	r24, r24
- 13a:	d1 f7       	brne	.-12     	; 0x130 <recive+0x28>
+ 138:	0e 94 50 02 	call	0x4a0	; 0x4a0 <rf12_hasdata>
+ 13c:	88 23       	and	r24, r24
+ 13e:	d1 f7       	brne	.-12     	; 0x134 <recive+0x28>
 			poll();
 		}
 		uint8_t from = rf12_rxbyte();
- 13c:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_rxbyte>
- 140:	c8 2f       	mov	r28, r24
+ 140:	0e 94 55 02 	call	0x4aa	; 0x4aa <rf12_rxbyte>
+ 144:	c8 2f       	mov	r28, r24
 		while(rf12_hasdata()) {
- 142:	02 c0       	rjmp	.+4      	; 0x148 <recive+0x40>
+ 146:	02 c0       	rjmp	.+4      	; 0x14c <recive+0x40>
 			poll();
- 144:	0e 94 73 00 	call	0xe6	; 0xe6 <poll>
+ 148:	0e 94 75 00 	call	0xea	; 0xea <poll>
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
 		while(rf12_hasdata()) {
 			poll();
 		}
 		uint8_t from = rf12_rxbyte();
 		while(rf12_hasdata()) {
- 148:	0e 94 4e 02 	call	0x49c	; 0x49c <rf12_hasdata>
- 14c:	88 23       	and	r24, r24
- 14e:	d1 f7       	brne	.-12     	; 0x144 <recive+0x3c>
+ 14c:	0e 94 50 02 	call	0x4a0	; 0x4a0 <rf12_hasdata>
+ 150:	88 23       	and	r24, r24
+ 152:	d1 f7       	brne	.-12     	; 0x148 <recive+0x3c>
 			poll();
 		}
 		if(from == MASTER) {
- 150:	c1 30       	cpi	r28, 0x01	; 1
- 152:	79 f5       	brne	.+94     	; 0x1b2 <recive+0xaa>
+ 154:	c1 30       	cpi	r28, 0x01	; 1
+ 156:	79 f5       	brne	.+94     	; 0x1b6 <recive+0xaa>
 			uint8_t data = rf12_rxbyte();
- 154:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_rxbyte>
+ 158:	0e 94 55 02 	call	0x4aa	; 0x4aa <rf12_rxbyte>
 			switch(data) {
- 158:	84 30       	cpi	r24, 0x04	; 4
- 15a:	51 f0       	breq	.+20     	; 0x170 <recive+0x68>
- 15c:	85 30       	cpi	r24, 0x05	; 5
- 15e:	18 f4       	brcc	.+6      	; 0x166 <recive+0x5e>
- 160:	81 30       	cpi	r24, 0x01	; 1
- 162:	39 f5       	brne	.+78     	; 0x1b2 <recive+0xaa>
- 164:	16 c0       	rjmp	.+44     	; 0x192 <recive+0x8a>
- 166:	85 30       	cpi	r24, 0x05	; 5
- 168:	51 f0       	breq	.+20     	; 0x17e <recive+0x76>
- 16a:	87 30       	cpi	r24, 0x07	; 7
- 16c:	11 f5       	brne	.+68     	; 0x1b2 <recive+0xaa>
- 16e:	0e c0       	rjmp	.+28     	; 0x18c <recive+0x84>
+ 15c:	84 30       	cpi	r24, 0x04	; 4
+ 15e:	51 f0       	breq	.+20     	; 0x174 <recive+0x68>
+ 160:	85 30       	cpi	r24, 0x05	; 5
+ 162:	18 f4       	brcc	.+6      	; 0x16a <recive+0x5e>
+ 164:	81 30       	cpi	r24, 0x01	; 1
+ 166:	39 f5       	brne	.+78     	; 0x1b6 <recive+0xaa>
+ 168:	16 c0       	rjmp	.+44     	; 0x196 <recive+0x8a>
+ 16a:	85 30       	cpi	r24, 0x05	; 5
+ 16c:	51 f0       	breq	.+20     	; 0x182 <recive+0x76>
+ 16e:	87 30       	cpi	r24, 0x07	; 7
+ 170:	11 f5       	brne	.+68     	; 0x1b6 <recive+0xaa>
+ 172:	0e c0       	rjmp	.+28     	; 0x190 <recive+0x84>
 				case PING: {
 					break;
 				}
 				case SETSLEEP: {
 					status = SLEEP;
- 170:	82 e0       	ldi	r24, 0x02	; 2
- 172:	90 e0       	ldi	r25, 0x00	; 0
- 174:	90 93 61 00 	sts	0x0061, r25
- 178:	80 93 60 00 	sts	0x0060, r24
+ 174:	82 e0       	ldi	r24, 0x02	; 2
+ 176:	90 e0       	ldi	r25, 0x00	; 0
+ 178:	90 93 63 00 	sts	0x0063, r25
+ 17c:	80 93 62 00 	sts	0x0062, r24
 					break;
- 17c:	0a c0       	rjmp	.+20     	; 0x192 <recive+0x8a>
+ 180:	0a c0       	rjmp	.+20     	; 0x196 <recive+0x8a>
 				}
 				case SETACTIVE: {
 					status = ACTIVE;
- 17e:	83 e0       	ldi	r24, 0x03	; 3
- 180:	90 e0       	ldi	r25, 0x00	; 0
- 182:	90 93 61 00 	sts	0x0061, r25
- 186:	80 93 60 00 	sts	0x0060, r24
+ 182:	83 e0       	ldi	r24, 0x03	; 3
+ 184:	90 e0       	ldi	r25, 0x00	; 0
+ 186:	90 93 63 00 	sts	0x0063, r25
+ 18a:	80 93 62 00 	sts	0x0062, r24
 					break;
- 18a:	03 c0       	rjmp	.+6      	; 0x192 <recive+0x8a>
+ 18e:	03 c0       	rjmp	.+6      	; 0x196 <recive+0x8a>
 				}
 				case SETRUN: {
 					turn();
- 18c:	0e 94 49 00 	call	0x92	; 0x92 <turn>
- 190:	10 c0       	rjmp	.+32     	; 0x1b2 <recive+0xaa>
+ 190:	0e 94 49 00 	call	0x92	; 0x92 <turn>
+ 194:	10 c0       	rjmp	.+32     	; 0x1b6 <recive+0xaa>
 				default:
 				{
 					return;
 				}
 			}
 			rf12_endasyncrx();
- 192:	0e 94 58 02 	call	0x4b0	; 0x4b0 <rf12_endasyncrx>
- 196:	8f e3       	ldi	r24, 0x3F	; 63
- 198:	9c e9       	ldi	r25, 0x9C	; 156
- 19a:	01 97       	sbiw	r24, 0x01	; 1
- 19c:	f1 f7       	brne	.-4      	; 0x19a <recive+0x92>
- 19e:	00 c0       	rjmp	.+0      	; 0x1a0 <recive+0x98>
- 1a0:	00 00       	nop
+ 196:	0e 94 5a 02 	call	0x4b4	; 0x4b4 <rf12_endasyncrx>
+ 19a:	8f e3       	ldi	r24, 0x3F	; 63
+ 19c:	9c e9       	ldi	r25, 0x9C	; 156
+ 19e:	01 97       	sbiw	r24, 0x01	; 1
+ 1a0:	f1 f7       	brne	.-4      	; 0x19e <recive+0x92>
+ 1a2:	00 c0       	rjmp	.+0      	; 0x1a4 <recive+0x98>
+ 1a4:	00 00       	nop
 			_delay_ms(20);
 			rf12_txpacket(MASTER, DEVICE, status);
- 1a2:	40 91 60 00 	lds	r20, 0x0060
- 1a6:	50 91 61 00 	lds	r21, 0x0061
- 1aa:	81 e0       	ldi	r24, 0x01	; 1
- 1ac:	6a e0       	ldi	r22, 0x0A	; 10
- 1ae:	0e 94 d5 02 	call	0x5aa	; 0x5aa <rf12_txpacket>
+ 1a6:	40 91 62 00 	lds	r20, 0x0062
+ 1aa:	50 91 63 00 	lds	r21, 0x0063
+ 1ae:	81 e0       	ldi	r24, 0x01	; 1
+ 1b0:	6a e0       	ldi	r22, 0x0A	; 10
+ 1b2:	0e 94 d7 02 	call	0x5ae	; 0x5ae <rf12_txpacket>
 	text[1] = 0;
 	rf12_rxdata(text,2);
 	if(text[0] == DEVICE && text[1] == PING) {
 		turn();
 	}*/
 }
- 1b2:	cf 91       	pop	r28
- 1b4:	08 95       	ret
+ 1b6:	cf 91       	pop	r28
+ 1b8:	08 95       	ret
 
-000001b6 <init_timer>:
+000001ba <init_timer>:
 	// Clock source: System Clock
 	// Clock value: 7,813 kHz
 	// Mode: Normal top=0xFF
 	// OC0 output: Disconnected
 	// Timer Period: 21,504 ms
 	TCCR0=(0<<WGM00) | (0<<COM01) | (0<<COM00) | (0<<WGM01) | (1<<CS02) | (0<<CS01) | (1<<CS00);
- 1b6:	85 e0       	ldi	r24, 0x05	; 5
- 1b8:	83 bf       	out	0x33, r24	; 51
+ 1ba:	85 e0       	ldi	r24, 0x05	; 5
+ 1bc:	83 bf       	out	0x33, r24	; 51
 	TCNT0=0x58;
- 1ba:	88 e5       	ldi	r24, 0x58	; 88
- 1bc:	82 bf       	out	0x32, r24	; 50
+ 1be:	88 e5       	ldi	r24, 0x58	; 88
+ 1c0:	82 bf       	out	0x32, r24	; 50
 	OCR0=0x00;
- 1be:	1c be       	out	0x3c, r1	; 60
+ 1c2:	1c be       	out	0x3c, r1	; 60
 	// Timer(s)/Counter(s) Interrupt(s) initialization
 	TIMSK=(0<<OCIE2) | (0<<TOIE2) | (0<<TICIE1) | (0<<OCIE1A) | (0<<OCIE1B) | (0<<TOIE1) | (0<<OCIE0) | (1<<TOIE0);
- 1c0:	81 e0       	ldi	r24, 0x01	; 1
- 1c2:	89 bf       	out	0x39, r24	; 57
+ 1c4:	81 e0       	ldi	r24, 0x01	; 1
+ 1c6:	89 bf       	out	0x39, r24	; 57
 }
- 1c4:	08 95       	ret
+ 1c8:	08 95       	ret
 
-000001c6 <__vector_9>:
+000001ca <__vector_9>:
 
 ISR(TIMER0_OVF_vect) {
- 1c6:	1f 92       	push	r1
- 1c8:	0f 92       	push	r0
- 1ca:	0f b6       	in	r0, 0x3f	; 63
+ 1ca:	1f 92       	push	r1
  1cc:	0f 92       	push	r0
- 1ce:	11 24       	eor	r1, r1
- 1d0:	2f 93       	push	r18
- 1d2:	3f 93       	push	r19
- 1d4:	8f 93       	push	r24
- 1d6:	9f 93       	push	r25
+ 1ce:	0f b6       	in	r0, 0x3f	; 63
+ 1d0:	0f 92       	push	r0
+ 1d2:	11 24       	eor	r1, r1
+ 1d4:	2f 93       	push	r18
+ 1d6:	3f 93       	push	r19
+ 1d8:	8f 93       	push	r24
+ 1da:	9f 93       	push	r25
 	// Reinitialize Timer 0 value
 	TCNT0=0x58;
- 1d8:	88 e5       	ldi	r24, 0x58	; 88
- 1da:	82 bf       	out	0x32, r24	; 50
+ 1dc:	88 e5       	ldi	r24, 0x58	; 88
+ 1de:	82 bf       	out	0x32, r24	; 50
 	
 	if(status == SLEEP) {
- 1dc:	80 91 60 00 	lds	r24, 0x0060
- 1e0:	90 91 61 00 	lds	r25, 0x0061
- 1e4:	82 30       	cpi	r24, 0x02	; 2
- 1e6:	91 05       	cpc	r25, r1
- 1e8:	d9 f4       	brne	.+54     	; 0x220 <__vector_9+0x5a>
+ 1e0:	80 91 62 00 	lds	r24, 0x0062
+ 1e4:	90 91 63 00 	lds	r25, 0x0063
+ 1e8:	82 30       	cpi	r24, 0x02	; 2
+ 1ea:	91 05       	cpc	r25, r1
+ 1ec:	d9 f4       	brne	.+54     	; 0x224 <__vector_9+0x5a>
 		if(pwm_led < 50) {
- 1ea:	80 91 64 00 	lds	r24, 0x0064
- 1ee:	90 91 65 00 	lds	r25, 0x0065
- 1f2:	82 33       	cpi	r24, 0x32	; 50
- 1f4:	91 05       	cpc	r25, r1
- 1f6:	54 f4       	brge	.+20     	; 0x20c <__vector_9+0x46>
+ 1ee:	80 91 64 00 	lds	r24, 0x0064
+ 1f2:	90 91 65 00 	lds	r25, 0x0065
+ 1f6:	82 33       	cpi	r24, 0x32	; 50
+ 1f8:	91 05       	cpc	r25, r1
+ 1fa:	54 f4       	brge	.+20     	; 0x210 <__vector_9+0x46>
 			pwm_led++;
- 1f8:	80 91 64 00 	lds	r24, 0x0064
- 1fc:	90 91 65 00 	lds	r25, 0x0065
- 200:	01 96       	adiw	r24, 0x01	; 1
- 202:	90 93 65 00 	sts	0x0065, r25
- 206:	80 93 64 00 	sts	0x0064, r24
- 20a:	0a c0       	rjmp	.+20     	; 0x220 <__vector_9+0x5a>
+ 1fc:	80 91 64 00 	lds	r24, 0x0064
+ 200:	90 91 65 00 	lds	r25, 0x0065
+ 204:	01 96       	adiw	r24, 0x01	; 1
+ 206:	90 93 65 00 	sts	0x0065, r25
+ 20a:	80 93 64 00 	sts	0x0064, r24
+ 20e:	0a c0       	rjmp	.+20     	; 0x224 <__vector_9+0x5a>
 		} else {
 			DDRB |= (1<<PB0);
- 20c:	b8 9a       	sbi	0x17, 0	; 23
+ 210:	b8 9a       	sbi	0x17, 0	; 23
 			if(PINB & (1<<PINB0)) {
- 20e:	b0 9b       	sbis	0x16, 0	; 22
- 210:	02 c0       	rjmp	.+4      	; 0x216 <__vector_9+0x50>
+ 212:	b0 9b       	sbis	0x16, 0	; 22
+ 214:	02 c0       	rjmp	.+4      	; 0x21a <__vector_9+0x50>
 				PORTB &= ~(1<<PB0);
- 212:	c0 98       	cbi	0x18, 0	; 24
- 214:	01 c0       	rjmp	.+2      	; 0x218 <__vector_9+0x52>
+ 216:	c0 98       	cbi	0x18, 0	; 24
+ 218:	01 c0       	rjmp	.+2      	; 0x21c <__vector_9+0x52>
 			} else {
 				PORTB |= (1<<PB0);
- 216:	c0 9a       	sbi	0x18, 0	; 24
+ 21a:	c0 9a       	sbi	0x18, 0	; 24
 			}
 			pwm_led = 0;
- 218:	10 92 65 00 	sts	0x0065, r1
- 21c:	10 92 64 00 	sts	0x0064, r1
+ 21c:	10 92 65 00 	sts	0x0065, r1
+ 220:	10 92 64 00 	sts	0x0064, r1
 		}
 	}
 	if(status == ACTIVE) {
- 220:	80 91 60 00 	lds	r24, 0x0060
- 224:	90 91 61 00 	lds	r25, 0x0061
- 228:	83 30       	cpi	r24, 0x03	; 3
- 22a:	91 05       	cpc	r25, r1
- 22c:	d9 f4       	brne	.+54     	; 0x264 <__vector_9+0x9e>
+ 224:	80 91 62 00 	lds	r24, 0x0062
+ 228:	90 91 63 00 	lds	r25, 0x0063
+ 22c:	83 30       	cpi	r24, 0x03	; 3
+ 22e:	91 05       	cpc	r25, r1
+ 230:	d9 f4       	brne	.+54     	; 0x268 <__vector_9+0x9e>
 		if(pwm_led < 5) {
- 22e:	80 91 64 00 	lds	r24, 0x0064
- 232:	90 91 65 00 	lds	r25, 0x0065
- 236:	85 30       	cpi	r24, 0x05	; 5
- 238:	91 05       	cpc	r25, r1
- 23a:	54 f4       	brge	.+20     	; 0x250 <__vector_9+0x8a>
+ 232:	80 91 64 00 	lds	r24, 0x0064
+ 236:	90 91 65 00 	lds	r25, 0x0065
+ 23a:	85 30       	cpi	r24, 0x05	; 5
+ 23c:	91 05       	cpc	r25, r1
+ 23e:	54 f4       	brge	.+20     	; 0x254 <__vector_9+0x8a>
 			pwm_led++;
- 23c:	80 91 64 00 	lds	r24, 0x0064
- 240:	90 91 65 00 	lds	r25, 0x0065
- 244:	01 96       	adiw	r24, 0x01	; 1
- 246:	90 93 65 00 	sts	0x0065, r25
- 24a:	80 93 64 00 	sts	0x0064, r24
- 24e:	0a c0       	rjmp	.+20     	; 0x264 <__vector_9+0x9e>
+ 240:	80 91 64 00 	lds	r24, 0x0064
+ 244:	90 91 65 00 	lds	r25, 0x0065
+ 248:	01 96       	adiw	r24, 0x01	; 1
+ 24a:	90 93 65 00 	sts	0x0065, r25
+ 24e:	80 93 64 00 	sts	0x0064, r24
+ 252:	0a c0       	rjmp	.+20     	; 0x268 <__vector_9+0x9e>
 		} else {
 			DDRB |= (1<<PB0);
- 250:	b8 9a       	sbi	0x17, 0	; 23
+ 254:	b8 9a       	sbi	0x17, 0	; 23
 			if(PINB & (1<<PINB0)) {
- 252:	b0 9b       	sbis	0x16, 0	; 22
- 254:	02 c0       	rjmp	.+4      	; 0x25a <__vector_9+0x94>
+ 256:	b0 9b       	sbis	0x16, 0	; 22
+ 258:	02 c0       	rjmp	.+4      	; 0x25e <__vector_9+0x94>
 				PORTB &= ~(1<<PB0);
- 256:	c0 98       	cbi	0x18, 0	; 24
- 258:	01 c0       	rjmp	.+2      	; 0x25c <__vector_9+0x96>
+ 25a:	c0 98       	cbi	0x18, 0	; 24
+ 25c:	01 c0       	rjmp	.+2      	; 0x260 <__vector_9+0x96>
 			} else {
 				PORTB |= (1<<PB0);
- 25a:	c0 9a       	sbi	0x18, 0	; 24
+ 25e:	c0 9a       	sbi	0x18, 0	; 24
 			}
 			pwm_led = 0;
- 25c:	10 92 65 00 	sts	0x0065, r1
- 260:	10 92 64 00 	sts	0x0064, r1
+ 260:	10 92 65 00 	sts	0x0065, r1
+ 264:	10 92 64 00 	sts	0x0064, r1
 		}
 	}
 	if(status == RUN) {
- 264:	80 91 60 00 	lds	r24, 0x0060
- 268:	90 91 61 00 	lds	r25, 0x0061
- 26c:	86 30       	cpi	r24, 0x06	; 6
- 26e:	91 05       	cpc	r25, r1
- 270:	d9 f4       	brne	.+54     	; 0x2a8 <__vector_9+0xe2>
+ 268:	80 91 62 00 	lds	r24, 0x0062
+ 26c:	90 91 63 00 	lds	r25, 0x0063
+ 270:	86 30       	cpi	r24, 0x06	; 6
+ 272:	91 05       	cpc	r25, r1
+ 274:	d9 f4       	brne	.+54     	; 0x2ac <__vector_9+0xe2>
 		if(pwm_led < 1) {
- 272:	80 91 64 00 	lds	r24, 0x0064
- 276:	90 91 65 00 	lds	r25, 0x0065
- 27a:	18 16       	cp	r1, r24
- 27c:	19 06       	cpc	r1, r25
- 27e:	54 f0       	brlt	.+20     	; 0x294 <__vector_9+0xce>
+ 276:	80 91 64 00 	lds	r24, 0x0064
+ 27a:	90 91 65 00 	lds	r25, 0x0065
+ 27e:	18 16       	cp	r1, r24
+ 280:	19 06       	cpc	r1, r25
+ 282:	54 f0       	brlt	.+20     	; 0x298 <__vector_9+0xce>
 			pwm_led++;
- 280:	80 91 64 00 	lds	r24, 0x0064
- 284:	90 91 65 00 	lds	r25, 0x0065
- 288:	01 96       	adiw	r24, 0x01	; 1
- 28a:	90 93 65 00 	sts	0x0065, r25
- 28e:	80 93 64 00 	sts	0x0064, r24
- 292:	0a c0       	rjmp	.+20     	; 0x2a8 <__vector_9+0xe2>
+ 284:	80 91 64 00 	lds	r24, 0x0064
+ 288:	90 91 65 00 	lds	r25, 0x0065
+ 28c:	01 96       	adiw	r24, 0x01	; 1
+ 28e:	90 93 65 00 	sts	0x0065, r25
+ 292:	80 93 64 00 	sts	0x0064, r24
+ 296:	0a c0       	rjmp	.+20     	; 0x2ac <__vector_9+0xe2>
 		} else {
 			DDRB |= (1<<PB0);
- 294:	b8 9a       	sbi	0x17, 0	; 23
+ 298:	b8 9a       	sbi	0x17, 0	; 23
 			if(PINB & (1<<PINB0)) {
- 296:	b0 9b       	sbis	0x16, 0	; 22
- 298:	02 c0       	rjmp	.+4      	; 0x29e <__vector_9+0xd8>
+ 29a:	b0 9b       	sbis	0x16, 0	; 22
+ 29c:	02 c0       	rjmp	.+4      	; 0x2a2 <__vector_9+0xd8>
 				PORTB &= ~(1<<PB0);
- 29a:	c0 98       	cbi	0x18, 0	; 24
- 29c:	01 c0       	rjmp	.+2      	; 0x2a0 <__vector_9+0xda>
+ 29e:	c0 98       	cbi	0x18, 0	; 24
+ 2a0:	01 c0       	rjmp	.+2      	; 0x2a4 <__vector_9+0xda>
 			} else {
 				PORTB |= (1<<PB0);
- 29e:	c0 9a       	sbi	0x18, 0	; 24
+ 2a2:	c0 9a       	sbi	0x18, 0	; 24
 			}
 			pwm_led = 0;
- 2a0:	10 92 65 00 	sts	0x0065, r1
- 2a4:	10 92 64 00 	sts	0x0064, r1
+ 2a4:	10 92 65 00 	sts	0x0065, r1
+ 2a8:	10 92 64 00 	sts	0x0064, r1
 		}
 	}
 	
 	DDRB |= (1<<PB1);
- 2a8:	b9 9a       	sbi	0x17, 1	; 23
+ 2ac:	b9 9a       	sbi	0x17, 1	; 23
 	PORTB |= (1<<PB1);
- 2aa:	c1 9a       	sbi	0x18, 1	; 24
+ 2ae:	c1 9a       	sbi	0x18, 1	; 24
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
- 2ac:	8f ea       	ldi	r24, 0xAF	; 175
- 2ae:	94 e0       	ldi	r25, 0x04	; 4
- 2b0:	01 97       	sbiw	r24, 0x01	; 1
- 2b2:	f1 f7       	brne	.-4      	; 0x2b0 <__vector_9+0xea>
- 2b4:	00 c0       	rjmp	.+0      	; 0x2b6 <__vector_9+0xf0>
- 2b6:	00 00       	nop
+ 2b0:	8f ea       	ldi	r24, 0xAF	; 175
+ 2b2:	94 e0       	ldi	r25, 0x04	; 4
+ 2b4:	01 97       	sbiw	r24, 0x01	; 1
+ 2b6:	f1 f7       	brne	.-4      	; 0x2b4 <__vector_9+0xea>
+ 2b8:	00 c0       	rjmp	.+0      	; 0x2ba <__vector_9+0xf0>
+ 2ba:	00 00       	nop
 	_delay_us(LEFT);
 	for(int i=0;i<servopos;i++) {
- 2b8:	80 91 62 00 	lds	r24, 0x0062
- 2bc:	90 91 63 00 	lds	r25, 0x0063
- 2c0:	18 16       	cp	r1, r24
- 2c2:	19 06       	cpc	r1, r25
- 2c4:	74 f4       	brge	.+28     	; 0x2e2 <__vector_9+0x11c>
- 2c6:	80 e0       	ldi	r24, 0x00	; 0
- 2c8:	90 e0       	ldi	r25, 0x00	; 0
- 2ca:	25 e1       	ldi	r18, 0x15	; 21
- 2cc:	2a 95       	dec	r18
- 2ce:	f1 f7       	brne	.-4      	; 0x2cc <__vector_9+0x106>
- 2d0:	00 00       	nop
- 2d2:	01 96       	adiw	r24, 0x01	; 1
- 2d4:	20 91 62 00 	lds	r18, 0x0062
- 2d8:	30 91 63 00 	lds	r19, 0x0063
- 2dc:	82 17       	cp	r24, r18
- 2de:	93 07       	cpc	r25, r19
- 2e0:	a4 f3       	brlt	.-24     	; 0x2ca <__vector_9+0x104>
+ 2bc:	80 91 60 00 	lds	r24, 0x0060
+ 2c0:	90 91 61 00 	lds	r25, 0x0061
+ 2c4:	18 16       	cp	r1, r24
+ 2c6:	19 06       	cpc	r1, r25
+ 2c8:	74 f4       	brge	.+28     	; 0x2e6 <__vector_9+0x11c>
+ 2ca:	80 e0       	ldi	r24, 0x00	; 0
+ 2cc:	90 e0       	ldi	r25, 0x00	; 0
+ 2ce:	25 e1       	ldi	r18, 0x15	; 21
+ 2d0:	2a 95       	dec	r18
+ 2d2:	f1 f7       	brne	.-4      	; 0x2d0 <__vector_9+0x106>
+ 2d4:	00 00       	nop
+ 2d6:	01 96       	adiw	r24, 0x01	; 1
+ 2d8:	20 91 60 00 	lds	r18, 0x0060
+ 2dc:	30 91 61 00 	lds	r19, 0x0061
+ 2e0:	82 17       	cp	r24, r18
+ 2e2:	93 07       	cpc	r25, r19
+ 2e4:	a4 f3       	brlt	.-24     	; 0x2ce <__vector_9+0x104>
 		_delay_us(STEP);
 	}
 	PORTB &= ~(1<<PB1);
- 2e2:	c1 98       	cbi	0x18, 1	; 24
+ 2e6:	c1 98       	cbi	0x18, 1	; 24
 }
- 2e4:	9f 91       	pop	r25
- 2e6:	8f 91       	pop	r24
- 2e8:	3f 91       	pop	r19
- 2ea:	2f 91       	pop	r18
- 2ec:	0f 90       	pop	r0
- 2ee:	0f be       	out	0x3f, r0	; 63
+ 2e8:	9f 91       	pop	r25
+ 2ea:	8f 91       	pop	r24
+ 2ec:	3f 91       	pop	r19
+ 2ee:	2f 91       	pop	r18
  2f0:	0f 90       	pop	r0
- 2f2:	1f 90       	pop	r1
- 2f4:	18 95       	reti
+ 2f2:	0f be       	out	0x3f, r0	; 63
+ 2f4:	0f 90       	pop	r0
+ 2f6:	1f 90       	pop	r1
+ 2f8:	18 95       	reti
 
-000002f6 <main>:
+000002fa <main>:
 
 int main(void)
 {
 	
 	rf12_init();					// ein paar Register setzen (z.B. CLK auf 10MHz)
- 2f6:	0e 94 ad 01 	call	0x35a	; 0x35a <rf12_init>
+ 2fa:	0e 94 af 01 	call	0x35e	; 0x35e <rf12_init>
 	rf12_setfreq(RF12FREQ(433.92));	// Sende/Empfangsfrequenz auf 433,92MHz einstellen
- 2fa:	80 e2       	ldi	r24, 0x20	; 32
- 2fc:	96 e0       	ldi	r25, 0x06	; 6
- 2fe:	0e 94 f5 01 	call	0x3ea	; 0x3ea <rf12_setfreq>
+ 2fe:	80 e2       	ldi	r24, 0x20	; 32
+ 300:	96 e0       	ldi	r25, 0x06	; 6
+ 302:	0e 94 f7 01 	call	0x3ee	; 0x3ee <rf12_setfreq>
 	rf12_setbandwidth(1, 0, 7);		// 400kHz Bandbreite, 0dB Verstärkung, DRSSI threshold: -61dBm
- 302:	81 e0       	ldi	r24, 0x01	; 1
- 304:	60 e0       	ldi	r22, 0x00	; 0
- 306:	47 e0       	ldi	r20, 0x07	; 7
- 308:	0e 94 d7 01 	call	0x3ae	; 0x3ae <rf12_setbandwidth>
+ 306:	81 e0       	ldi	r24, 0x01	; 1
+ 308:	60 e0       	ldi	r22, 0x00	; 0
+ 30a:	47 e0       	ldi	r20, 0x07	; 7
+ 30c:	0e 94 d9 01 	call	0x3b2	; 0x3b2 <rf12_setbandwidth>
 	rf12_setbaud(9600);				// 19200 baud
- 30c:	80 e8       	ldi	r24, 0x80	; 128
- 30e:	95 e2       	ldi	r25, 0x25	; 37
- 310:	0e 94 05 02 	call	0x40a	; 0x40a <rf12_setbaud>
+ 310:	80 e8       	ldi	r24, 0x80	; 128
+ 312:	95 e2       	ldi	r25, 0x25	; 37
+ 314:	0e 94 07 02 	call	0x40e	; 0x40e <rf12_setbaud>
 	rf12_setpower(0, 6);			// 1mW Ausgangsleistung, 120kHz Frequenzshift
- 314:	80 e0       	ldi	r24, 0x00	; 0
- 316:	66 e0       	ldi	r22, 0x06	; 6
- 318:	0e 94 2c 02 	call	0x458	; 0x458 <rf12_setpower>
+ 318:	80 e0       	ldi	r24, 0x00	; 0
+ 31a:	66 e0       	ldi	r22, 0x06	; 6
+ 31c:	0e 94 2e 02 	call	0x45c	; 0x45c <rf12_setpower>
 	//rf12_ready();
 		
 	init_timer();
- 31c:	0e 94 db 00 	call	0x1b6	; 0x1b6 <init_timer>
+ 320:	0e 94 dd 00 	call	0x1ba	; 0x1ba <init_timer>
 	sei();
- 320:	78 94       	sei
+ 324:	78 94       	sei
 	
 	
 	//DDRB |= (1<<PINB0);
     while(1)
     {
 		recive();
- 322:	0e 94 84 00 	call	0x108	; 0x108 <recive>
- 326:	fd cf       	rjmp	.-6      	; 0x322 <main+0x2c>
+ 326:	0e 94 86 00 	call	0x10c	; 0x10c <recive>
+ 32a:	fd cf       	rjmp	.-6      	; 0x326 <main+0x2c>
 
-00000328 <rf12_trans>:
+0000032c <rf12_trans>:
 unsigned short rf12_trans(unsigned short wert)
 {	
 	unsigned short werti = 0;
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
- 328:	94 98       	cbi	0x12, 4	; 18
- 32a:	40 e1       	ldi	r20, 0x10	; 16
+ 32c:	94 98       	cbi	0x12, 4	; 18
+ 32e:	40 e1       	ldi	r20, 0x10	; 16
 #include "rf12.h"
 #include <util/delay.h>
 
 unsigned short rf12_trans(unsigned short wert)
 {	
 	unsigned short werti = 0;
- 32c:	20 e0       	ldi	r18, 0x00	; 0
- 32e:	30 e0       	ldi	r19, 0x00	; 0
+ 330:	20 e0       	ldi	r18, 0x00	; 0
+ 332:	30 e0       	ldi	r19, 0x00	; 0
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
 	for (i=0; i<16; i++)
 	{	
 		if (wert&32768) {
- 330:	99 23       	and	r25, r25
- 332:	14 f4       	brge	.+4      	; 0x338 <rf12_trans+0x10>
+ 334:	99 23       	and	r25, r25
+ 336:	14 f4       	brge	.+4      	; 0x33c <rf12_trans+0x10>
 			RF_PORT |= (1<<SDI);
- 334:	96 9a       	sbi	0x12, 6	; 18
- 336:	01 c0       	rjmp	.+2      	; 0x33a <rf12_trans+0x12>
+ 338:	96 9a       	sbi	0x12, 6	; 18
+ 33a:	01 c0       	rjmp	.+2      	; 0x33e <rf12_trans+0x12>
 		}		
 		else {
 			RF_PORT &= ~(1<<SDI);
- 338:	96 98       	cbi	0x12, 6	; 18
+ 33c:	96 98       	cbi	0x12, 6	; 18
 		}			
 		werti<<=1;
- 33a:	22 0f       	add	r18, r18
- 33c:	33 1f       	adc	r19, r19
+ 33e:	22 0f       	add	r18, r18
+ 340:	33 1f       	adc	r19, r19
 		if (RF_PIN & (1<<SDO)) {
- 33e:	83 99       	sbic	0x10, 3	; 16
+ 342:	83 99       	sbic	0x10, 3	; 16
 			werti|=1;
- 340:	21 60       	ori	r18, 0x01	; 1
+ 344:	21 60       	ori	r18, 0x01	; 1
 		}		
 		RF_PORT |= (1<<SCK);
- 342:	95 9a       	sbi	0x12, 5	; 18
+ 346:	95 9a       	sbi	0x12, 5	; 18
 		wert<<=1;
- 344:	88 0f       	add	r24, r24
- 346:	99 1f       	adc	r25, r25
- 348:	00 c0       	rjmp	.+0      	; 0x34a <rf12_trans+0x22>
- 34a:	00 00       	nop
+ 348:	88 0f       	add	r24, r24
+ 34a:	99 1f       	adc	r25, r25
+ 34c:	00 c0       	rjmp	.+0      	; 0x34e <rf12_trans+0x22>
+ 34e:	00 00       	nop
 		_delay_us(0.3);
 		RF_PORT &= ~(1<<SCK);
- 34c:	95 98       	cbi	0x12, 5	; 18
- 34e:	41 50       	subi	r20, 0x01	; 1
+ 350:	95 98       	cbi	0x12, 5	; 18
+ 352:	41 50       	subi	r20, 0x01	; 1
 {	
 	unsigned short werti = 0;
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
 	for (i=0; i<16; i++)
- 350:	79 f7       	brne	.-34     	; 0x330 <rf12_trans+0x8>
+ 354:	79 f7       	brne	.-34     	; 0x334 <rf12_trans+0x8>
 		RF_PORT |= (1<<SCK);
 		wert<<=1;
 		_delay_us(0.3);
 		RF_PORT &= ~(1<<SCK);
 	}
 	RF_PORT |= (1<<CS);
- 352:	94 9a       	sbi	0x12, 4	; 18
+ 356:	94 9a       	sbi	0x12, 4	; 18
 	return werti;
 }
- 354:	82 2f       	mov	r24, r18
- 356:	93 2f       	mov	r25, r19
- 358:	08 95       	ret
+ 358:	82 2f       	mov	r24, r18
+ 35a:	93 2f       	mov	r25, r19
+ 35c:	08 95       	ret
 
-0000035a <rf12_init>:
+0000035e <rf12_init>:
 
 void rf12_init(void)
 {
 	RF_DDR |= (1<<SDI) | (1<<SCK) | (1<<CS);
- 35a:	81 b3       	in	r24, 0x11	; 17
- 35c:	80 67       	ori	r24, 0x70	; 112
- 35e:	81 bb       	out	0x11, r24	; 17
+ 35e:	81 b3       	in	r24, 0x11	; 17
+ 360:	80 67       	ori	r24, 0x70	; 112
+ 362:	81 bb       	out	0x11, r24	; 17
 	RF_PORT |= (1<<CS);
- 360:	94 9a       	sbi	0x12, 4	; 18
+ 364:	94 9a       	sbi	0x12, 4	; 18
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
- 362:	8f ef       	ldi	r24, 0xFF	; 255
- 364:	90 e7       	ldi	r25, 0x70	; 112
- 366:	a2 e0       	ldi	r26, 0x02	; 2
- 368:	81 50       	subi	r24, 0x01	; 1
- 36a:	90 40       	sbci	r25, 0x00	; 0
- 36c:	a0 40       	sbci	r26, 0x00	; 0
- 36e:	e1 f7       	brne	.-8      	; 0x368 <rf12_init+0xe>
- 370:	00 c0       	rjmp	.+0      	; 0x372 <rf12_init+0x18>
- 372:	00 00       	nop
+ 366:	8f ef       	ldi	r24, 0xFF	; 255
+ 368:	90 e7       	ldi	r25, 0x70	; 112
+ 36a:	a2 e0       	ldi	r26, 0x02	; 2
+ 36c:	81 50       	subi	r24, 0x01	; 1
+ 36e:	90 40       	sbci	r25, 0x00	; 0
+ 370:	a0 40       	sbci	r26, 0x00	; 0
+ 372:	e1 f7       	brne	.-8      	; 0x36c <rf12_init+0xe>
+ 374:	00 c0       	rjmp	.+0      	; 0x376 <rf12_init+0x18>
+ 376:	00 00       	nop
 
 	_delay_ms(100);
 
 	rf12_trans(0xC0E0);			// AVR CLK: 10MHz
- 374:	80 ee       	ldi	r24, 0xE0	; 224
- 376:	90 ec       	ldi	r25, 0xC0	; 192
- 378:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 378:	80 ee       	ldi	r24, 0xE0	; 224
+ 37a:	90 ec       	ldi	r25, 0xC0	; 192
+ 37c:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0x80D7);			// Enable FIFO
- 37c:	87 ed       	ldi	r24, 0xD7	; 215
- 37e:	90 e8       	ldi	r25, 0x80	; 128
- 380:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 380:	87 ed       	ldi	r24, 0xD7	; 215
+ 382:	90 e8       	ldi	r25, 0x80	; 128
+ 384:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xC2AB);			// Data Filter: internal
- 384:	8b ea       	ldi	r24, 0xAB	; 171
- 386:	92 ec       	ldi	r25, 0xC2	; 194
- 388:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 388:	8b ea       	ldi	r24, 0xAB	; 171
+ 38a:	92 ec       	ldi	r25, 0xC2	; 194
+ 38c:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xCA81);			// Set FIFO mode
- 38c:	81 e8       	ldi	r24, 0x81	; 129
- 38e:	9a ec       	ldi	r25, 0xCA	; 202
- 390:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 390:	81 e8       	ldi	r24, 0x81	; 129
+ 392:	9a ec       	ldi	r25, 0xCA	; 202
+ 394:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xE000);			// disable wakeuptimer
- 394:	80 e0       	ldi	r24, 0x00	; 0
- 396:	90 ee       	ldi	r25, 0xE0	; 224
- 398:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 398:	80 e0       	ldi	r24, 0x00	; 0
+ 39a:	90 ee       	ldi	r25, 0xE0	; 224
+ 39c:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xC800);			// disable low duty cycle
- 39c:	80 e0       	ldi	r24, 0x00	; 0
- 39e:	98 ec       	ldi	r25, 0xC8	; 200
- 3a0:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 3a0:	80 e0       	ldi	r24, 0x00	; 0
+ 3a2:	98 ec       	ldi	r25, 0xC8	; 200
+ 3a4:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xC4F7);			// AFC settings: autotuning: -10kHz...+7,5kHz
- 3a4:	87 ef       	ldi	r24, 0xF7	; 247
- 3a6:	94 ec       	ldi	r25, 0xC4	; 196
- 3a8:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 3a8:	87 ef       	ldi	r24, 0xF7	; 247
+ 3aa:	94 ec       	ldi	r25, 0xC4	; 196
+ 3ac:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 3ac:	08 95       	ret
+ 3b0:	08 95       	ret
 
-000003ae <rf12_setbandwidth>:
+000003b2 <rf12_setbandwidth>:
 
 void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
 {
 	rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
- 3ae:	90 e0       	ldi	r25, 0x00	; 0
- 3b0:	88 0f       	add	r24, r24
- 3b2:	99 1f       	adc	r25, r25
- 3b4:	82 95       	swap	r24
- 3b6:	92 95       	swap	r25
- 3b8:	90 7f       	andi	r25, 0xF0	; 240
- 3ba:	98 27       	eor	r25, r24
- 3bc:	80 7f       	andi	r24, 0xF0	; 240
+ 3b2:	90 e0       	ldi	r25, 0x00	; 0
+ 3b4:	88 0f       	add	r24, r24
+ 3b6:	99 1f       	adc	r25, r25
+ 3b8:	82 95       	swap	r24
+ 3ba:	92 95       	swap	r25
+ 3bc:	90 7f       	andi	r25, 0xF0	; 240
  3be:	98 27       	eor	r25, r24
- 3c0:	90 70       	andi	r25, 0x00	; 0
- 3c2:	50 e0       	ldi	r21, 0x00	; 0
- 3c4:	47 70       	andi	r20, 0x07	; 7
- 3c6:	50 70       	andi	r21, 0x00	; 0
- 3c8:	84 2b       	or	r24, r20
- 3ca:	95 2b       	or	r25, r21
- 3cc:	94 69       	ori	r25, 0x94	; 148
- 3ce:	70 e0       	ldi	r23, 0x00	; 0
- 3d0:	63 70       	andi	r22, 0x03	; 3
- 3d2:	70 70       	andi	r23, 0x00	; 0
- 3d4:	66 0f       	add	r22, r22
- 3d6:	77 1f       	adc	r23, r23
+ 3c0:	80 7f       	andi	r24, 0xF0	; 240
+ 3c2:	98 27       	eor	r25, r24
+ 3c4:	90 70       	andi	r25, 0x00	; 0
+ 3c6:	50 e0       	ldi	r21, 0x00	; 0
+ 3c8:	47 70       	andi	r20, 0x07	; 7
+ 3ca:	50 70       	andi	r21, 0x00	; 0
+ 3cc:	84 2b       	or	r24, r20
+ 3ce:	95 2b       	or	r25, r21
+ 3d0:	94 69       	ori	r25, 0x94	; 148
+ 3d2:	70 e0       	ldi	r23, 0x00	; 0
+ 3d4:	63 70       	andi	r22, 0x03	; 3
+ 3d6:	70 70       	andi	r23, 0x00	; 0
  3d8:	66 0f       	add	r22, r22
  3da:	77 1f       	adc	r23, r23
  3dc:	66 0f       	add	r22, r22
  3de:	77 1f       	adc	r23, r23
- 3e0:	86 2b       	or	r24, r22
- 3e2:	97 2b       	or	r25, r23
- 3e4:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 3e0:	66 0f       	add	r22, r22
+ 3e2:	77 1f       	adc	r23, r23
+ 3e4:	86 2b       	or	r24, r22
+ 3e6:	97 2b       	or	r25, r23
+ 3e8:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 3e8:	08 95       	ret
+ 3ec:	08 95       	ret
 
-000003ea <rf12_setfreq>:
+000003ee <rf12_setfreq>:
 
 void rf12_setfreq(unsigned short freq)
 {	
 	if (freq<96) {				// 430,2400MHz
- 3ea:	80 36       	cpi	r24, 0x60	; 96
- 3ec:	91 05       	cpc	r25, r1
- 3ee:	38 f0       	brcs	.+14     	; 0x3fe <rf12_setfreq+0x14>
- 3f0:	2f e0       	ldi	r18, 0x0F	; 15
- 3f2:	80 34       	cpi	r24, 0x40	; 64
- 3f4:	92 07       	cpc	r25, r18
- 3f6:	28 f0       	brcs	.+10     	; 0x402 <rf12_setfreq+0x18>
- 3f8:	8f e3       	ldi	r24, 0x3F	; 63
- 3fa:	9f e0       	ldi	r25, 0x0F	; 15
- 3fc:	02 c0       	rjmp	.+4      	; 0x402 <rf12_setfreq+0x18>
+ 3ee:	80 36       	cpi	r24, 0x60	; 96
+ 3f0:	91 05       	cpc	r25, r1
+ 3f2:	38 f0       	brcs	.+14     	; 0x402 <rf12_setfreq+0x14>
+ 3f4:	2f e0       	ldi	r18, 0x0F	; 15
+ 3f6:	80 34       	cpi	r24, 0x40	; 64
+ 3f8:	92 07       	cpc	r25, r18
+ 3fa:	28 f0       	brcs	.+10     	; 0x406 <rf12_setfreq+0x18>
+ 3fc:	8f e3       	ldi	r24, 0x3F	; 63
+ 3fe:	9f e0       	ldi	r25, 0x0F	; 15
+ 400:	02 c0       	rjmp	.+4      	; 0x406 <rf12_setfreq+0x18>
 		freq=96;
- 3fe:	80 e6       	ldi	r24, 0x60	; 96
- 400:	90 e0       	ldi	r25, 0x00	; 0
+ 402:	80 e6       	ldi	r24, 0x60	; 96
+ 404:	90 e0       	ldi	r25, 0x00	; 0
 	} else if (freq>3903) {		// 439,7575MHz
 		freq=3903;
 	}	
 	rf12_trans(0xA000|freq);
- 402:	90 6a       	ori	r25, 0xA0	; 160
- 404:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 406:	90 6a       	ori	r25, 0xA0	; 160
+ 408:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 408:	08 95       	ret
+ 40c:	08 95       	ret
 
-0000040a <rf12_setbaud>:
+0000040e <rf12_setbaud>:
 
 void rf12_setbaud(unsigned short baud)
 {
 	if (baud<663) {
- 40a:	22 e0       	ldi	r18, 0x02	; 2
- 40c:	87 39       	cpi	r24, 0x97	; 151
- 40e:	92 07       	cpc	r25, r18
- 410:	10 f1       	brcs	.+68     	; 0x456 <rf12_setbaud+0x4c>
+ 40e:	22 e0       	ldi	r18, 0x02	; 2
+ 410:	87 39       	cpi	r24, 0x97	; 151
+ 412:	92 07       	cpc	r25, r18
+ 414:	10 f1       	brcs	.+68     	; 0x45a <rf12_setbaud+0x4c>
 		return;
 	}	
 	if (baud<5400) {				// Baudrate= 344827,58621/(R+1)/(1+CS*7)
- 412:	25 e1       	ldi	r18, 0x15	; 21
- 414:	88 31       	cpi	r24, 0x18	; 24
- 416:	92 07       	cpc	r25, r18
- 418:	80 f4       	brcc	.+32     	; 0x43a <rf12_setbaud+0x30>
+ 416:	25 e1       	ldi	r18, 0x15	; 21
+ 418:	88 31       	cpi	r24, 0x18	; 24
+ 41a:	92 07       	cpc	r25, r18
+ 41c:	80 f4       	brcc	.+32     	; 0x43e <rf12_setbaud+0x30>
 		rf12_trans(0xC680|((43104/baud)-1));
- 41a:	9c 01       	movw	r18, r24
- 41c:	40 e0       	ldi	r20, 0x00	; 0
- 41e:	50 e0       	ldi	r21, 0x00	; 0
- 420:	60 e6       	ldi	r22, 0x60	; 96
- 422:	78 ea       	ldi	r23, 0xA8	; 168
- 424:	80 e0       	ldi	r24, 0x00	; 0
- 426:	90 e0       	ldi	r25, 0x00	; 0
- 428:	0e 94 4d 03 	call	0x69a	; 0x69a <__divmodsi4>
- 42c:	c9 01       	movw	r24, r18
- 42e:	01 97       	sbiw	r24, 0x01	; 1
- 430:	80 68       	ori	r24, 0x80	; 128
- 432:	96 6c       	ori	r25, 0xC6	; 198
- 434:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
- 438:	08 95       	ret
+ 41e:	9c 01       	movw	r18, r24
+ 420:	40 e0       	ldi	r20, 0x00	; 0
+ 422:	50 e0       	ldi	r21, 0x00	; 0
+ 424:	60 e6       	ldi	r22, 0x60	; 96
+ 426:	78 ea       	ldi	r23, 0xA8	; 168
+ 428:	80 e0       	ldi	r24, 0x00	; 0
+ 42a:	90 e0       	ldi	r25, 0x00	; 0
+ 42c:	0e 94 4f 03 	call	0x69e	; 0x69e <__divmodsi4>
+ 430:	c9 01       	movw	r24, r18
+ 432:	01 97       	sbiw	r24, 0x01	; 1
+ 434:	80 68       	ori	r24, 0x80	; 128
+ 436:	96 6c       	ori	r25, 0xC6	; 198
+ 438:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
+ 43c:	08 95       	ret
 	} else {
 		rf12_trans(0xC600|((344828UL/baud)-1));
- 43a:	9c 01       	movw	r18, r24
- 43c:	40 e0       	ldi	r20, 0x00	; 0
- 43e:	50 e0       	ldi	r21, 0x00	; 0
- 440:	6c ef       	ldi	r22, 0xFC	; 252
- 442:	72 e4       	ldi	r23, 0x42	; 66
- 444:	85 e0       	ldi	r24, 0x05	; 5
- 446:	90 e0       	ldi	r25, 0x00	; 0
- 448:	0e 94 2b 03 	call	0x656	; 0x656 <__udivmodsi4>
- 44c:	c9 01       	movw	r24, r18
- 44e:	01 97       	sbiw	r24, 0x01	; 1
- 450:	96 6c       	ori	r25, 0xC6	; 198
- 452:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
- 456:	08 95       	ret
+ 43e:	9c 01       	movw	r18, r24
+ 440:	40 e0       	ldi	r20, 0x00	; 0
+ 442:	50 e0       	ldi	r21, 0x00	; 0
+ 444:	6c ef       	ldi	r22, 0xFC	; 252
+ 446:	72 e4       	ldi	r23, 0x42	; 66
+ 448:	85 e0       	ldi	r24, 0x05	; 5
+ 44a:	90 e0       	ldi	r25, 0x00	; 0
+ 44c:	0e 94 2d 03 	call	0x65a	; 0x65a <__udivmodsi4>
+ 450:	c9 01       	movw	r24, r18
+ 452:	01 97       	sbiw	r24, 0x01	; 1
+ 454:	96 6c       	ori	r25, 0xC6	; 198
+ 456:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
+ 45a:	08 95       	ret
 
-00000458 <rf12_setpower>:
+0000045c <rf12_setpower>:
 	}	
 }
 
 void rf12_setpower(unsigned char power, unsigned char mod)
 {
 	rf12_trans(0x9800|(power&7)|((mod&15)<<4));
- 458:	90 e0       	ldi	r25, 0x00	; 0
- 45a:	87 70       	andi	r24, 0x07	; 7
- 45c:	90 70       	andi	r25, 0x00	; 0
- 45e:	98 69       	ori	r25, 0x98	; 152
- 460:	70 e0       	ldi	r23, 0x00	; 0
- 462:	62 95       	swap	r22
- 464:	72 95       	swap	r23
- 466:	70 7f       	andi	r23, 0xF0	; 240
- 468:	76 27       	eor	r23, r22
- 46a:	60 7f       	andi	r22, 0xF0	; 240
+ 45c:	90 e0       	ldi	r25, 0x00	; 0
+ 45e:	87 70       	andi	r24, 0x07	; 7
+ 460:	90 70       	andi	r25, 0x00	; 0
+ 462:	98 69       	ori	r25, 0x98	; 152
+ 464:	70 e0       	ldi	r23, 0x00	; 0
+ 466:	62 95       	swap	r22
+ 468:	72 95       	swap	r23
+ 46a:	70 7f       	andi	r23, 0xF0	; 240
  46c:	76 27       	eor	r23, r22
- 46e:	70 70       	andi	r23, 0x00	; 0
- 470:	86 2b       	or	r24, r22
- 472:	97 2b       	or	r25, r23
- 474:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 46e:	60 7f       	andi	r22, 0xF0	; 240
+ 470:	76 27       	eor	r23, r22
+ 472:	70 70       	andi	r23, 0x00	; 0
+ 474:	86 2b       	or	r24, r22
+ 476:	97 2b       	or	r25, r23
+ 478:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 478:	08 95       	ret
+ 47c:	08 95       	ret
 
-0000047a <rf12_ready>:
+0000047e <rf12_ready>:
 
 void rf12_ready(void)
 {	
 	RF_PORT &= ~(1<<CS);
- 47a:	94 98       	cbi	0x12, 4	; 18
+ 47e:	94 98       	cbi	0x12, 4	; 18
 	while (!(RF_PIN & (1<<SDO))); // wait until FIFO ready
- 47c:	83 9b       	sbis	0x10, 3	; 16
- 47e:	fe cf       	rjmp	.-4      	; 0x47c <rf12_ready+0x2>
+ 480:	83 9b       	sbis	0x10, 3	; 16
+ 482:	fe cf       	rjmp	.-4      	; 0x480 <rf12_ready+0x2>
 }
- 480:	08 95       	ret
+ 484:	08 95       	ret
 
-00000482 <rf12_beginasyncrx>:
+00000486 <rf12_beginasyncrx>:
 
 void rf12_beginasyncrx() {
 	rf12_trans(0x82C8);			// RX on
- 482:	88 ec       	ldi	r24, 0xC8	; 200
- 484:	92 e8       	ldi	r25, 0x82	; 130
- 486:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 486:	88 ec       	ldi	r24, 0xC8	; 200
+ 488:	92 e8       	ldi	r25, 0x82	; 130
+ 48a:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xCA81);			// set FIFO mode
- 48a:	81 e8       	ldi	r24, 0x81	; 129
- 48c:	9a ec       	ldi	r25, 0xCA	; 202
- 48e:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 48e:	81 e8       	ldi	r24, 0x81	; 129
+ 490:	9a ec       	ldi	r25, 0xCA	; 202
+ 492:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xCA83);			// enable FIFO
- 492:	83 e8       	ldi	r24, 0x83	; 131
- 494:	9a ec       	ldi	r25, 0xCA	; 202
- 496:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 496:	83 e8       	ldi	r24, 0x83	; 131
+ 498:	9a ec       	ldi	r25, 0xCA	; 202
+ 49a:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 49a:	08 95       	ret
+ 49e:	08 95       	ret
 
-0000049c <rf12_hasdata>:
+000004a0 <rf12_hasdata>:
 uint8_t rf12_hasdata() {
 	RF_PORT &= ~(1<<CS);
- 49c:	94 98       	cbi	0x12, 4	; 18
+ 4a0:	94 98       	cbi	0x12, 4	; 18
 	return !(RF_PIN & (1<<SDO));
- 49e:	81 e0       	ldi	r24, 0x01	; 1
- 4a0:	83 99       	sbic	0x10, 3	; 16
- 4a2:	80 e0       	ldi	r24, 0x00	; 0
+ 4a2:	81 e0       	ldi	r24, 0x01	; 1
+ 4a4:	83 99       	sbic	0x10, 3	; 16
+ 4a6:	80 e0       	ldi	r24, 0x00	; 0
 }
- 4a4:	08 95       	ret
+ 4a8:	08 95       	ret
 
-000004a6 <rf12_rxbyte>:
+000004aa <rf12_rxbyte>:
 uint8_t rf12_rxbyte() {
 	return rf12_trans(0xB000);
- 4a6:	80 e0       	ldi	r24, 0x00	; 0
- 4a8:	90 eb       	ldi	r25, 0xB0	; 176
- 4aa:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4aa:	80 e0       	ldi	r24, 0x00	; 0
+ 4ac:	90 eb       	ldi	r25, 0xB0	; 176
+ 4ae:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 4ae:	08 95       	ret
+ 4b2:	08 95       	ret
 
-000004b0 <rf12_endasyncrx>:
+000004b4 <rf12_endasyncrx>:
 void rf12_endasyncrx() {
 	rf12_trans(0x8208);			// RX off
- 4b0:	88 e0       	ldi	r24, 0x08	; 8
- 4b2:	92 e8       	ldi	r25, 0x82	; 130
- 4b4:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4b4:	88 e0       	ldi	r24, 0x08	; 8
+ 4b6:	92 e8       	ldi	r25, 0x82	; 130
+ 4b8:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 4b8:	08 95       	ret
+ 4bc:	08 95       	ret
 
-000004ba <rf12_txdata>:
+000004be <rf12_txdata>:
 
 void rf12_txdata(unsigned char *data, unsigned char number)
 {	
- 4ba:	0f 93       	push	r16
- 4bc:	1f 93       	push	r17
- 4be:	cf 93       	push	r28
- 4c0:	df 93       	push	r29
- 4c2:	8c 01       	movw	r16, r24
- 4c4:	c6 2f       	mov	r28, r22
+ 4be:	0f 93       	push	r16
+ 4c0:	1f 93       	push	r17
+ 4c2:	cf 93       	push	r28
+ 4c4:	df 93       	push	r29
+ 4c6:	8c 01       	movw	r16, r24
+ 4c8:	c6 2f       	mov	r28, r22
 	unsigned char i;
 	rf12_trans(0x8238);			// TX on
- 4c6:	88 e3       	ldi	r24, 0x38	; 56
- 4c8:	92 e8       	ldi	r25, 0x82	; 130
- 4ca:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4ca:	88 e3       	ldi	r24, 0x38	; 56
+ 4cc:	92 e8       	ldi	r25, 0x82	; 130
+ 4ce:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 4ce:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 4d2:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 4d2:	8a ea       	ldi	r24, 0xAA	; 170
- 4d4:	98 eb       	ldi	r25, 0xB8	; 184
- 4d6:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4d6:	8a ea       	ldi	r24, 0xAA	; 170
+ 4d8:	98 eb       	ldi	r25, 0xB8	; 184
+ 4da:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 4da:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 4de:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 4de:	8a ea       	ldi	r24, 0xAA	; 170
- 4e0:	98 eb       	ldi	r25, 0xB8	; 184
- 4e2:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4e2:	8a ea       	ldi	r24, 0xAA	; 170
+ 4e4:	98 eb       	ldi	r25, 0xB8	; 184
+ 4e6:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 4e6:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 4ea:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 4ea:	8a ea       	ldi	r24, 0xAA	; 170
- 4ec:	98 eb       	ldi	r25, 0xB8	; 184
- 4ee:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4ee:	8a ea       	ldi	r24, 0xAA	; 170
+ 4f0:	98 eb       	ldi	r25, 0xB8	; 184
+ 4f2:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 4f2:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 4f6:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB82D);
- 4f6:	8d e2       	ldi	r24, 0x2D	; 45
- 4f8:	98 eb       	ldi	r25, 0xB8	; 184
- 4fa:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 4fa:	8d e2       	ldi	r24, 0x2D	; 45
+ 4fc:	98 eb       	ldi	r25, 0xB8	; 184
+ 4fe:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 4fe:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 502:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8D4);
- 502:	84 ed       	ldi	r24, 0xD4	; 212
- 504:	98 eb       	ldi	r25, 0xB8	; 184
- 506:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 506:	84 ed       	ldi	r24, 0xD4	; 212
+ 508:	98 eb       	ldi	r25, 0xB8	; 184
+ 50a:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	for (i=0; i<number; i++)
- 50a:	cc 23       	and	r28, r28
- 50c:	99 f0       	breq	.+38     	; 0x534 <rf12_txdata+0x7a>
+ 50e:	cc 23       	and	r28, r28
+ 510:	99 f0       	breq	.+38     	; 0x538 <rf12_txdata+0x7a>
 }
 void rf12_endasyncrx() {
 	rf12_trans(0x8208);			// RX off
 }
 
 void rf12_txdata(unsigned char *data, unsigned char number)
- 50e:	c8 01       	movw	r24, r16
- 510:	01 96       	adiw	r24, 0x01	; 1
- 512:	c1 50       	subi	r28, 0x01	; 1
- 514:	9c 01       	movw	r18, r24
- 516:	2c 0f       	add	r18, r28
- 518:	31 1d       	adc	r19, r1
- 51a:	e9 01       	movw	r28, r18
+ 512:	c8 01       	movw	r24, r16
+ 514:	01 96       	adiw	r24, 0x01	; 1
+ 516:	c1 50       	subi	r28, 0x01	; 1
+ 518:	9c 01       	movw	r18, r24
+ 51a:	2c 0f       	add	r18, r28
+ 51c:	31 1d       	adc	r19, r1
+ 51e:	e9 01       	movw	r28, r18
 	rf12_trans(0xB82D);
 	rf12_ready();
 	rf12_trans(0xB8D4);
 	for (i=0; i<number; i++)
 	{		
 		rf12_ready();
- 51c:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 520:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 		rf12_trans(0xB800|(*data++));
- 520:	f8 01       	movw	r30, r16
- 522:	81 91       	ld	r24, Z+
- 524:	8f 01       	movw	r16, r30
- 526:	90 e0       	ldi	r25, 0x00	; 0
- 528:	98 6b       	ori	r25, 0xB8	; 184
- 52a:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 524:	f8 01       	movw	r30, r16
+ 526:	81 91       	ld	r24, Z+
+ 528:	8f 01       	movw	r16, r30
+ 52a:	90 e0       	ldi	r25, 0x00	; 0
+ 52c:	98 6b       	ori	r25, 0xB8	; 184
+ 52e:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xB8AA);
 	rf12_ready();
 	rf12_trans(0xB82D);
 	rf12_ready();
 	rf12_trans(0xB8D4);
 	for (i=0; i<number; i++)
- 52e:	0c 17       	cp	r16, r28
- 530:	1d 07       	cpc	r17, r29
- 532:	a1 f7       	brne	.-24     	; 0x51c <rf12_txdata+0x62>
+ 532:	0c 17       	cp	r16, r28
+ 534:	1d 07       	cpc	r17, r29
+ 536:	a1 f7       	brne	.-24     	; 0x520 <rf12_txdata+0x62>
 	{		
 		rf12_ready();
 		rf12_trans(0xB800|(*data++));
 	}
 	rf12_ready();
- 534:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 538:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0x8208);			// TX off
- 538:	88 e0       	ldi	r24, 0x08	; 8
- 53a:	92 e8       	ldi	r25, 0x82	; 130
- 53c:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 53c:	88 e0       	ldi	r24, 0x08	; 8
+ 53e:	92 e8       	ldi	r25, 0x82	; 130
+ 540:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 540:	df 91       	pop	r29
- 542:	cf 91       	pop	r28
- 544:	1f 91       	pop	r17
- 546:	0f 91       	pop	r16
- 548:	08 95       	ret
+ 544:	df 91       	pop	r29
+ 546:	cf 91       	pop	r28
+ 548:	1f 91       	pop	r17
+ 54a:	0f 91       	pop	r16
+ 54c:	08 95       	ret
 
-0000054a <rf12_rxdata>:
+0000054e <rf12_rxdata>:
 
 void rf12_rxdata(unsigned char *data, unsigned char number)
 {	
- 54a:	0f 93       	push	r16
- 54c:	1f 93       	push	r17
- 54e:	cf 93       	push	r28
- 550:	df 93       	push	r29
- 552:	8c 01       	movw	r16, r24
- 554:	d6 2f       	mov	r29, r22
+ 54e:	0f 93       	push	r16
+ 550:	1f 93       	push	r17
+ 552:	cf 93       	push	r28
+ 554:	df 93       	push	r29
+ 556:	8c 01       	movw	r16, r24
+ 558:	d6 2f       	mov	r29, r22
 	unsigned char i;
 	rf12_trans(0x82C8);			// RX on
- 556:	88 ec       	ldi	r24, 0xC8	; 200
- 558:	92 e8       	ldi	r25, 0x82	; 130
- 55a:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 55a:	88 ec       	ldi	r24, 0xC8	; 200
+ 55c:	92 e8       	ldi	r25, 0x82	; 130
+ 55e:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xCA81);			// set FIFO mode
- 55e:	81 e8       	ldi	r24, 0x81	; 129
- 560:	9a ec       	ldi	r25, 0xCA	; 202
- 562:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 562:	81 e8       	ldi	r24, 0x81	; 129
+ 564:	9a ec       	ldi	r25, 0xCA	; 202
+ 566:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_trans(0xCA83);			// enable FIFO
- 566:	83 e8       	ldi	r24, 0x83	; 131
- 568:	9a ec       	ldi	r25, 0xCA	; 202
- 56a:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 56a:	83 e8       	ldi	r24, 0x83	; 131
+ 56c:	9a ec       	ldi	r25, 0xCA	; 202
+ 56e:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	for (i=0; i<number; i++)
- 56e:	dd 23       	and	r29, r29
- 570:	99 f0       	breq	.+38     	; 0x598 <rf12_rxdata+0x4e>
+ 572:	dd 23       	and	r29, r29
+ 574:	99 f0       	breq	.+38     	; 0x59c <rf12_rxdata+0x4e>
 	}
 	rf12_ready();
 	rf12_trans(0x8208);			// TX off
 }
 
 void rf12_rxdata(unsigned char *data, unsigned char number)
- 572:	c8 01       	movw	r24, r16
- 574:	01 96       	adiw	r24, 0x01	; 1
- 576:	d1 50       	subi	r29, 0x01	; 1
- 578:	9c 01       	movw	r18, r24
- 57a:	2d 0f       	add	r18, r29
- 57c:	31 1d       	adc	r19, r1
- 57e:	e9 01       	movw	r28, r18
+ 576:	c8 01       	movw	r24, r16
+ 578:	01 96       	adiw	r24, 0x01	; 1
+ 57a:	d1 50       	subi	r29, 0x01	; 1
+ 57c:	9c 01       	movw	r18, r24
+ 57e:	2d 0f       	add	r18, r29
+ 580:	31 1d       	adc	r19, r1
+ 582:	e9 01       	movw	r28, r18
 	rf12_trans(0x82C8);			// RX on
 	rf12_trans(0xCA81);			// set FIFO mode
 	rf12_trans(0xCA83);			// enable FIFO
 	for (i=0; i<number; i++)
 	{	
 		rf12_ready();
- 580:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 584:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 		*data++=rf12_trans(0xB000);
- 584:	80 e0       	ldi	r24, 0x00	; 0
- 586:	90 eb       	ldi	r25, 0xB0	; 176
- 588:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
- 58c:	f8 01       	movw	r30, r16
- 58e:	81 93       	st	Z+, r24
- 590:	8f 01       	movw	r16, r30
+ 588:	80 e0       	ldi	r24, 0x00	; 0
+ 58a:	90 eb       	ldi	r25, 0xB0	; 176
+ 58c:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
+ 590:	f8 01       	movw	r30, r16
+ 592:	81 93       	st	Z+, r24
+ 594:	8f 01       	movw	r16, r30
 {	
 	unsigned char i;
 	rf12_trans(0x82C8);			// RX on
 	rf12_trans(0xCA81);			// set FIFO mode
 	rf12_trans(0xCA83);			// enable FIFO
 	for (i=0; i<number; i++)
- 592:	ec 17       	cp	r30, r28
- 594:	fd 07       	cpc	r31, r29
- 596:	a1 f7       	brne	.-24     	; 0x580 <rf12_rxdata+0x36>
+ 596:	ec 17       	cp	r30, r28
+ 598:	fd 07       	cpc	r31, r29
+ 59a:	a1 f7       	brne	.-24     	; 0x584 <rf12_rxdata+0x36>
 	{	
 		rf12_ready();
 		*data++=rf12_trans(0xB000);
 	}
 	rf12_trans(0x8208);			// RX off
- 598:	88 e0       	ldi	r24, 0x08	; 8
- 59a:	92 e8       	ldi	r25, 0x82	; 130
- 59c:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 59c:	88 e0       	ldi	r24, 0x08	; 8
+ 59e:	92 e8       	ldi	r25, 0x82	; 130
+ 5a0:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 }
- 5a0:	df 91       	pop	r29
- 5a2:	cf 91       	pop	r28
- 5a4:	1f 91       	pop	r17
- 5a6:	0f 91       	pop	r16
- 5a8:	08 95       	ret
+ 5a4:	df 91       	pop	r29
+ 5a6:	cf 91       	pop	r28
+ 5a8:	1f 91       	pop	r17
+ 5aa:	0f 91       	pop	r16
+ 5ac:	08 95       	ret
 
-000005aa <rf12_txpacket>:
+000005ae <rf12_txpacket>:
 
 void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) {
- 5aa:	1f 93       	push	r17
- 5ac:	cf 93       	push	r28
- 5ae:	df 93       	push	r29
- 5b0:	18 2f       	mov	r17, r24
- 5b2:	d6 2f       	mov	r29, r22
- 5b4:	c4 2f       	mov	r28, r20
+ 5ae:	1f 93       	push	r17
+ 5b0:	cf 93       	push	r28
+ 5b2:	df 93       	push	r29
+ 5b4:	18 2f       	mov	r17, r24
+ 5b6:	d6 2f       	mov	r29, r22
+ 5b8:	c4 2f       	mov	r28, r20
 	rf12_trans(0x8238);			// TX on
- 5b6:	88 e3       	ldi	r24, 0x38	; 56
- 5b8:	92 e8       	ldi	r25, 0x82	; 130
- 5ba:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5ba:	88 e3       	ldi	r24, 0x38	; 56
+ 5bc:	92 e8       	ldi	r25, 0x82	; 130
+ 5be:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5be:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5c2:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 5c2:	8a ea       	ldi	r24, 0xAA	; 170
- 5c4:	98 eb       	ldi	r25, 0xB8	; 184
- 5c6:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5c6:	8a ea       	ldi	r24, 0xAA	; 170
+ 5c8:	98 eb       	ldi	r25, 0xB8	; 184
+ 5ca:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5ca:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5ce:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 5ce:	8a ea       	ldi	r24, 0xAA	; 170
- 5d0:	98 eb       	ldi	r25, 0xB8	; 184
- 5d2:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5d2:	8a ea       	ldi	r24, 0xAA	; 170
+ 5d4:	98 eb       	ldi	r25, 0xB8	; 184
+ 5d6:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5d6:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5da:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8AA);
- 5da:	8a ea       	ldi	r24, 0xAA	; 170
- 5dc:	98 eb       	ldi	r25, 0xB8	; 184
- 5de:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5de:	8a ea       	ldi	r24, 0xAA	; 170
+ 5e0:	98 eb       	ldi	r25, 0xB8	; 184
+ 5e2:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5e2:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5e6:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB82D);
- 5e6:	8d e2       	ldi	r24, 0x2D	; 45
- 5e8:	98 eb       	ldi	r25, 0xB8	; 184
- 5ea:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5ea:	8d e2       	ldi	r24, 0x2D	; 45
+ 5ec:	98 eb       	ldi	r25, 0xB8	; 184
+ 5ee:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5ee:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5f2:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB8D4);
- 5f2:	84 ed       	ldi	r24, 0xD4	; 212
- 5f4:	98 eb       	ldi	r25, 0xB8	; 184
- 5f6:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 5f6:	84 ed       	ldi	r24, 0xD4	; 212
+ 5f8:	98 eb       	ldi	r25, 0xB8	; 184
+ 5fa:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 5fa:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 5fe:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB800|addr);
- 5fe:	81 2f       	mov	r24, r17
- 600:	90 e0       	ldi	r25, 0x00	; 0
- 602:	98 6b       	ori	r25, 0xB8	; 184
- 604:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 602:	81 2f       	mov	r24, r17
+ 604:	90 e0       	ldi	r25, 0x00	; 0
+ 606:	98 6b       	ori	r25, 0xB8	; 184
+ 608:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 608:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 60c:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB800|from);
- 60c:	8d 2f       	mov	r24, r29
- 60e:	90 e0       	ldi	r25, 0x00	; 0
- 610:	98 6b       	ori	r25, 0xB8	; 184
- 612:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 610:	8d 2f       	mov	r24, r29
+ 612:	90 e0       	ldi	r25, 0x00	; 0
+ 614:	98 6b       	ori	r25, 0xB8	; 184
+ 616:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 616:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 61a:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB800|data);
- 61a:	8c 2f       	mov	r24, r28
- 61c:	90 e0       	ldi	r25, 0x00	; 0
- 61e:	98 6b       	ori	r25, 0xB8	; 184
- 620:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 61e:	8c 2f       	mov	r24, r28
+ 620:	90 e0       	ldi	r25, 0x00	; 0
+ 622:	98 6b       	ori	r25, 0xB8	; 184
+ 624:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 624:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 628:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0xB800);
- 628:	80 e0       	ldi	r24, 0x00	; 0
- 62a:	98 eb       	ldi	r25, 0xB8	; 184
- 62c:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
+ 62c:	80 e0       	ldi	r24, 0x00	; 0
+ 62e:	98 eb       	ldi	r25, 0xB8	; 184
+ 630:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
 	rf12_ready();
- 630:	0e 94 3d 02 	call	0x47a	; 0x47a <rf12_ready>
+ 634:	0e 94 3f 02 	call	0x47e	; 0x47e <rf12_ready>
 	rf12_trans(0x8208); // TX off
- 634:	88 e0       	ldi	r24, 0x08	; 8
- 636:	92 e8       	ldi	r25, 0x82	; 130
- 638:	0e 94 94 01 	call	0x328	; 0x328 <rf12_trans>
- 63c:	8f ef       	ldi	r24, 0xFF	; 255
- 63e:	90 e7       	ldi	r25, 0x70	; 112
- 640:	a2 e0       	ldi	r26, 0x02	; 2
- 642:	81 50       	subi	r24, 0x01	; 1
- 644:	90 40       	sbci	r25, 0x00	; 0
- 646:	a0 40       	sbci	r26, 0x00	; 0
- 648:	e1 f7       	brne	.-8      	; 0x642 <rf12_txpacket+0x98>
- 64a:	00 c0       	rjmp	.+0      	; 0x64c <rf12_txpacket+0xa2>
- 64c:	00 00       	nop
+ 638:	88 e0       	ldi	r24, 0x08	; 8
+ 63a:	92 e8       	ldi	r25, 0x82	; 130
+ 63c:	0e 94 96 01 	call	0x32c	; 0x32c <rf12_trans>
+ 640:	8f ef       	ldi	r24, 0xFF	; 255
+ 642:	90 e7       	ldi	r25, 0x70	; 112
+ 644:	a2 e0       	ldi	r26, 0x02	; 2
+ 646:	81 50       	subi	r24, 0x01	; 1
+ 648:	90 40       	sbci	r25, 0x00	; 0
+ 64a:	a0 40       	sbci	r26, 0x00	; 0
+ 64c:	e1 f7       	brne	.-8      	; 0x646 <rf12_txpacket+0x98>
+ 64e:	00 c0       	rjmp	.+0      	; 0x650 <rf12_txpacket+0xa2>
+ 650:	00 00       	nop
 	_delay_ms(100);
- 64e:	df 91       	pop	r29
- 650:	cf 91       	pop	r28
- 652:	1f 91       	pop	r17
- 654:	08 95       	ret
+ 652:	df 91       	pop	r29
+ 654:	cf 91       	pop	r28
+ 656:	1f 91       	pop	r17
+ 658:	08 95       	ret
 
-00000656 <__udivmodsi4>:
- 656:	a1 e2       	ldi	r26, 0x21	; 33
- 658:	1a 2e       	mov	r1, r26
- 65a:	aa 1b       	sub	r26, r26
- 65c:	bb 1b       	sub	r27, r27
- 65e:	fd 01       	movw	r30, r26
- 660:	0d c0       	rjmp	.+26     	; 0x67c <__udivmodsi4_ep>
+0000065a <__udivmodsi4>:
+ 65a:	a1 e2       	ldi	r26, 0x21	; 33
+ 65c:	1a 2e       	mov	r1, r26
+ 65e:	aa 1b       	sub	r26, r26
+ 660:	bb 1b       	sub	r27, r27
+ 662:	fd 01       	movw	r30, r26
+ 664:	0d c0       	rjmp	.+26     	; 0x680 <__udivmodsi4_ep>
 
-00000662 <__udivmodsi4_loop>:
- 662:	aa 1f       	adc	r26, r26
- 664:	bb 1f       	adc	r27, r27
- 666:	ee 1f       	adc	r30, r30
- 668:	ff 1f       	adc	r31, r31
- 66a:	a2 17       	cp	r26, r18
- 66c:	b3 07       	cpc	r27, r19
- 66e:	e4 07       	cpc	r30, r20
- 670:	f5 07       	cpc	r31, r21
- 672:	20 f0       	brcs	.+8      	; 0x67c <__udivmodsi4_ep>
- 674:	a2 1b       	sub	r26, r18
- 676:	b3 0b       	sbc	r27, r19
- 678:	e4 0b       	sbc	r30, r20
- 67a:	f5 0b       	sbc	r31, r21
+00000666 <__udivmodsi4_loop>:
+ 666:	aa 1f       	adc	r26, r26
+ 668:	bb 1f       	adc	r27, r27
+ 66a:	ee 1f       	adc	r30, r30
+ 66c:	ff 1f       	adc	r31, r31
+ 66e:	a2 17       	cp	r26, r18
+ 670:	b3 07       	cpc	r27, r19
+ 672:	e4 07       	cpc	r30, r20
+ 674:	f5 07       	cpc	r31, r21
+ 676:	20 f0       	brcs	.+8      	; 0x680 <__udivmodsi4_ep>
+ 678:	a2 1b       	sub	r26, r18
+ 67a:	b3 0b       	sbc	r27, r19
+ 67c:	e4 0b       	sbc	r30, r20
+ 67e:	f5 0b       	sbc	r31, r21
 
-0000067c <__udivmodsi4_ep>:
- 67c:	66 1f       	adc	r22, r22
- 67e:	77 1f       	adc	r23, r23
- 680:	88 1f       	adc	r24, r24
- 682:	99 1f       	adc	r25, r25
- 684:	1a 94       	dec	r1
- 686:	69 f7       	brne	.-38     	; 0x662 <__udivmodsi4_loop>
- 688:	60 95       	com	r22
- 68a:	70 95       	com	r23
- 68c:	80 95       	com	r24
- 68e:	90 95       	com	r25
- 690:	9b 01       	movw	r18, r22
- 692:	ac 01       	movw	r20, r24
- 694:	bd 01       	movw	r22, r26
- 696:	cf 01       	movw	r24, r30
- 698:	08 95       	ret
+00000680 <__udivmodsi4_ep>:
+ 680:	66 1f       	adc	r22, r22
+ 682:	77 1f       	adc	r23, r23
+ 684:	88 1f       	adc	r24, r24
+ 686:	99 1f       	adc	r25, r25
+ 688:	1a 94       	dec	r1
+ 68a:	69 f7       	brne	.-38     	; 0x666 <__udivmodsi4_loop>
+ 68c:	60 95       	com	r22
+ 68e:	70 95       	com	r23
+ 690:	80 95       	com	r24
+ 692:	90 95       	com	r25
+ 694:	9b 01       	movw	r18, r22
+ 696:	ac 01       	movw	r20, r24
+ 698:	bd 01       	movw	r22, r26
+ 69a:	cf 01       	movw	r24, r30
+ 69c:	08 95       	ret
 
-0000069a <__divmodsi4>:
- 69a:	97 fb       	bst	r25, 7
- 69c:	09 2e       	mov	r0, r25
- 69e:	05 26       	eor	r0, r21
- 6a0:	0e d0       	rcall	.+28     	; 0x6be <__divmodsi4_neg1>
- 6a2:	57 fd       	sbrc	r21, 7
- 6a4:	04 d0       	rcall	.+8      	; 0x6ae <__divmodsi4_neg2>
- 6a6:	d7 df       	rcall	.-82     	; 0x656 <__udivmodsi4>
- 6a8:	0a d0       	rcall	.+20     	; 0x6be <__divmodsi4_neg1>
- 6aa:	00 1c       	adc	r0, r0
- 6ac:	38 f4       	brcc	.+14     	; 0x6bc <__divmodsi4_exit>
+0000069e <__divmodsi4>:
+ 69e:	97 fb       	bst	r25, 7
+ 6a0:	09 2e       	mov	r0, r25
+ 6a2:	05 26       	eor	r0, r21
+ 6a4:	0e d0       	rcall	.+28     	; 0x6c2 <__divmodsi4_neg1>
+ 6a6:	57 fd       	sbrc	r21, 7
+ 6a8:	04 d0       	rcall	.+8      	; 0x6b2 <__divmodsi4_neg2>
+ 6aa:	d7 df       	rcall	.-82     	; 0x65a <__udivmodsi4>
+ 6ac:	0a d0       	rcall	.+20     	; 0x6c2 <__divmodsi4_neg1>
+ 6ae:	00 1c       	adc	r0, r0
+ 6b0:	38 f4       	brcc	.+14     	; 0x6c0 <__divmodsi4_exit>
 
-000006ae <__divmodsi4_neg2>:
- 6ae:	50 95       	com	r21
- 6b0:	40 95       	com	r20
- 6b2:	30 95       	com	r19
- 6b4:	21 95       	neg	r18
- 6b6:	3f 4f       	sbci	r19, 0xFF	; 255
- 6b8:	4f 4f       	sbci	r20, 0xFF	; 255
- 6ba:	5f 4f       	sbci	r21, 0xFF	; 255
+000006b2 <__divmodsi4_neg2>:
+ 6b2:	50 95       	com	r21
+ 6b4:	40 95       	com	r20
+ 6b6:	30 95       	com	r19
+ 6b8:	21 95       	neg	r18
+ 6ba:	3f 4f       	sbci	r19, 0xFF	; 255
+ 6bc:	4f 4f       	sbci	r20, 0xFF	; 255
+ 6be:	5f 4f       	sbci	r21, 0xFF	; 255
 
-000006bc <__divmodsi4_exit>:
- 6bc:	08 95       	ret
+000006c0 <__divmodsi4_exit>:
+ 6c0:	08 95       	ret
 
-000006be <__divmodsi4_neg1>:
- 6be:	f6 f7       	brtc	.-4      	; 0x6bc <__divmodsi4_exit>
- 6c0:	90 95       	com	r25
- 6c2:	80 95       	com	r24
- 6c4:	70 95       	com	r23
- 6c6:	61 95       	neg	r22
- 6c8:	7f 4f       	sbci	r23, 0xFF	; 255
- 6ca:	8f 4f       	sbci	r24, 0xFF	; 255
- 6cc:	9f 4f       	sbci	r25, 0xFF	; 255
- 6ce:	08 95       	ret
+000006c2 <__divmodsi4_neg1>:
+ 6c2:	f6 f7       	brtc	.-4      	; 0x6c0 <__divmodsi4_exit>
+ 6c4:	90 95       	com	r25
+ 6c6:	80 95       	com	r24
+ 6c8:	70 95       	com	r23
+ 6ca:	61 95       	neg	r22
+ 6cc:	7f 4f       	sbci	r23, 0xFF	; 255
+ 6ce:	8f 4f       	sbci	r24, 0xFF	; 255
+ 6d0:	9f 4f       	sbci	r25, 0xFF	; 255
+ 6d2:	08 95       	ret
 
-000006d0 <_exit>:
- 6d0:	f8 94       	cli
+000006d4 <_exit>:
+ 6d4:	f8 94       	cli
 
-000006d2 <__stop_program>:
- 6d2:	ff cf       	rjmp	.-2      	; 0x6d2 <__stop_program>
+000006d6 <__stop_program>:
+ 6d6:	ff cf       	rjmp	.-2      	; 0x6d6 <__stop_program>
diff --git a/Reciver/Reciver/Debug/Reciver.map b/Reciver/Reciver/Debug/Reciver.map
index 443f74f..234bfb5 100644
--- a/Reciver/Reciver/Debug/Reciver.map
+++ b/Reciver/Reciver/Debug/Reciver.map
@@ -124,7 +124,7 @@ LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoo
 .rela.plt
  *(.rela.plt)
 
-.text           0x00000000      0x6d4
+.text           0x00000000      0x6d8
  *(.vectors)
  .vectors       0x00000000       0x54 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
                 0x00000000                __vector_default
@@ -200,47 +200,47 @@ LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoo
                 0x0000008e                __vector_16
                 0x0000008e                __vector_18
                 0x0000008e                __vector_20
- .text          0x00000092      0x296 Reciver.o
+ .text          0x00000092      0x29a Reciver.o
                 0x00000092                turn
-                0x000000e6                poll
-                0x00000108                recive
-                0x000001b6                init_timer
-                0x000001c6                __vector_9
-                0x000002f6                main
- .text          0x00000328      0x32e rf12.o
-                0x00000328                rf12_trans
-                0x0000035a                rf12_init
-                0x000003ae                rf12_setbandwidth
-                0x000003ea                rf12_setfreq
-                0x0000040a                rf12_setbaud
-                0x00000458                rf12_setpower
-                0x0000047a                rf12_ready
-                0x00000482                rf12_beginasyncrx
-                0x0000049c                rf12_hasdata
-                0x000004a6                rf12_rxbyte
-                0x000004b0                rf12_endasyncrx
-                0x000004ba                rf12_txdata
-                0x0000054a                rf12_rxdata
-                0x000005aa                rf12_txpacket
- .text          0x00000656        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
- .text          0x00000656        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
- .text          0x00000656        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
- .text          0x00000656        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
- .text          0x00000656        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
-                0x00000656                . = ALIGN (0x2)
+                0x000000ea                poll
+                0x0000010c                recive
+                0x000001ba                init_timer
+                0x000001ca                __vector_9
+                0x000002fa                main
+ .text          0x0000032c      0x32e rf12.o
+                0x0000032c                rf12_trans
+                0x0000035e                rf12_init
+                0x000003b2                rf12_setbandwidth
+                0x000003ee                rf12_setfreq
+                0x0000040e                rf12_setbaud
+                0x0000045c                rf12_setpower
+                0x0000047e                rf12_ready
+                0x00000486                rf12_beginasyncrx
+                0x000004a0                rf12_hasdata
+                0x000004aa                rf12_rxbyte
+                0x000004b4                rf12_endasyncrx
+                0x000004be                rf12_txdata
+                0x0000054e                rf12_rxdata
+                0x000005ae                rf12_txpacket
+ .text          0x0000065a        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+ .text          0x0000065a        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+ .text          0x0000065a        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .text          0x0000065a        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+ .text          0x0000065a        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                0x0000065a                . = ALIGN (0x2)
  *(.text.*)
- .text.libgcc   0x00000656       0x44 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
-                0x00000656                __udivmodsi4
- .text.libgcc   0x0000069a       0x36 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
-                0x0000069a                __divmodsi4
- .text.libgcc   0x000006d0        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
- .text.libgcc   0x000006d0        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
- .text.libgcc   0x000006d0        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
-                0x000006d0                . = ALIGN (0x2)
+ .text.libgcc   0x0000065a       0x44 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+                0x0000065a                __udivmodsi4
+ .text.libgcc   0x0000069e       0x36 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+                0x0000069e                __divmodsi4
+ .text.libgcc   0x000006d4        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .text.libgcc   0x000006d4        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+ .text.libgcc   0x000006d4        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                0x000006d4                . = ALIGN (0x2)
  *(.fini9)
- .fini9         0x000006d0        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
-                0x000006d0                _exit
-                0x000006d0                exit
+ .fini9         0x000006d4        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+                0x000006d4                _exit
+                0x000006d4                exit
  *(.fini9)
  *(.fini8)
  *(.fini8)
@@ -259,36 +259,36 @@ LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoo
  *(.fini1)
  *(.fini1)
  *(.fini0)
- .fini0         0x000006d0        0x4 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .fini0         0x000006d4        0x4 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
  *(.fini0)
-                0x000006d4                _etext = .
+                0x000006d8                _etext = .
 
-.data           0x00800060        0x2 load address 0x000006d4
+.data           0x00800060        0x4 load address 0x000006d8
                 0x00800060                PROVIDE (__data_start, .)
  *(.data)
  .data          0x00800060        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
- .data          0x00800060        0x2 Reciver.o
-                0x00800060                status
- .data          0x00800062        0x0 rf12.o
- .data          0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
- .data          0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
- .data          0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
- .data          0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
- .data          0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+ .data          0x00800060        0x4 Reciver.o
+                0x00800060                servopos
+                0x00800062                status
+ .data          0x00800064        0x0 rf12.o
+ .data          0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+ .data          0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+ .data          0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .data          0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+ .data          0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
  *(.data*)
  *(.rodata)
  *(.rodata*)
  *(.gnu.linkonce.d*)
-                0x00800062                . = ALIGN (0x2)
-                0x00800062                _edata = .
-                0x00800062                PROVIDE (__data_end, .)
+                0x00800064                . = ALIGN (0x2)
+                0x00800064                _edata = .
+                0x00800064                PROVIDE (__data_end, .)
 
-.bss            0x00800062        0x4
-                0x00800062                PROVIDE (__bss_start, .)
+.bss            0x00800064        0x2
+                0x00800064                PROVIDE (__bss_start, .)
  *(.bss)
- .bss           0x00800062        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
- .bss           0x00800062        0x4 Reciver.o
-                0x00800062                servopos
+ .bss           0x00800064        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+ .bss           0x00800064        0x2 Reciver.o
                 0x00800064                pwm_led
  .bss           0x00800066        0x0 rf12.o
  .bss           0x00800066        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
@@ -299,8 +299,8 @@ LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoo
  *(.bss*)
  *(COMMON)
                 0x00800066                PROVIDE (__bss_end, .)
-                0x000006d4                __data_load_start = LOADADDR (.data)
-                0x000006d6                __data_load_end = (__data_load_start + SIZEOF (.data))
+                0x000006d8                __data_load_start = LOADADDR (.data)
+                0x000006dc                __data_load_end = (__data_load_start + SIZEOF (.data))
 
 .noinit         0x00800066        0x0
                 0x00800066                PROVIDE (__noinit_start, .)
diff --git a/Reciver/Reciver/Debug/Reciver.srec b/Reciver/Reciver/Debug/Reciver.srec
index 39876e4..d40575a 100644
--- a/Reciver/Reciver/Debug/Reciver.srec
+++ b/Reciver/Reciver/Debug/Reciver.srec
@@ -1,113 +1,113 @@
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 S11300300C9447000C9447000C9447000C94470020
 S11300400C9447000C9447000C9447000C94470010
 S11300500C94470011241FBECFE5D4E0DEBFCDBF12
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 S9030000FC
diff --git a/Reciver/Reciver/Reciver.c b/Reciver/Reciver/Reciver.c
index 76d2a09..594a8f8 100644
--- a/Reciver/Reciver/Reciver.c
+++ b/Reciver/Reciver/Reciver.c
@@ -17,15 +17,15 @@
 volatile int status = SLEEP;
 volatile int pwm_led = 0;
 
-volatile int servopos = 0;
+volatile int servopos = RIGHT;
 
 void turn() {
 	if(status == RUN)
 		return;
 	status = RUN;
-	servopos = RIGHT;
+	servopos = RIGHT-60;
 	_delay_ms(700);
-	servopos = 0;
+	servopos = RIGHT;
 	_delay_ms(700);
 }