diff --git a/V5B/BackupFiles/Zeitschaltung.T3000A b/V5B/BackupFiles/Zeitschaltung.T3000A
index 3a87629..264efb4 100644
Binary files a/V5B/BackupFiles/Zeitschaltung.T3000A and b/V5B/BackupFiles/Zeitschaltung.T3000A differ
diff --git a/V5B/BackupFiles/Zeitschaltung.T3000B b/V5B/BackupFiles/Zeitschaltung.T3000B
index c1092b3..3a87629 100644
Binary files a/V5B/BackupFiles/Zeitschaltung.T3000B and b/V5B/BackupFiles/Zeitschaltung.T3000B differ
diff --git a/V5B/BackupFiles/Zeitschaltung.T3000C b/V5B/BackupFiles/Zeitschaltung.T3000C
index 1d30452..c1092b3 100644
Binary files a/V5B/BackupFiles/Zeitschaltung.T3000C and b/V5B/BackupFiles/Zeitschaltung.T3000C differ
diff --git a/V5B/Reciver/Reciver.atsln b/V5B/Reciver/Reciver.atsln
new file mode 100644
index 0000000..93137b2
--- /dev/null
+++ b/V5B/Reciver/Reciver.atsln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Atmel Studio Solution File, Format Version 11.00
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Reciver", "Reciver\Reciver.cproj", "{762E00F9-912F-4C48-851F-1F51C060E5AE}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|AVR = Debug|AVR
+		Release|AVR = Release|AVR
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{762E00F9-912F-4C48-851F-1F51C060E5AE}.Debug|AVR.ActiveCfg = Debug|AVR
+		{762E00F9-912F-4C48-851F-1F51C060E5AE}.Debug|AVR.Build.0 = Debug|AVR
+		{762E00F9-912F-4C48-851F-1F51C060E5AE}.Release|AVR.ActiveCfg = Release|AVR
+		{762E00F9-912F-4C48-851F-1F51C060E5AE}.Release|AVR.Build.0 = Release|AVR
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/V5B/Reciver/Reciver.atsuo b/V5B/Reciver/Reciver.atsuo
new file mode 100644
index 0000000..4a150c6
Binary files /dev/null and b/V5B/Reciver/Reciver.atsuo differ
diff --git a/V5B/Reciver/Reciver/Debug/Makefile b/V5B/Reciver/Reciver/Debug/Makefile
new file mode 100644
index 0000000..db73fda
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Makefile
@@ -0,0 +1,130 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS := 
+PROJ := 
+
+O_SRCS := 
+C_SRCS := 
+S_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+PREPROCESSING_SRCS := 
+OBJS := 
+OBJS_AS_ARGS := 
+C_DEPS := 
+C_DEPS_AS_ARGS := 
+EXECUTABLES := 
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := 
+
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS +=  \
+../Reciver.c \
+../rf12.c
+
+
+PREPROCESSING_SRCS += 
+
+
+ASM_SRCS += 
+
+
+OBJS +=  \
+Reciver.o \
+rf12.o
+
+
+OBJS_AS_ARGS +=  \
+Reciver.o \
+rf12.o
+
+
+C_DEPS +=  \
+Reciver.d \
+rf12.d
+
+
+C_DEPS_AS_ARGS +=  \
+Reciver.d \
+rf12.d
+
+
+OUTPUT_FILE_PATH +=Reciver.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +=Reciver.elf
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+# AVR32/GNU C Compiler
+
+
+
+
+
+./%.o: .././%.c
+	@echo Building file: $<
+	@echo Invoking: AVR/GNU C Compiler : (AVR_8_bit_GNU_Toolchain_3.4.1_830) 4.6.2
+	$(QUOTE)C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-gcc.exe$(QUOTE) -funsigned-char -funsigned-bitfields -O1 -fpack-struct -fshort-enums -g2 -Wall -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"  -mmcu=attiny24a   -o"$@" "$<" 
+	@echo Finished building: $<
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables 
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP)
+	@echo Building target: $@
+	@echo Invoking: AVR/GNU Linker : (AVR_8_bit_GNU_Toolchain_3.4.1_830) 4.6.2
+	$(QUOTE)C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="Reciver.map" -Wl,--start-group -Wl,-lm  -Wl,--end-group  -mmcu=attiny24a  
+	@echo Finished building target: $@
+	"C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature  "Reciver.elf" "Reciver.hex"
+	"C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -j .eeprom  --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0  --no-change-warnings -O ihex "Reciver.elf" "Reciver.eep" || exit 0
+	"C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objdump.exe" -h -S "Reciver.elf" > "Reciver.lss"
+	"C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature  "Reciver.elf" "Reciver.srec"
+	"C:\Program Files (x86)\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-size.exe" "Reciver.elf"
+	
+
+
+
+
+
+# Other Targets
+clean:
+	-$(RM) $(OBJS_AS_ARGS)$(C_DEPS_AS_ARGS) $(EXECUTABLES) 
+	rm -rf "Reciver.elf" "Reciver.a" "Reciver.hex" "Reciver.lss" "Reciver.eep" "Reciver.map" "Reciver.srec"
+	
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.d b/V5B/Reciver/Reciver/Debug/Reciver.d
new file mode 100644
index 0000000..e0dc0bc
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.d
@@ -0,0 +1,53 @@
+Reciver.d Reciver.o: .././Reciver.c .././global.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/io.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/sfr_defs.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/inttypes.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/include/stdint.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/stdint.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/iotn24a.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/portpins.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/common.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/version.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/fuse.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/lock.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/interrupt.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay_basic.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/math.h \
+ .././rf12.h .././codes.h
+
+.././global.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/io.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/sfr_defs.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/inttypes.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/include/stdint.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/stdint.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/iotn24a.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/portpins.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/common.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/version.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/fuse.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/lock.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/interrupt.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay_basic.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/math.h:
+
+.././rf12.h:
+
+.././codes.h:
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.eep b/V5B/Reciver/Reciver/Debug/Reciver.eep
new file mode 100644
index 0000000..1996e8f
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.eep
@@ -0,0 +1 @@
+:00000001FF
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.elf b/V5B/Reciver/Reciver/Debug/Reciver.elf
new file mode 100644
index 0000000..311856b
Binary files /dev/null and b/V5B/Reciver/Reciver/Debug/Reciver.elf differ
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.hex b/V5B/Reciver/Reciver/Debug/Reciver.hex
new file mode 100644
index 0000000..748f809
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.hex
@@ -0,0 +1,107 @@
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+:10066000001C38F450954095309521953F4F4F4FE1
+:100670005F4F0895F6F790958095709561957F4F3F
+:0A0680008F4F9F4F0895F894FFCFAD
+:04068A00B4000200B6
+:00000001FF
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.lss b/V5B/Reciver/Reciver/Debug/Reciver.lss
new file mode 100644
index 0000000..3f58b71
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.lss
@@ -0,0 +1,1296 @@
+
+Reciver.elf:     file format elf32-avr
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         0000068a  00000000  00000000  00000094  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000004  00800060  0000068a  0000071e  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000002  00800064  00800064  00000722  2**0
+                  ALLOC
+  3 .stab         000006b4  00000000  00000000  00000724  2**2
+                  CONTENTS, READONLY, DEBUGGING
+  4 .stabstr      00000085  00000000  00000000  00000dd8  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  5 .debug_aranges 000000e0  00000000  00000000  00000e60  2**3
+                  CONTENTS, READONLY, DEBUGGING
+  6 .debug_info   00000d5e  00000000  00000000  00000f40  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  7 .debug_abbrev 00000388  00000000  00000000  00001c9e  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  8 .debug_line   0000074d  00000000  00000000  00002026  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  9 .debug_frame  000001c8  00000000  00000000  00002774  2**2
+                  CONTENTS, READONLY, DEBUGGING
+ 10 .debug_str    0000025c  00000000  00000000  0000293c  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_loc    000006d5  00000000  00000000  00002b98  2**0
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <__vectors>:
+   0:	10 c0       	rjmp	.+32     	; 0x22 <__ctors_end>
+   2:	28 c0       	rjmp	.+80     	; 0x54 <__bad_interrupt>
+   4:	27 c0       	rjmp	.+78     	; 0x54 <__bad_interrupt>
+   6:	26 c0       	rjmp	.+76     	; 0x54 <__bad_interrupt>
+   8:	25 c0       	rjmp	.+74     	; 0x54 <__bad_interrupt>
+   a:	24 c0       	rjmp	.+72     	; 0x54 <__bad_interrupt>
+   c:	23 c0       	rjmp	.+70     	; 0x54 <__bad_interrupt>
+   e:	22 c0       	rjmp	.+68     	; 0x54 <__bad_interrupt>
+  10:	21 c0       	rjmp	.+66     	; 0x54 <__bad_interrupt>
+  12:	20 c0       	rjmp	.+64     	; 0x54 <__bad_interrupt>
+  14:	1f c0       	rjmp	.+62     	; 0x54 <__bad_interrupt>
+  16:	0a c1       	rjmp	.+532    	; 0x22c <__vector_11>
+  18:	1d c0       	rjmp	.+58     	; 0x54 <__bad_interrupt>
+  1a:	1c c0       	rjmp	.+56     	; 0x54 <__bad_interrupt>
+  1c:	1b c0       	rjmp	.+54     	; 0x54 <__bad_interrupt>
+  1e:	1a c0       	rjmp	.+52     	; 0x54 <__bad_interrupt>
+  20:	19 c0       	rjmp	.+50     	; 0x54 <__bad_interrupt>
+
+00000022 <__ctors_end>:
+  22:	11 24       	eor	r1, r1
+  24:	1f be       	out	0x3f, r1	; 63
+  26:	cf ed       	ldi	r28, 0xDF	; 223
+  28:	cd bf       	out	0x3d, r28	; 61
+
+0000002a <__do_copy_data>:
+  2a:	10 e0       	ldi	r17, 0x00	; 0
+  2c:	a0 e6       	ldi	r26, 0x60	; 96
+  2e:	b0 e0       	ldi	r27, 0x00	; 0
+  30:	ea e8       	ldi	r30, 0x8A	; 138
+  32:	f6 e0       	ldi	r31, 0x06	; 6
+  34:	02 c0       	rjmp	.+4      	; 0x3a <__CCP__+0x6>
+  36:	05 90       	lpm	r0, Z+
+  38:	0d 92       	st	X+, r0
+  3a:	a4 36       	cpi	r26, 0x64	; 100
+  3c:	b1 07       	cpc	r27, r17
+  3e:	d9 f7       	brne	.-10     	; 0x36 <__CCP__+0x2>
+
+00000040 <__do_clear_bss>:
+  40:	10 e0       	ldi	r17, 0x00	; 0
+  42:	a4 e6       	ldi	r26, 0x64	; 100
+  44:	b0 e0       	ldi	r27, 0x00	; 0
+  46:	01 c0       	rjmp	.+2      	; 0x4a <.do_clear_bss_start>
+
+00000048 <.do_clear_bss_loop>:
+  48:	1d 92       	st	X+, r1
+
+0000004a <.do_clear_bss_start>:
+  4a:	a6 36       	cpi	r26, 0x66	; 102
+  4c:	b1 07       	cpc	r27, r17
+  4e:	e1 f7       	brne	.-8      	; 0x48 <.do_clear_bss_loop>
+  50:	6c d1       	rcall	.+728    	; 0x32a <main>
+  52:	19 c3       	rjmp	.+1586   	; 0x686 <_exit>
+
+00000054 <__bad_interrupt>:
+  54:	d5 cf       	rjmp	.-86     	; 0x0 <__vectors>
+
+00000056 <turn>:
+volatile int pwm_led = 0;
+
+volatile int servopos = RIGHT;
+
+void turn() {
+	if(status == RUN)
+  56:	80 91 62 00 	lds	r24, 0x0062
+  5a:	90 91 63 00 	lds	r25, 0x0063
+  5e:	86 30       	cpi	r24, 0x06	; 6
+  60:	91 05       	cpc	r25, r1
+  62:	09 f4       	brne	.+2      	; 0x66 <turn+0x10>
+  64:	40 c0       	rjmp	.+128    	; 0xe6 <__stack+0x7>
+		return;
+	status = RUN;
+  66:	86 e0       	ldi	r24, 0x06	; 6
+  68:	90 e0       	ldi	r25, 0x00	; 0
+  6a:	90 93 63 00 	sts	0x0063, r25
+  6e:	80 93 62 00 	sts	0x0062, r24
+	servopos = RIGHT-60;
+  72:	88 e7       	ldi	r24, 0x78	; 120
+  74:	90 e0       	ldi	r25, 0x00	; 0
+  76:	90 93 61 00 	sts	0x0061, r25
+  7a:	80 93 60 00 	sts	0x0060, r24
+	#else
+		//round up by default
+		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
+	#endif
+
+	__builtin_avr_delay_cycles(__ticks_dc);
+  7e:	8f e3       	ldi	r24, 0x3F	; 63
+  80:	9c e9       	ldi	r25, 0x9C	; 156
+  82:	01 97       	sbiw	r24, 0x01	; 1
+  84:	f1 f7       	brne	.-4      	; 0x82 <turn+0x2c>
+  86:	00 c0       	rjmp	.+0      	; 0x88 <turn+0x32>
+  88:	00 00       	nop
+	_delay_ms(10+DEVICE);
+	rf12_txpacket(MASTER, DEVICE, status);
+  8a:	40 91 62 00 	lds	r20, 0x0062
+  8e:	50 91 63 00 	lds	r21, 0x0063
+  92:	81 e0       	ldi	r24, 0x01	; 1
+  94:	6a e0       	ldi	r22, 0x0A	; 10
+  96:	79 d2       	rcall	.+1266   	; 0x58a <rf12_txpacket>
+  98:	8f ef       	ldi	r24, 0xFF	; 255
+  9a:	96 e1       	ldi	r25, 0x16	; 22
+  9c:	a1 e1       	ldi	r26, 0x11	; 17
+  9e:	81 50       	subi	r24, 0x01	; 1
+  a0:	90 40       	sbci	r25, 0x00	; 0
+  a2:	a0 40       	sbci	r26, 0x00	; 0
+  a4:	e1 f7       	brne	.-8      	; 0x9e <turn+0x48>
+  a6:	00 c0       	rjmp	.+0      	; 0xa8 <turn+0x52>
+  a8:	00 00       	nop
+	_delay_ms(700);
+	servopos = RIGHT-120;
+  aa:	8c e3       	ldi	r24, 0x3C	; 60
+  ac:	90 e0       	ldi	r25, 0x00	; 0
+  ae:	90 93 61 00 	sts	0x0061, r25
+  b2:	80 93 60 00 	sts	0x0060, r24
+  b6:	8f ef       	ldi	r24, 0xFF	; 255
+  b8:	96 e1       	ldi	r25, 0x16	; 22
+  ba:	a1 e1       	ldi	r26, 0x11	; 17
+  bc:	81 50       	subi	r24, 0x01	; 1
+  be:	90 40       	sbci	r25, 0x00	; 0
+  c0:	a0 40       	sbci	r26, 0x00	; 0
+  c2:	e1 f7       	brne	.-8      	; 0xbc <turn+0x66>
+  c4:	00 c0       	rjmp	.+0      	; 0xc6 <turn+0x70>
+  c6:	00 00       	nop
+	_delay_ms(700);
+	servopos = RIGHT;
+  c8:	84 eb       	ldi	r24, 0xB4	; 180
+  ca:	90 e0       	ldi	r25, 0x00	; 0
+  cc:	90 93 61 00 	sts	0x0061, r25
+  d0:	80 93 60 00 	sts	0x0060, r24
+  d4:	8f ef       	ldi	r24, 0xFF	; 255
+  d6:	96 e1       	ldi	r25, 0x16	; 22
+  d8:	a1 e1       	ldi	r26, 0x11	; 17
+  da:	81 50       	subi	r24, 0x01	; 1
+  dc:	90 40       	sbci	r25, 0x00	; 0
+  de:	a0 40       	sbci	r26, 0x00	; 0
+  e0:	e1 f7       	brne	.-8      	; 0xda <turn+0x84>
+  e2:	00 c0       	rjmp	.+0      	; 0xe4 <__stack+0x5>
+  e4:	00 00       	nop
+  e6:	08 95       	ret
+
+000000e8 <poll>:
+	_delay_ms(700);
+}
+
+void poll() {
+	DDRB &= ~(1<<PINB2);
+  e8:	ba 98       	cbi	0x17, 2	; 23
+	if(status == ACTIVE) {
+  ea:	80 91 62 00 	lds	r24, 0x0062
+  ee:	90 91 63 00 	lds	r25, 0x0063
+  f2:	83 30       	cpi	r24, 0x03	; 3
+  f4:	91 05       	cpc	r25, r1
+  f6:	29 f4       	brne	.+10     	; 0x102 <poll+0x1a>
+		if(PINB & (1<<PINB2)) {
+  f8:	b2 9b       	sbis	0x16, 2	; 22
+  fa:	03 c0       	rjmp	.+6      	; 0x102 <poll+0x1a>
+			rf12_endasyncrx();
+  fc:	df d1       	rcall	.+958    	; 0x4bc <rf12_endasyncrx>
+			turn();
+  fe:	ab df       	rcall	.-170    	; 0x56 <turn>
+			rf12_beginasyncrx();
+ 100:	ca d1       	rcall	.+916    	; 0x496 <rf12_beginasyncrx>
+		}
+	}
+	if(status == SLEEP) {
+ 102:	80 91 62 00 	lds	r24, 0x0062
+ 106:	90 91 63 00 	lds	r25, 0x0063
+ 10a:	82 30       	cpi	r24, 0x02	; 2
+ 10c:	91 05       	cpc	r25, r1
+ 10e:	41 f4       	brne	.+16     	; 0x120 <poll+0x38>
+		if(PINB & (1<<PINB2)) {
+ 110:	b2 9b       	sbis	0x16, 2	; 22
+ 112:	06 c0       	rjmp	.+12     	; 0x120 <poll+0x38>
+			rf12_endasyncrx();
+ 114:	d3 d1       	rcall	.+934    	; 0x4bc <rf12_endasyncrx>
+			rf12_txpacket(MASTER, DEVICE, DEDECT);
+ 116:	81 e0       	ldi	r24, 0x01	; 1
+ 118:	6a e0       	ldi	r22, 0x0A	; 10
+ 11a:	48 e0       	ldi	r20, 0x08	; 8
+ 11c:	36 d2       	rcall	.+1132   	; 0x58a <rf12_txpacket>
+			rf12_beginasyncrx();
+ 11e:	bb d1       	rcall	.+886    	; 0x496 <rf12_beginasyncrx>
+		}			
+	}
+	if(!(PINA & (1<<PINA4))) { //SCK auf 0
+ 120:	cc 99       	sbic	0x19, 4	; 25
+ 122:	2e c0       	rjmp	.+92     	; 0x180 <poll+0x98>
+		if(status == SLEEP) {
+ 124:	80 91 62 00 	lds	r24, 0x0062
+ 128:	90 91 63 00 	lds	r25, 0x0063
+ 12c:	82 30       	cpi	r24, 0x02	; 2
+ 12e:	91 05       	cpc	r25, r1
+ 130:	39 f5       	brne	.+78     	; 0x180 <poll+0x98>
+			status = RUN;
+ 132:	86 e0       	ldi	r24, 0x06	; 6
+ 134:	90 e0       	ldi	r25, 0x00	; 0
+ 136:	90 93 63 00 	sts	0x0063, r25
+ 13a:	80 93 62 00 	sts	0x0062, r24
+ 13e:	8f ef       	ldi	r24, 0xFF	; 255
+ 140:	91 e1       	ldi	r25, 0x11	; 17
+ 142:	aa e7       	ldi	r26, 0x7A	; 122
+ 144:	81 50       	subi	r24, 0x01	; 1
+ 146:	90 40       	sbci	r25, 0x00	; 0
+ 148:	a0 40       	sbci	r26, 0x00	; 0
+ 14a:	e1 f7       	brne	.-8      	; 0x144 <poll+0x5c>
+ 14c:	00 c0       	rjmp	.+0      	; 0x14e <poll+0x66>
+ 14e:	00 00       	nop
+ 150:	8f ef       	ldi	r24, 0xFF	; 255
+ 152:	91 e1       	ldi	r25, 0x11	; 17
+ 154:	aa e7       	ldi	r26, 0x7A	; 122
+ 156:	81 50       	subi	r24, 0x01	; 1
+ 158:	90 40       	sbci	r25, 0x00	; 0
+ 15a:	a0 40       	sbci	r26, 0x00	; 0
+ 15c:	e1 f7       	brne	.-8      	; 0x156 <poll+0x6e>
+ 15e:	00 c0       	rjmp	.+0      	; 0x160 <poll+0x78>
+ 160:	00 00       	nop
+ 162:	8f ef       	ldi	r24, 0xFF	; 255
+ 164:	91 e1       	ldi	r25, 0x11	; 17
+ 166:	aa e7       	ldi	r26, 0x7A	; 122
+ 168:	81 50       	subi	r24, 0x01	; 1
+ 16a:	90 40       	sbci	r25, 0x00	; 0
+ 16c:	a0 40       	sbci	r26, 0x00	; 0
+ 16e:	e1 f7       	brne	.-8      	; 0x168 <poll+0x80>
+ 170:	00 c0       	rjmp	.+0      	; 0x172 <poll+0x8a>
+ 172:	00 00       	nop
+			_delay_ms(5000);
+			_delay_ms(5000);
+			_delay_ms(5000);
+			status = ACTIVE;
+ 174:	83 e0       	ldi	r24, 0x03	; 3
+ 176:	90 e0       	ldi	r25, 0x00	; 0
+ 178:	90 93 63 00 	sts	0x0063, r25
+ 17c:	80 93 62 00 	sts	0x0062, r24
+ 180:	08 95       	ret
+
+00000182 <recive>:
+		}
+	}
+}
+
+void recive() {
+ 182:	cf 93       	push	r28
+	rf12_beginasyncrx();
+ 184:	88 d1       	rcall	.+784    	; 0x496 <rf12_beginasyncrx>
+	while(rf12_hasdata()) {
+ 186:	01 c0       	rjmp	.+2      	; 0x18a <recive+0x8>
+		poll();
+ 188:	af df       	rcall	.-162    	; 0xe8 <poll>
+	}
+}
+
+void recive() {
+	rf12_beginasyncrx();
+	while(rf12_hasdata()) {
+ 18a:	8f d1       	rcall	.+798    	; 0x4aa <rf12_hasdata>
+ 18c:	88 23       	and	r24, r24
+ 18e:	e1 f7       	brne	.-8      	; 0x188 <recive+0x6>
+		poll();
+	}
+	uint8_t addr = rf12_rxbyte();
+ 190:	91 d1       	rcall	.+802    	; 0x4b4 <rf12_rxbyte>
+	if(addr == ALL || addr == DEVICE || addr == GROUP) {
+ 192:	88 23       	and	r24, r24
+ 194:	31 f0       	breq	.+12     	; 0x1a2 <recive+0x20>
+ 196:	8a 30       	cpi	r24, 0x0A	; 10
+ 198:	21 f0       	breq	.+8      	; 0x1a2 <recive+0x20>
+ 19a:	80 3f       	cpi	r24, 0xF0	; 240
+ 19c:	e9 f5       	brne	.+122    	; 0x218 <recive+0x96>
+ 19e:	01 c0       	rjmp	.+2      	; 0x1a2 <recive+0x20>
+		while(rf12_hasdata()) {
+			poll();
+ 1a0:	a3 df       	rcall	.-186    	; 0xe8 <poll>
+	while(rf12_hasdata()) {
+		poll();
+	}
+	uint8_t addr = rf12_rxbyte();
+	if(addr == ALL || addr == DEVICE || addr == GROUP) {
+		while(rf12_hasdata()) {
+ 1a2:	83 d1       	rcall	.+774    	; 0x4aa <rf12_hasdata>
+ 1a4:	88 23       	and	r24, r24
+ 1a6:	e1 f7       	brne	.-8      	; 0x1a0 <recive+0x1e>
+			poll();
+		}
+		uint8_t from = rf12_rxbyte();
+ 1a8:	85 d1       	rcall	.+778    	; 0x4b4 <rf12_rxbyte>
+ 1aa:	c8 2f       	mov	r28, r24
+		while(rf12_hasdata()) {
+ 1ac:	01 c0       	rjmp	.+2      	; 0x1b0 <recive+0x2e>
+			poll();
+ 1ae:	9c df       	rcall	.-200    	; 0xe8 <poll>
+	if(addr == ALL || addr == DEVICE || addr == GROUP) {
+		while(rf12_hasdata()) {
+			poll();
+		}
+		uint8_t from = rf12_rxbyte();
+		while(rf12_hasdata()) {
+ 1b0:	7c d1       	rcall	.+760    	; 0x4aa <rf12_hasdata>
+ 1b2:	88 23       	and	r24, r24
+ 1b4:	e1 f7       	brne	.-8      	; 0x1ae <recive+0x2c>
+			poll();
+		}
+		if(from == MASTER) {
+ 1b6:	c1 30       	cpi	r28, 0x01	; 1
+ 1b8:	79 f5       	brne	.+94     	; 0x218 <recive+0x96>
+			uint8_t data = rf12_rxbyte();
+ 1ba:	7c d1       	rcall	.+760    	; 0x4b4 <rf12_rxbyte>
+			switch(data) {
+ 1bc:	84 30       	cpi	r24, 0x04	; 4
+ 1be:	51 f0       	breq	.+20     	; 0x1d4 <recive+0x52>
+ 1c0:	85 30       	cpi	r24, 0x05	; 5
+ 1c2:	18 f4       	brcc	.+6      	; 0x1ca <recive+0x48>
+ 1c4:	81 30       	cpi	r24, 0x01	; 1
+ 1c6:	c1 f4       	brne	.+48     	; 0x1f8 <recive+0x76>
+ 1c8:	19 c0       	rjmp	.+50     	; 0x1fc <recive+0x7a>
+ 1ca:	85 30       	cpi	r24, 0x05	; 5
+ 1cc:	51 f0       	breq	.+20     	; 0x1e2 <recive+0x60>
+ 1ce:	87 30       	cpi	r24, 0x07	; 7
+ 1d0:	99 f4       	brne	.+38     	; 0x1f8 <recive+0x76>
+ 1d2:	0e c0       	rjmp	.+28     	; 0x1f0 <recive+0x6e>
+				case PING: {
+					break;
+				}
+				case SETSLEEP: {
+					status = SLEEP;
+ 1d4:	82 e0       	ldi	r24, 0x02	; 2
+ 1d6:	90 e0       	ldi	r25, 0x00	; 0
+ 1d8:	90 93 63 00 	sts	0x0063, r25
+ 1dc:	80 93 62 00 	sts	0x0062, r24
+					break;
+ 1e0:	0d c0       	rjmp	.+26     	; 0x1fc <recive+0x7a>
+				}
+				case SETACTIVE: {
+					status = ACTIVE;
+ 1e2:	83 e0       	ldi	r24, 0x03	; 3
+ 1e4:	90 e0       	ldi	r25, 0x00	; 0
+ 1e6:	90 93 63 00 	sts	0x0063, r25
+ 1ea:	80 93 62 00 	sts	0x0062, r24
+					break;
+ 1ee:	06 c0       	rjmp	.+12     	; 0x1fc <recive+0x7a>
+				}
+				case SETRUN: {
+					rf12_endasyncrx();
+ 1f0:	65 d1       	rcall	.+714    	; 0x4bc <rf12_endasyncrx>
+					turn();
+ 1f2:	31 df       	rcall	.-414    	; 0x56 <turn>
+					rf12_beginasyncrx();
+ 1f4:	50 d1       	rcall	.+672    	; 0x496 <rf12_beginasyncrx>
+					return;
+ 1f6:	10 c0       	rjmp	.+32     	; 0x218 <recive+0x96>
+				}
+				default:
+				{
+					rf12_endasyncrx();
+ 1f8:	61 d1       	rcall	.+706    	; 0x4bc <rf12_endasyncrx>
+					return;
+ 1fa:	0e c0       	rjmp	.+28     	; 0x218 <recive+0x96>
+				}
+			}
+			rf12_endasyncrx();
+ 1fc:	5f d1       	rcall	.+702    	; 0x4bc <rf12_endasyncrx>
+ 1fe:	8f e3       	ldi	r24, 0x3F	; 63
+ 200:	9c e9       	ldi	r25, 0x9C	; 156
+ 202:	01 97       	sbiw	r24, 0x01	; 1
+ 204:	f1 f7       	brne	.-4      	; 0x202 <recive+0x80>
+ 206:	00 c0       	rjmp	.+0      	; 0x208 <recive+0x86>
+ 208:	00 00       	nop
+			_delay_ms(10+DEVICE);
+			rf12_txpacket(MASTER, DEVICE, status);
+ 20a:	40 91 62 00 	lds	r20, 0x0062
+ 20e:	50 91 63 00 	lds	r21, 0x0063
+ 212:	81 e0       	ldi	r24, 0x01	; 1
+ 214:	6a e0       	ldi	r22, 0x0A	; 10
+ 216:	b9 d1       	rcall	.+882    	; 0x58a <rf12_txpacket>
+			return;
+		}					
+	}
+}
+ 218:	cf 91       	pop	r28
+ 21a:	08 95       	ret
+
+0000021c <init_timer>:
+	// Clock value: 7,813 kHz
+	// Mode: Normal top=0xFF
+	// OC0A output: Disconnected
+	// OC0B output: Disconnected
+	// Timer Period: 21,504 ms
+	TCCR0A = (0<<COM0A1) | (0<<COM0A0) | (0<<COM0B1) | (0<<COM0B0) | (0<<WGM01) | (0<<WGM00);
+ 21c:	10 be       	out	0x30, r1	; 48
+	TCCR0B = (0<<WGM02) | (1<<CS02) | (0<<CS01) | (1<<CS00);
+ 21e:	85 e0       	ldi	r24, 0x05	; 5
+ 220:	83 bf       	out	0x33, r24	; 51
+	TCNT0 = 0x58;
+ 222:	88 e5       	ldi	r24, 0x58	; 88
+ 224:	82 bf       	out	0x32, r24	; 50
+	
+	// Timer/Counter 0 Interrupt(s) initialization
+	TIMSK0=(0<<OCIE0B) | (0<<OCIE0A) | (1<<TOIE0);
+ 226:	81 e0       	ldi	r24, 0x01	; 1
+ 228:	89 bf       	out	0x39, r24	; 57
+}
+ 22a:	08 95       	ret
+
+0000022c <__vector_11>:
+
+ISR(TIM0_OVF_vect) {
+ 22c:	1f 92       	push	r1
+ 22e:	0f 92       	push	r0
+ 230:	0f b6       	in	r0, 0x3f	; 63
+ 232:	0f 92       	push	r0
+ 234:	11 24       	eor	r1, r1
+ 236:	2f 93       	push	r18
+ 238:	3f 93       	push	r19
+ 23a:	8f 93       	push	r24
+ 23c:	9f 93       	push	r25
+	// Reinitialize Timer 0 value
+	TCNT0=0x58;
+ 23e:	88 e5       	ldi	r24, 0x58	; 88
+ 240:	82 bf       	out	0x32, r24	; 50
+	
+	if(status == SLEEP) {
+ 242:	80 91 62 00 	lds	r24, 0x0062
+ 246:	90 91 63 00 	lds	r25, 0x0063
+ 24a:	82 30       	cpi	r24, 0x02	; 2
+ 24c:	91 05       	cpc	r25, r1
+ 24e:	81 f4       	brne	.+32     	; 0x270 <__vector_11+0x44>
+		if(pwm_led > 50) {
+ 250:	80 91 64 00 	lds	r24, 0x0064
+ 254:	90 91 65 00 	lds	r25, 0x0065
+ 258:	83 33       	cpi	r24, 0x33	; 51
+ 25a:	91 05       	cpc	r25, r1
+ 25c:	b4 f1       	brlt	.+108    	; 0x2ca <__vector_11+0x9e>
+			PORTB ^= (1<<PINB1);
+ 25e:	98 b3       	in	r25, 0x18	; 24
+ 260:	82 e0       	ldi	r24, 0x02	; 2
+ 262:	89 27       	eor	r24, r25
+ 264:	88 bb       	out	0x18, r24	; 24
+			pwm_led = 0;
+ 266:	10 92 65 00 	sts	0x0065, r1
+ 26a:	10 92 64 00 	sts	0x0064, r1
+ 26e:	2d c0       	rjmp	.+90     	; 0x2ca <__vector_11+0x9e>
+		}					
+	} else if(status == ACTIVE) {
+ 270:	80 91 62 00 	lds	r24, 0x0062
+ 274:	90 91 63 00 	lds	r25, 0x0063
+ 278:	83 30       	cpi	r24, 0x03	; 3
+ 27a:	91 05       	cpc	r25, r1
+ 27c:	81 f4       	brne	.+32     	; 0x29e <__vector_11+0x72>
+		if(pwm_led > 5) {
+ 27e:	80 91 64 00 	lds	r24, 0x0064
+ 282:	90 91 65 00 	lds	r25, 0x0065
+ 286:	86 30       	cpi	r24, 0x06	; 6
+ 288:	91 05       	cpc	r25, r1
+ 28a:	fc f0       	brlt	.+62     	; 0x2ca <__vector_11+0x9e>
+			PORTB ^= (1<<PINB1);
+ 28c:	98 b3       	in	r25, 0x18	; 24
+ 28e:	82 e0       	ldi	r24, 0x02	; 2
+ 290:	89 27       	eor	r24, r25
+ 292:	88 bb       	out	0x18, r24	; 24
+			pwm_led = 0;
+ 294:	10 92 65 00 	sts	0x0065, r1
+ 298:	10 92 64 00 	sts	0x0064, r1
+ 29c:	16 c0       	rjmp	.+44     	; 0x2ca <__vector_11+0x9e>
+		}
+	} else if(status == RUN) {
+ 29e:	80 91 62 00 	lds	r24, 0x0062
+ 2a2:	90 91 63 00 	lds	r25, 0x0063
+ 2a6:	86 30       	cpi	r24, 0x06	; 6
+ 2a8:	91 05       	cpc	r25, r1
+ 2aa:	79 f4       	brne	.+30     	; 0x2ca <__vector_11+0x9e>
+		if(pwm_led > 1) {
+ 2ac:	80 91 64 00 	lds	r24, 0x0064
+ 2b0:	90 91 65 00 	lds	r25, 0x0065
+ 2b4:	82 30       	cpi	r24, 0x02	; 2
+ 2b6:	91 05       	cpc	r25, r1
+ 2b8:	44 f0       	brlt	.+16     	; 0x2ca <__vector_11+0x9e>
+			PORTB ^= (1<<PINB1);
+ 2ba:	98 b3       	in	r25, 0x18	; 24
+ 2bc:	82 e0       	ldi	r24, 0x02	; 2
+ 2be:	89 27       	eor	r24, r25
+ 2c0:	88 bb       	out	0x18, r24	; 24
+			pwm_led = 0;
+ 2c2:	10 92 65 00 	sts	0x0065, r1
+ 2c6:	10 92 64 00 	sts	0x0064, r1
+		}
+	}
+	pwm_led++;	
+ 2ca:	80 91 64 00 	lds	r24, 0x0064
+ 2ce:	90 91 65 00 	lds	r25, 0x0065
+ 2d2:	01 96       	adiw	r24, 0x01	; 1
+ 2d4:	90 93 65 00 	sts	0x0065, r25
+ 2d8:	80 93 64 00 	sts	0x0064, r24
+	
+	DDRB |= (1<<PINB0);
+ 2dc:	b8 9a       	sbi	0x17, 0	; 23
+	PORTB |= (1<<PINB0);
+ 2de:	c0 9a       	sbi	0x18, 0	; 24
+	#else
+		//round up by default
+		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
+	#endif
+
+	__builtin_avr_delay_cycles(__ticks_dc);
+ 2e0:	8f ea       	ldi	r24, 0xAF	; 175
+ 2e2:	94 e0       	ldi	r25, 0x04	; 4
+ 2e4:	01 97       	sbiw	r24, 0x01	; 1
+ 2e6:	f1 f7       	brne	.-4      	; 0x2e4 <__vector_11+0xb8>
+ 2e8:	00 c0       	rjmp	.+0      	; 0x2ea <__vector_11+0xbe>
+ 2ea:	00 00       	nop
+	_delay_us(LEFT);
+	for(int i=0;i<servopos;i++) {
+ 2ec:	80 91 60 00 	lds	r24, 0x0060
+ 2f0:	90 91 61 00 	lds	r25, 0x0061
+ 2f4:	18 16       	cp	r1, r24
+ 2f6:	19 06       	cpc	r1, r25
+ 2f8:	74 f4       	brge	.+28     	; 0x316 <__vector_11+0xea>
+ 2fa:	80 e0       	ldi	r24, 0x00	; 0
+ 2fc:	90 e0       	ldi	r25, 0x00	; 0
+ 2fe:	25 e1       	ldi	r18, 0x15	; 21
+ 300:	2a 95       	dec	r18
+ 302:	f1 f7       	brne	.-4      	; 0x300 <__vector_11+0xd4>
+ 304:	00 00       	nop
+ 306:	01 96       	adiw	r24, 0x01	; 1
+ 308:	20 91 60 00 	lds	r18, 0x0060
+ 30c:	30 91 61 00 	lds	r19, 0x0061
+ 310:	82 17       	cp	r24, r18
+ 312:	93 07       	cpc	r25, r19
+ 314:	a4 f3       	brlt	.-24     	; 0x2fe <__vector_11+0xd2>
+		_delay_us(STEP);
+	}
+	PORTB &= ~(1<<PINB0);
+ 316:	c0 98       	cbi	0x18, 0	; 24
+}
+ 318:	9f 91       	pop	r25
+ 31a:	8f 91       	pop	r24
+ 31c:	3f 91       	pop	r19
+ 31e:	2f 91       	pop	r18
+ 320:	0f 90       	pop	r0
+ 322:	0f be       	out	0x3f, r0	; 63
+ 324:	0f 90       	pop	r0
+ 326:	1f 90       	pop	r1
+ 328:	18 95       	reti
+
+0000032a <main>:
+
+int main(void)
+{
+	
+	rf12_init();					// ein paar Register setzen (z.B. CLK auf 10MHz)
+ 32a:	2f d0       	rcall	.+94     	; 0x38a <rf12_init>
+	rf12_setfreq(RF12FREQ(433.92));	// Sende/Empfangsfrequenz auf 433,92MHz einstellen
+ 32c:	80 e2       	ldi	r24, 0x20	; 32
+ 32e:	96 e0       	ldi	r25, 0x06	; 6
+ 330:	6c d0       	rcall	.+216    	; 0x40a <rf12_setfreq>
+	rf12_setbandwidth(1, 0, 7);		// 400kHz Bandbreite, 0dB Verstärkung, DRSSI threshold: -61dBm
+ 332:	81 e0       	ldi	r24, 0x01	; 1
+ 334:	60 e0       	ldi	r22, 0x00	; 0
+ 336:	47 e0       	ldi	r20, 0x07	; 7
+ 338:	4b d0       	rcall	.+150    	; 0x3d0 <rf12_setbandwidth>
+	rf12_setbaud(9600);				// 19200 baud
+ 33a:	80 e8       	ldi	r24, 0x80	; 128
+ 33c:	95 e2       	ldi	r25, 0x25	; 37
+ 33e:	74 d0       	rcall	.+232    	; 0x428 <rf12_setbaud>
+	rf12_setpower(0, 6);			// 1mW Ausgangsleistung, 120kHz Frequenzshift
+ 340:	80 e0       	ldi	r24, 0x00	; 0
+ 342:	66 e0       	ldi	r22, 0x06	; 6
+ 344:	94 d0       	rcall	.+296    	; 0x46e <rf12_setpower>
+		
+	init_timer();
+ 346:	6a df       	rcall	.-300    	; 0x21c <init_timer>
+	DDRB |= (1<<PINB1); //Led Auf Ausgang
+ 348:	b9 9a       	sbi	0x17, 1	; 23
+	DDRA &= ~(1<<PINA4); //SCK Eingang
+ 34a:	d4 98       	cbi	0x1a, 4	; 26
+	PORTA |= (1<<PINA4); //SCK Pullup
+ 34c:	dc 9a       	sbi	0x1b, 4	; 27
+	DDRA |= (1<<PINA6); //MOSI Ausgang
+ 34e:	d6 9a       	sbi	0x1a, 6	; 26
+	PORTA &= ~(1<<PINA6); //MOSI 0
+ 350:	de 98       	cbi	0x1b, 6	; 27
+	sei();
+ 352:	78 94       	sei
+	
+	//DDRB |= (1<<PINB1);
+    while(1)
+    {
+		recive();
+ 354:	16 df       	rcall	.-468    	; 0x182 <recive>
+ 356:	fe cf       	rjmp	.-4      	; 0x354 <main+0x2a>
+
+00000358 <rf12_trans>:
+unsigned short rf12_trans(unsigned short wert)
+{	
+	unsigned short werti = 0;
+	unsigned char i;
+	
+	RF_PORT &= ~(1<<CS);
+ 358:	d9 98       	cbi	0x1b, 1	; 27
+ 35a:	40 e1       	ldi	r20, 0x10	; 16
+#include "rf12.h"
+#include <util/delay.h>
+
+unsigned short rf12_trans(unsigned short wert)
+{	
+	unsigned short werti = 0;
+ 35c:	20 e0       	ldi	r18, 0x00	; 0
+ 35e:	30 e0       	ldi	r19, 0x00	; 0
+	unsigned char i;
+	
+	RF_PORT &= ~(1<<CS);
+	for (i=0; i<16; i++)
+	{	
+		if (wert&32768) {
+ 360:	99 23       	and	r25, r25
+ 362:	14 f4       	brge	.+4      	; 0x368 <rf12_trans+0x10>
+			RF_PORT |= (1<<SDI);
+ 364:	db 9a       	sbi	0x1b, 3	; 27
+ 366:	01 c0       	rjmp	.+2      	; 0x36a <rf12_trans+0x12>
+		}		
+		else {
+			RF_PORT &= ~(1<<SDI);
+ 368:	db 98       	cbi	0x1b, 3	; 27
+		}			
+		werti<<=1;
+ 36a:	22 0f       	add	r18, r18
+ 36c:	33 1f       	adc	r19, r19
+		if (RF_PIN & (1<<SDO)) {
+ 36e:	c8 99       	sbic	0x19, 0	; 25
+			werti|=1;
+ 370:	21 60       	ori	r18, 0x01	; 1
+		}		
+		RF_PORT |= (1<<SCK);
+ 372:	da 9a       	sbi	0x1b, 2	; 27
+		wert<<=1;
+ 374:	88 0f       	add	r24, r24
+ 376:	99 1f       	adc	r25, r25
+ 378:	00 c0       	rjmp	.+0      	; 0x37a <rf12_trans+0x22>
+ 37a:	00 00       	nop
+		_delay_us(0.3);
+		RF_PORT &= ~(1<<SCK);
+ 37c:	da 98       	cbi	0x1b, 2	; 27
+ 37e:	41 50       	subi	r20, 0x01	; 1
+{	
+	unsigned short werti = 0;
+	unsigned char i;
+	
+	RF_PORT &= ~(1<<CS);
+	for (i=0; i<16; i++)
+ 380:	79 f7       	brne	.-34     	; 0x360 <rf12_trans+0x8>
+		RF_PORT |= (1<<SCK);
+		wert<<=1;
+		_delay_us(0.3);
+		RF_PORT &= ~(1<<SCK);
+	}
+	RF_PORT |= (1<<CS);
+ 382:	d9 9a       	sbi	0x1b, 1	; 27
+	return werti;
+}
+ 384:	82 2f       	mov	r24, r18
+ 386:	93 2f       	mov	r25, r19
+ 388:	08 95       	ret
+
+0000038a <rf12_init>:
+
+void rf12_init(void)
+{
+	RF_DDR |= (1<<SDI) | (1<<SCK) | (1<<CS);
+ 38a:	8a b3       	in	r24, 0x1a	; 26
+ 38c:	8e 60       	ori	r24, 0x0E	; 14
+ 38e:	8a bb       	out	0x1a, r24	; 26
+	RF_PORT |= (1<<CS);
+ 390:	d9 9a       	sbi	0x1b, 1	; 27
+	#else
+		//round up by default
+		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
+	#endif
+
+	__builtin_avr_delay_cycles(__ticks_dc);
+ 392:	8f ef       	ldi	r24, 0xFF	; 255
+ 394:	90 e7       	ldi	r25, 0x70	; 112
+ 396:	a2 e0       	ldi	r26, 0x02	; 2
+ 398:	81 50       	subi	r24, 0x01	; 1
+ 39a:	90 40       	sbci	r25, 0x00	; 0
+ 39c:	a0 40       	sbci	r26, 0x00	; 0
+ 39e:	e1 f7       	brne	.-8      	; 0x398 <rf12_init+0xe>
+ 3a0:	00 c0       	rjmp	.+0      	; 0x3a2 <rf12_init+0x18>
+ 3a2:	00 00       	nop
+
+	_delay_ms(100);
+
+	rf12_trans(0xC0E0);			// AVR CLK: 10MHz
+ 3a4:	80 ee       	ldi	r24, 0xE0	; 224
+ 3a6:	90 ec       	ldi	r25, 0xC0	; 192
+ 3a8:	d7 df       	rcall	.-82     	; 0x358 <rf12_trans>
+	rf12_trans(0x80D7);			// Enable FIFO
+ 3aa:	87 ed       	ldi	r24, 0xD7	; 215
+ 3ac:	90 e8       	ldi	r25, 0x80	; 128
+ 3ae:	d4 df       	rcall	.-88     	; 0x358 <rf12_trans>
+	rf12_trans(0xC2AB);			// Data Filter: internal
+ 3b0:	8b ea       	ldi	r24, 0xAB	; 171
+ 3b2:	92 ec       	ldi	r25, 0xC2	; 194
+ 3b4:	d1 df       	rcall	.-94     	; 0x358 <rf12_trans>
+	rf12_trans(0xCA81);			// Set FIFO mode
+ 3b6:	81 e8       	ldi	r24, 0x81	; 129
+ 3b8:	9a ec       	ldi	r25, 0xCA	; 202
+ 3ba:	ce df       	rcall	.-100    	; 0x358 <rf12_trans>
+	rf12_trans(0xE000);			// disable wakeuptimer
+ 3bc:	80 e0       	ldi	r24, 0x00	; 0
+ 3be:	90 ee       	ldi	r25, 0xE0	; 224
+ 3c0:	cb df       	rcall	.-106    	; 0x358 <rf12_trans>
+	rf12_trans(0xC800);			// disable low duty cycle
+ 3c2:	80 e0       	ldi	r24, 0x00	; 0
+ 3c4:	98 ec       	ldi	r25, 0xC8	; 200
+ 3c6:	c8 df       	rcall	.-112    	; 0x358 <rf12_trans>
+	rf12_trans(0xC4F7);			// AFC settings: autotuning: -10kHz...+7,5kHz
+ 3c8:	87 ef       	ldi	r24, 0xF7	; 247
+ 3ca:	94 ec       	ldi	r25, 0xC4	; 196
+ 3cc:	c5 df       	rcall	.-118    	; 0x358 <rf12_trans>
+}
+ 3ce:	08 95       	ret
+
+000003d0 <rf12_setbandwidth>:
+
+void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
+{
+	rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
+ 3d0:	90 e0       	ldi	r25, 0x00	; 0
+ 3d2:	88 0f       	add	r24, r24
+ 3d4:	99 1f       	adc	r25, r25
+ 3d6:	82 95       	swap	r24
+ 3d8:	92 95       	swap	r25
+ 3da:	90 7f       	andi	r25, 0xF0	; 240
+ 3dc:	98 27       	eor	r25, r24
+ 3de:	80 7f       	andi	r24, 0xF0	; 240
+ 3e0:	98 27       	eor	r25, r24
+ 3e2:	90 70       	andi	r25, 0x00	; 0
+ 3e4:	50 e0       	ldi	r21, 0x00	; 0
+ 3e6:	47 70       	andi	r20, 0x07	; 7
+ 3e8:	50 70       	andi	r21, 0x00	; 0
+ 3ea:	84 2b       	or	r24, r20
+ 3ec:	95 2b       	or	r25, r21
+ 3ee:	94 69       	ori	r25, 0x94	; 148
+ 3f0:	70 e0       	ldi	r23, 0x00	; 0
+ 3f2:	63 70       	andi	r22, 0x03	; 3
+ 3f4:	70 70       	andi	r23, 0x00	; 0
+ 3f6:	66 0f       	add	r22, r22
+ 3f8:	77 1f       	adc	r23, r23
+ 3fa:	66 0f       	add	r22, r22
+ 3fc:	77 1f       	adc	r23, r23
+ 3fe:	66 0f       	add	r22, r22
+ 400:	77 1f       	adc	r23, r23
+ 402:	86 2b       	or	r24, r22
+ 404:	97 2b       	or	r25, r23
+ 406:	a8 df       	rcall	.-176    	; 0x358 <rf12_trans>
+}
+ 408:	08 95       	ret
+
+0000040a <rf12_setfreq>:
+
+void rf12_setfreq(unsigned short freq)
+{	
+	if (freq<96) {				// 430,2400MHz
+ 40a:	80 36       	cpi	r24, 0x60	; 96
+ 40c:	91 05       	cpc	r25, r1
+ 40e:	38 f0       	brcs	.+14     	; 0x41e <rf12_setfreq+0x14>
+ 410:	2f e0       	ldi	r18, 0x0F	; 15
+ 412:	80 34       	cpi	r24, 0x40	; 64
+ 414:	92 07       	cpc	r25, r18
+ 416:	28 f0       	brcs	.+10     	; 0x422 <rf12_setfreq+0x18>
+ 418:	8f e3       	ldi	r24, 0x3F	; 63
+ 41a:	9f e0       	ldi	r25, 0x0F	; 15
+ 41c:	02 c0       	rjmp	.+4      	; 0x422 <rf12_setfreq+0x18>
+		freq=96;
+ 41e:	80 e6       	ldi	r24, 0x60	; 96
+ 420:	90 e0       	ldi	r25, 0x00	; 0
+	} else if (freq>3903) {		// 439,7575MHz
+		freq=3903;
+	}	
+	rf12_trans(0xA000|freq);
+ 422:	90 6a       	ori	r25, 0xA0	; 160
+ 424:	99 df       	rcall	.-206    	; 0x358 <rf12_trans>
+}
+ 426:	08 95       	ret
+
+00000428 <rf12_setbaud>:
+
+void rf12_setbaud(unsigned short baud)
+{
+	if (baud<663) {
+ 428:	22 e0       	ldi	r18, 0x02	; 2
+ 42a:	87 39       	cpi	r24, 0x97	; 151
+ 42c:	92 07       	cpc	r25, r18
+ 42e:	f0 f0       	brcs	.+60     	; 0x46c <rf12_setbaud+0x44>
+		return;
+	}	
+	if (baud<5400) {				// Baudrate= 344827,58621/(R+1)/(1+CS*7)
+ 430:	25 e1       	ldi	r18, 0x15	; 21
+ 432:	88 31       	cpi	r24, 0x18	; 24
+ 434:	92 07       	cpc	r25, r18
+ 436:	70 f4       	brcc	.+28     	; 0x454 <rf12_setbaud+0x2c>
+		rf12_trans(0xC680|((43104/baud)-1));
+ 438:	9c 01       	movw	r18, r24
+ 43a:	40 e0       	ldi	r20, 0x00	; 0
+ 43c:	50 e0       	ldi	r21, 0x00	; 0
+ 43e:	60 e6       	ldi	r22, 0x60	; 96
+ 440:	78 ea       	ldi	r23, 0xA8	; 168
+ 442:	80 e0       	ldi	r24, 0x00	; 0
+ 444:	90 e0       	ldi	r25, 0x00	; 0
+ 446:	04 d1       	rcall	.+520    	; 0x650 <__divmodsi4>
+ 448:	c9 01       	movw	r24, r18
+ 44a:	01 97       	sbiw	r24, 0x01	; 1
+ 44c:	80 68       	ori	r24, 0x80	; 128
+ 44e:	96 6c       	ori	r25, 0xC6	; 198
+ 450:	83 df       	rcall	.-250    	; 0x358 <rf12_trans>
+ 452:	08 95       	ret
+	} else {
+		rf12_trans(0xC600|((344828UL/baud)-1));
+ 454:	9c 01       	movw	r18, r24
+ 456:	40 e0       	ldi	r20, 0x00	; 0
+ 458:	50 e0       	ldi	r21, 0x00	; 0
+ 45a:	6c ef       	ldi	r22, 0xFC	; 252
+ 45c:	72 e4       	ldi	r23, 0x42	; 66
+ 45e:	85 e0       	ldi	r24, 0x05	; 5
+ 460:	90 e0       	ldi	r25, 0x00	; 0
+ 462:	d4 d0       	rcall	.+424    	; 0x60c <__udivmodsi4>
+ 464:	c9 01       	movw	r24, r18
+ 466:	01 97       	sbiw	r24, 0x01	; 1
+ 468:	96 6c       	ori	r25, 0xC6	; 198
+ 46a:	76 df       	rcall	.-276    	; 0x358 <rf12_trans>
+ 46c:	08 95       	ret
+
+0000046e <rf12_setpower>:
+	}	
+}
+
+void rf12_setpower(unsigned char power, unsigned char mod)
+{
+	rf12_trans(0x9800|(power&7)|((mod&15)<<4));
+ 46e:	90 e0       	ldi	r25, 0x00	; 0
+ 470:	87 70       	andi	r24, 0x07	; 7
+ 472:	90 70       	andi	r25, 0x00	; 0
+ 474:	98 69       	ori	r25, 0x98	; 152
+ 476:	70 e0       	ldi	r23, 0x00	; 0
+ 478:	62 95       	swap	r22
+ 47a:	72 95       	swap	r23
+ 47c:	70 7f       	andi	r23, 0xF0	; 240
+ 47e:	76 27       	eor	r23, r22
+ 480:	60 7f       	andi	r22, 0xF0	; 240
+ 482:	76 27       	eor	r23, r22
+ 484:	70 70       	andi	r23, 0x00	; 0
+ 486:	86 2b       	or	r24, r22
+ 488:	97 2b       	or	r25, r23
+ 48a:	66 df       	rcall	.-308    	; 0x358 <rf12_trans>
+}
+ 48c:	08 95       	ret
+
+0000048e <rf12_ready>:
+
+void rf12_ready(void)
+{	
+	RF_PORT &= ~(1<<CS);
+ 48e:	d9 98       	cbi	0x1b, 1	; 27
+	while (!(RF_PIN & (1<<SDO))); // wait until FIFO ready
+ 490:	c8 9b       	sbis	0x19, 0	; 25
+ 492:	fe cf       	rjmp	.-4      	; 0x490 <rf12_ready+0x2>
+}
+ 494:	08 95       	ret
+
+00000496 <rf12_beginasyncrx>:
+
+void rf12_beginasyncrx() {
+	rf12_trans(0x82C8);			// RX on
+ 496:	88 ec       	ldi	r24, 0xC8	; 200
+ 498:	92 e8       	ldi	r25, 0x82	; 130
+ 49a:	5e df       	rcall	.-324    	; 0x358 <rf12_trans>
+	rf12_trans(0xCA81);			// set FIFO mode
+ 49c:	81 e8       	ldi	r24, 0x81	; 129
+ 49e:	9a ec       	ldi	r25, 0xCA	; 202
+ 4a0:	5b df       	rcall	.-330    	; 0x358 <rf12_trans>
+	rf12_trans(0xCA83);			// enable FIFO
+ 4a2:	83 e8       	ldi	r24, 0x83	; 131
+ 4a4:	9a ec       	ldi	r25, 0xCA	; 202
+ 4a6:	58 df       	rcall	.-336    	; 0x358 <rf12_trans>
+}
+ 4a8:	08 95       	ret
+
+000004aa <rf12_hasdata>:
+uint8_t rf12_hasdata() {
+	RF_PORT &= ~(1<<CS);
+ 4aa:	d9 98       	cbi	0x1b, 1	; 27
+	return !(RF_PIN & (1<<SDO));
+ 4ac:	81 e0       	ldi	r24, 0x01	; 1
+ 4ae:	c8 99       	sbic	0x19, 0	; 25
+ 4b0:	80 e0       	ldi	r24, 0x00	; 0
+}
+ 4b2:	08 95       	ret
+
+000004b4 <rf12_rxbyte>:
+uint8_t rf12_rxbyte() {
+	return rf12_trans(0xB000);
+ 4b4:	80 e0       	ldi	r24, 0x00	; 0
+ 4b6:	90 eb       	ldi	r25, 0xB0	; 176
+ 4b8:	4f df       	rcall	.-354    	; 0x358 <rf12_trans>
+}
+ 4ba:	08 95       	ret
+
+000004bc <rf12_endasyncrx>:
+void rf12_endasyncrx() {
+	rf12_trans(0x8208);			// RX off
+ 4bc:	88 e0       	ldi	r24, 0x08	; 8
+ 4be:	92 e8       	ldi	r25, 0x82	; 130
+ 4c0:	4b df       	rcall	.-362    	; 0x358 <rf12_trans>
+}
+ 4c2:	08 95       	ret
+
+000004c4 <rf12_txdata>:
+
+void rf12_txdata(unsigned char *data, unsigned char number)
+{	
+ 4c4:	0f 93       	push	r16
+ 4c6:	1f 93       	push	r17
+ 4c8:	cf 93       	push	r28
+ 4ca:	df 93       	push	r29
+ 4cc:	8c 01       	movw	r16, r24
+ 4ce:	c6 2f       	mov	r28, r22
+	unsigned char i;
+	rf12_trans(0x8238);			// TX on
+ 4d0:	88 e3       	ldi	r24, 0x38	; 56
+ 4d2:	92 e8       	ldi	r25, 0x82	; 130
+ 4d4:	41 df       	rcall	.-382    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 4d6:	db df       	rcall	.-74     	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 4d8:	8a ea       	ldi	r24, 0xAA	; 170
+ 4da:	98 eb       	ldi	r25, 0xB8	; 184
+ 4dc:	3d df       	rcall	.-390    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 4de:	d7 df       	rcall	.-82     	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 4e0:	8a ea       	ldi	r24, 0xAA	; 170
+ 4e2:	98 eb       	ldi	r25, 0xB8	; 184
+ 4e4:	39 df       	rcall	.-398    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 4e6:	d3 df       	rcall	.-90     	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 4e8:	8a ea       	ldi	r24, 0xAA	; 170
+ 4ea:	98 eb       	ldi	r25, 0xB8	; 184
+ 4ec:	35 df       	rcall	.-406    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 4ee:	cf df       	rcall	.-98     	; 0x48e <rf12_ready>
+	rf12_trans(0xB82D);
+ 4f0:	8d e2       	ldi	r24, 0x2D	; 45
+ 4f2:	98 eb       	ldi	r25, 0xB8	; 184
+ 4f4:	31 df       	rcall	.-414    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 4f6:	cb df       	rcall	.-106    	; 0x48e <rf12_ready>
+	rf12_trans(0xB8D4);
+ 4f8:	84 ed       	ldi	r24, 0xD4	; 212
+ 4fa:	98 eb       	ldi	r25, 0xB8	; 184
+ 4fc:	2d df       	rcall	.-422    	; 0x358 <rf12_trans>
+	for (i=0; i<number; i++)
+ 4fe:	cc 23       	and	r28, r28
+ 500:	89 f0       	breq	.+34     	; 0x524 <rf12_txdata+0x60>
+}
+void rf12_endasyncrx() {
+	rf12_trans(0x8208);			// RX off
+}
+
+void rf12_txdata(unsigned char *data, unsigned char number)
+ 502:	c8 01       	movw	r24, r16
+ 504:	01 96       	adiw	r24, 0x01	; 1
+ 506:	c1 50       	subi	r28, 0x01	; 1
+ 508:	9c 01       	movw	r18, r24
+ 50a:	2c 0f       	add	r18, r28
+ 50c:	31 1d       	adc	r19, r1
+ 50e:	e9 01       	movw	r28, r18
+	rf12_trans(0xB82D);
+	rf12_ready();
+	rf12_trans(0xB8D4);
+	for (i=0; i<number; i++)
+	{		
+		rf12_ready();
+ 510:	be df       	rcall	.-132    	; 0x48e <rf12_ready>
+		rf12_trans(0xB800|(*data++));
+ 512:	f8 01       	movw	r30, r16
+ 514:	81 91       	ld	r24, Z+
+ 516:	8f 01       	movw	r16, r30
+ 518:	90 e0       	ldi	r25, 0x00	; 0
+ 51a:	98 6b       	ori	r25, 0xB8	; 184
+ 51c:	1d df       	rcall	.-454    	; 0x358 <rf12_trans>
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB82D);
+	rf12_ready();
+	rf12_trans(0xB8D4);
+	for (i=0; i<number; i++)
+ 51e:	0c 17       	cp	r16, r28
+ 520:	1d 07       	cpc	r17, r29
+ 522:	b1 f7       	brne	.-20     	; 0x510 <rf12_txdata+0x4c>
+	{		
+		rf12_ready();
+		rf12_trans(0xB800|(*data++));
+	}
+	rf12_ready();
+ 524:	b4 df       	rcall	.-152    	; 0x48e <rf12_ready>
+	rf12_trans(0x8208);			// TX off
+ 526:	88 e0       	ldi	r24, 0x08	; 8
+ 528:	92 e8       	ldi	r25, 0x82	; 130
+ 52a:	16 df       	rcall	.-468    	; 0x358 <rf12_trans>
+}
+ 52c:	df 91       	pop	r29
+ 52e:	cf 91       	pop	r28
+ 530:	1f 91       	pop	r17
+ 532:	0f 91       	pop	r16
+ 534:	08 95       	ret
+
+00000536 <rf12_rxdata>:
+
+void rf12_rxdata(unsigned char *data, unsigned char number)
+{	
+ 536:	0f 93       	push	r16
+ 538:	1f 93       	push	r17
+ 53a:	cf 93       	push	r28
+ 53c:	df 93       	push	r29
+ 53e:	8c 01       	movw	r16, r24
+ 540:	d6 2f       	mov	r29, r22
+	unsigned char i;
+	rf12_trans(0x82C8);			// RX on
+ 542:	88 ec       	ldi	r24, 0xC8	; 200
+ 544:	92 e8       	ldi	r25, 0x82	; 130
+ 546:	08 df       	rcall	.-496    	; 0x358 <rf12_trans>
+	rf12_trans(0xCA81);			// set FIFO mode
+ 548:	81 e8       	ldi	r24, 0x81	; 129
+ 54a:	9a ec       	ldi	r25, 0xCA	; 202
+ 54c:	05 df       	rcall	.-502    	; 0x358 <rf12_trans>
+	rf12_trans(0xCA83);			// enable FIFO
+ 54e:	83 e8       	ldi	r24, 0x83	; 131
+ 550:	9a ec       	ldi	r25, 0xCA	; 202
+ 552:	02 df       	rcall	.-508    	; 0x358 <rf12_trans>
+	for (i=0; i<number; i++)
+ 554:	dd 23       	and	r29, r29
+ 556:	89 f0       	breq	.+34     	; 0x57a <rf12_rxdata+0x44>
+	}
+	rf12_ready();
+	rf12_trans(0x8208);			// TX off
+}
+
+void rf12_rxdata(unsigned char *data, unsigned char number)
+ 558:	c8 01       	movw	r24, r16
+ 55a:	01 96       	adiw	r24, 0x01	; 1
+ 55c:	d1 50       	subi	r29, 0x01	; 1
+ 55e:	9c 01       	movw	r18, r24
+ 560:	2d 0f       	add	r18, r29
+ 562:	31 1d       	adc	r19, r1
+ 564:	e9 01       	movw	r28, r18
+	rf12_trans(0x82C8);			// RX on
+	rf12_trans(0xCA81);			// set FIFO mode
+	rf12_trans(0xCA83);			// enable FIFO
+	for (i=0; i<number; i++)
+	{	
+		rf12_ready();
+ 566:	93 df       	rcall	.-218    	; 0x48e <rf12_ready>
+		*data++=rf12_trans(0xB000);
+ 568:	80 e0       	ldi	r24, 0x00	; 0
+ 56a:	90 eb       	ldi	r25, 0xB0	; 176
+ 56c:	f5 de       	rcall	.-534    	; 0x358 <rf12_trans>
+ 56e:	f8 01       	movw	r30, r16
+ 570:	81 93       	st	Z+, r24
+ 572:	8f 01       	movw	r16, r30
+{	
+	unsigned char i;
+	rf12_trans(0x82C8);			// RX on
+	rf12_trans(0xCA81);			// set FIFO mode
+	rf12_trans(0xCA83);			// enable FIFO
+	for (i=0; i<number; i++)
+ 574:	ec 17       	cp	r30, r28
+ 576:	fd 07       	cpc	r31, r29
+ 578:	b1 f7       	brne	.-20     	; 0x566 <rf12_rxdata+0x30>
+	{	
+		rf12_ready();
+		*data++=rf12_trans(0xB000);
+	}
+	rf12_trans(0x8208);			// RX off
+ 57a:	88 e0       	ldi	r24, 0x08	; 8
+ 57c:	92 e8       	ldi	r25, 0x82	; 130
+ 57e:	ec de       	rcall	.-552    	; 0x358 <rf12_trans>
+}
+ 580:	df 91       	pop	r29
+ 582:	cf 91       	pop	r28
+ 584:	1f 91       	pop	r17
+ 586:	0f 91       	pop	r16
+ 588:	08 95       	ret
+
+0000058a <rf12_txpacket>:
+
+void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) {
+ 58a:	1f 93       	push	r17
+ 58c:	cf 93       	push	r28
+ 58e:	df 93       	push	r29
+ 590:	18 2f       	mov	r17, r24
+ 592:	d6 2f       	mov	r29, r22
+ 594:	c4 2f       	mov	r28, r20
+	rf12_trans(0x8238);			// TX on
+ 596:	88 e3       	ldi	r24, 0x38	; 56
+ 598:	92 e8       	ldi	r25, 0x82	; 130
+ 59a:	de de       	rcall	.-580    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 59c:	78 df       	rcall	.-272    	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 59e:	8a ea       	ldi	r24, 0xAA	; 170
+ 5a0:	98 eb       	ldi	r25, 0xB8	; 184
+ 5a2:	da de       	rcall	.-588    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5a4:	74 df       	rcall	.-280    	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 5a6:	8a ea       	ldi	r24, 0xAA	; 170
+ 5a8:	98 eb       	ldi	r25, 0xB8	; 184
+ 5aa:	d6 de       	rcall	.-596    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5ac:	70 df       	rcall	.-288    	; 0x48e <rf12_ready>
+	rf12_trans(0xB8AA);
+ 5ae:	8a ea       	ldi	r24, 0xAA	; 170
+ 5b0:	98 eb       	ldi	r25, 0xB8	; 184
+ 5b2:	d2 de       	rcall	.-604    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5b4:	6c df       	rcall	.-296    	; 0x48e <rf12_ready>
+	rf12_trans(0xB82D);
+ 5b6:	8d e2       	ldi	r24, 0x2D	; 45
+ 5b8:	98 eb       	ldi	r25, 0xB8	; 184
+ 5ba:	ce de       	rcall	.-612    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5bc:	68 df       	rcall	.-304    	; 0x48e <rf12_ready>
+	rf12_trans(0xB8D4);
+ 5be:	84 ed       	ldi	r24, 0xD4	; 212
+ 5c0:	98 eb       	ldi	r25, 0xB8	; 184
+ 5c2:	ca de       	rcall	.-620    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5c4:	64 df       	rcall	.-312    	; 0x48e <rf12_ready>
+	rf12_trans(0xB800|addr);
+ 5c6:	81 2f       	mov	r24, r17
+ 5c8:	90 e0       	ldi	r25, 0x00	; 0
+ 5ca:	98 6b       	ori	r25, 0xB8	; 184
+ 5cc:	c5 de       	rcall	.-630    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5ce:	5f df       	rcall	.-322    	; 0x48e <rf12_ready>
+	rf12_trans(0xB800|from);
+ 5d0:	8d 2f       	mov	r24, r29
+ 5d2:	90 e0       	ldi	r25, 0x00	; 0
+ 5d4:	98 6b       	ori	r25, 0xB8	; 184
+ 5d6:	c0 de       	rcall	.-640    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5d8:	5a df       	rcall	.-332    	; 0x48e <rf12_ready>
+	rf12_trans(0xB800|data);
+ 5da:	8c 2f       	mov	r24, r28
+ 5dc:	90 e0       	ldi	r25, 0x00	; 0
+ 5de:	98 6b       	ori	r25, 0xB8	; 184
+ 5e0:	bb de       	rcall	.-650    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5e2:	55 df       	rcall	.-342    	; 0x48e <rf12_ready>
+	rf12_trans(0xB800);
+ 5e4:	80 e0       	ldi	r24, 0x00	; 0
+ 5e6:	98 eb       	ldi	r25, 0xB8	; 184
+ 5e8:	b7 de       	rcall	.-658    	; 0x358 <rf12_trans>
+	rf12_ready();
+ 5ea:	51 df       	rcall	.-350    	; 0x48e <rf12_ready>
+	rf12_trans(0x8208); // TX off
+ 5ec:	88 e0       	ldi	r24, 0x08	; 8
+ 5ee:	92 e8       	ldi	r25, 0x82	; 130
+ 5f0:	b3 de       	rcall	.-666    	; 0x358 <rf12_trans>
+ 5f2:	8f ef       	ldi	r24, 0xFF	; 255
+ 5f4:	90 e7       	ldi	r25, 0x70	; 112
+ 5f6:	a2 e0       	ldi	r26, 0x02	; 2
+ 5f8:	81 50       	subi	r24, 0x01	; 1
+ 5fa:	90 40       	sbci	r25, 0x00	; 0
+ 5fc:	a0 40       	sbci	r26, 0x00	; 0
+ 5fe:	e1 f7       	brne	.-8      	; 0x5f8 <rf12_txpacket+0x6e>
+ 600:	00 c0       	rjmp	.+0      	; 0x602 <rf12_txpacket+0x78>
+ 602:	00 00       	nop
+	_delay_ms(100);
+ 604:	df 91       	pop	r29
+ 606:	cf 91       	pop	r28
+ 608:	1f 91       	pop	r17
+ 60a:	08 95       	ret
+
+0000060c <__udivmodsi4>:
+ 60c:	a1 e2       	ldi	r26, 0x21	; 33
+ 60e:	1a 2e       	mov	r1, r26
+ 610:	aa 1b       	sub	r26, r26
+ 612:	bb 1b       	sub	r27, r27
+ 614:	fd 01       	movw	r30, r26
+ 616:	0d c0       	rjmp	.+26     	; 0x632 <__udivmodsi4_ep>
+
+00000618 <__udivmodsi4_loop>:
+ 618:	aa 1f       	adc	r26, r26
+ 61a:	bb 1f       	adc	r27, r27
+ 61c:	ee 1f       	adc	r30, r30
+ 61e:	ff 1f       	adc	r31, r31
+ 620:	a2 17       	cp	r26, r18
+ 622:	b3 07       	cpc	r27, r19
+ 624:	e4 07       	cpc	r30, r20
+ 626:	f5 07       	cpc	r31, r21
+ 628:	20 f0       	brcs	.+8      	; 0x632 <__udivmodsi4_ep>
+ 62a:	a2 1b       	sub	r26, r18
+ 62c:	b3 0b       	sbc	r27, r19
+ 62e:	e4 0b       	sbc	r30, r20
+ 630:	f5 0b       	sbc	r31, r21
+
+00000632 <__udivmodsi4_ep>:
+ 632:	66 1f       	adc	r22, r22
+ 634:	77 1f       	adc	r23, r23
+ 636:	88 1f       	adc	r24, r24
+ 638:	99 1f       	adc	r25, r25
+ 63a:	1a 94       	dec	r1
+ 63c:	69 f7       	brne	.-38     	; 0x618 <__udivmodsi4_loop>
+ 63e:	60 95       	com	r22
+ 640:	70 95       	com	r23
+ 642:	80 95       	com	r24
+ 644:	90 95       	com	r25
+ 646:	9b 01       	movw	r18, r22
+ 648:	ac 01       	movw	r20, r24
+ 64a:	bd 01       	movw	r22, r26
+ 64c:	cf 01       	movw	r24, r30
+ 64e:	08 95       	ret
+
+00000650 <__divmodsi4>:
+ 650:	97 fb       	bst	r25, 7
+ 652:	09 2e       	mov	r0, r25
+ 654:	05 26       	eor	r0, r21
+ 656:	0e d0       	rcall	.+28     	; 0x674 <__divmodsi4_neg1>
+ 658:	57 fd       	sbrc	r21, 7
+ 65a:	04 d0       	rcall	.+8      	; 0x664 <__divmodsi4_neg2>
+ 65c:	d7 df       	rcall	.-82     	; 0x60c <__udivmodsi4>
+ 65e:	0a d0       	rcall	.+20     	; 0x674 <__divmodsi4_neg1>
+ 660:	00 1c       	adc	r0, r0
+ 662:	38 f4       	brcc	.+14     	; 0x672 <__divmodsi4_exit>
+
+00000664 <__divmodsi4_neg2>:
+ 664:	50 95       	com	r21
+ 666:	40 95       	com	r20
+ 668:	30 95       	com	r19
+ 66a:	21 95       	neg	r18
+ 66c:	3f 4f       	sbci	r19, 0xFF	; 255
+ 66e:	4f 4f       	sbci	r20, 0xFF	; 255
+ 670:	5f 4f       	sbci	r21, 0xFF	; 255
+
+00000672 <__divmodsi4_exit>:
+ 672:	08 95       	ret
+
+00000674 <__divmodsi4_neg1>:
+ 674:	f6 f7       	brtc	.-4      	; 0x672 <__divmodsi4_exit>
+ 676:	90 95       	com	r25
+ 678:	80 95       	com	r24
+ 67a:	70 95       	com	r23
+ 67c:	61 95       	neg	r22
+ 67e:	7f 4f       	sbci	r23, 0xFF	; 255
+ 680:	8f 4f       	sbci	r24, 0xFF	; 255
+ 682:	9f 4f       	sbci	r25, 0xFF	; 255
+ 684:	08 95       	ret
+
+00000686 <_exit>:
+ 686:	f8 94       	cli
+
+00000688 <__stop_program>:
+ 688:	ff cf       	rjmp	.-2      	; 0x688 <__stop_program>
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.map b/V5B/Reciver/Reciver/Debug/Reciver.map
new file mode 100644
index 0000000..790ace8
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.map
@@ -0,0 +1,430 @@
+Archive member included because of file (symbol)
+
+c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_udivmodsi4.o)
+                              rf12.o (__udivmodsi4)
+c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_divmodsi4.o)
+                              rf12.o (__divmodsi4)
+c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_exit.o)
+                              c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr25/crttn24a.o (exit)
+c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_copy_data.o)
+                              Reciver.o (__do_copy_data)
+c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_clear_bss.o)
+                              Reciver.o (__do_clear_bss)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+text             0x00000000         0x00002000         xr
+data             0x00800060         0x0000ffa0         rw !x
+eeprom           0x00810000         0x00010000         rw !x
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+signature        0x00840000         0x00000400         rw !x
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr25/crttn24a.o
+LOAD Reciver.o
+LOAD rf12.o
+START GROUP
+LOAD c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr25\libm.a
+END GROUP
+LOAD c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a
+LOAD c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr25\libc.a
+LOAD c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a
+
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+ *(.gnu.version_r)
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+                0x00000000                __vector_default
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+ SORT(*)(.ctors)
+ SORT(*)(.dtors)
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+                0x00000022                __init
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+ *(.init9)
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+                0x00000054                __vector_1
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+ *(.debug_abbrev)
+ .debug_abbrev  0x00000000      0x189 Reciver.o
+ .debug_abbrev  0x00000189      0x19b rf12.o
+ .debug_abbrev  0x00000324       0x14 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_udivmodsi4.o)
+ .debug_abbrev  0x00000338       0x14 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_divmodsi4.o)
+ .debug_abbrev  0x0000034c       0x14 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_exit.o)
+ .debug_abbrev  0x00000360       0x14 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_copy_data.o)
+ .debug_abbrev  0x00000374       0x14 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_clear_bss.o)
+
+.debug_line     0x00000000      0x74d
+ *(.debug_line)
+ .debug_line    0x00000000      0x23b Reciver.o
+ .debug_line    0x0000023b      0x222 rf12.o
+ .debug_line    0x0000045d       0xa8 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_udivmodsi4.o)
+ .debug_line    0x00000505       0xa1 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_divmodsi4.o)
+ .debug_line    0x000005a6       0x88 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_exit.o)
+ .debug_line    0x0000062e       0x91 c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_copy_data.o)
+ .debug_line    0x000006bf       0x8e c:/program files (x86)/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr25\libgcc.a(_clear_bss.o)
+
+.debug_frame    0x00000000      0x1c8
+ *(.debug_frame)
+ .debug_frame   0x00000000       0x9c Reciver.o
+ .debug_frame   0x0000009c      0x12c rf12.o
+
+.debug_str      0x00000000      0x25c
+ *(.debug_str)
+ .debug_str     0x00000000      0x165 Reciver.o
+                                0x19e (size before relaxing)
+ .debug_str     0x00000165       0xf7 rf12.o
+                                0x25b (size before relaxing)
+
+.debug_loc      0x00000000      0x6d5
+ *(.debug_loc)
+ .debug_loc     0x00000000      0x393 Reciver.o
+ .debug_loc     0x00000393      0x342 rf12.o
+
+.debug_macinfo
+ *(.debug_macinfo)
+OUTPUT(Reciver.elf elf32-avr)
+LOAD linker stubs
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.srec b/V5B/Reciver/Reciver/Debug/Reciver.srec
new file mode 100644
index 0000000..279bb2c
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/Reciver.srec
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diff --git a/V5B/Reciver/Reciver/Debug/makedep.mk b/V5B/Reciver/Reciver/Debug/makedep.mk
new file mode 100644
index 0000000..562bd5a
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/makedep.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+Reciver.c
+
+rf12.c
+
diff --git a/V5B/Reciver/Reciver/Debug/rf12.d b/V5B/Reciver/Reciver/Debug/rf12.d
new file mode 100644
index 0000000..3c81315
--- /dev/null
+++ b/V5B/Reciver/Reciver/Debug/rf12.d
@@ -0,0 +1,48 @@
+rf12.d rf12.o: .././rf12.c \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/io.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/sfr_defs.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/inttypes.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/include/stdint.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/stdint.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/iotn24a.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/portpins.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/common.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/version.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/fuse.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/lock.h \
+ .././rf12.h .././global.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay_basic.h \
+ c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/math.h
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/io.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/sfr_defs.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/inttypes.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/include/stdint.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/stdint.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/iotn24a.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/portpins.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/common.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/version.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/fuse.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/avr/lock.h:
+
+.././rf12.h:
+
+.././global.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/util/delay_basic.h:
+
+c:\program\ files\ (x86)\atmel\atmel\ studio\ 6.0\extensions\atmel\avrgcc\3.4.1.95\avrtoolchain\bin\../lib/gcc/avr/4.6.2/../../../../avr/include/math.h:
diff --git a/V5B/Reciver/Reciver/Reciver.c b/V5B/Reciver/Reciver/Reciver.c
new file mode 100644
index 0000000..6bf80df
--- /dev/null
+++ b/V5B/Reciver/Reciver/Reciver.c
@@ -0,0 +1,182 @@
+/*
+ * Reciver.c
+ *
+ * Created: 25.03.2013 21:03:07
+ *  Author: netz
+ */ 
+
+#include "global.h"
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <util/delay.h>
+#include "rf12.h"
+#include "codes.h"
+
+
+volatile int status = SLEEP;
+volatile int pwm_led = 0;
+
+volatile int servopos = RIGHT;
+
+void turn() {
+	if(status == RUN)
+		return;
+	status = RUN;
+	servopos = RIGHT-60;
+	_delay_ms(10+DEVICE);
+	rf12_txpacket(MASTER, DEVICE, status);
+	_delay_ms(700);
+	servopos = RIGHT-120;
+	_delay_ms(700);
+	servopos = RIGHT;
+	_delay_ms(700);
+}
+
+void poll() {
+	DDRB &= ~(1<<PINB2);
+	if(status == ACTIVE) {
+		if(PINB & (1<<PINB2)) {
+			rf12_endasyncrx();
+			turn();
+			rf12_beginasyncrx();
+		}
+	}
+	if(status == SLEEP) {
+		if(PINB & (1<<PINB2)) {
+			rf12_endasyncrx();
+			rf12_txpacket(MASTER, DEVICE, DEDECT);
+			rf12_beginasyncrx();
+		}			
+	}
+	if(!(PINA & (1<<PINA4))) { //SCK auf 0
+		if(status == SLEEP) {
+			status = RUN;
+			_delay_ms(5000);
+			_delay_ms(5000);
+			_delay_ms(5000);
+			status = ACTIVE;
+		}
+	}
+}
+
+void recive() {
+	rf12_beginasyncrx();
+	while(rf12_hasdata()) {
+		poll();
+	}
+	uint8_t addr = rf12_rxbyte();
+	if(addr == ALL || addr == DEVICE || addr == GROUP) {
+		while(rf12_hasdata()) {
+			poll();
+		}
+		uint8_t from = rf12_rxbyte();
+		while(rf12_hasdata()) {
+			poll();
+		}
+		if(from == MASTER) {
+			uint8_t data = rf12_rxbyte();
+			switch(data) {
+				case PING: {
+					break;
+				}
+				case SETSLEEP: {
+					status = SLEEP;
+					break;
+				}
+				case SETACTIVE: {
+					status = ACTIVE;
+					break;
+				}
+				case SETRUN: {
+					rf12_endasyncrx();
+					turn();
+					rf12_beginasyncrx();
+					return;
+				}
+				default:
+				{
+					rf12_endasyncrx();
+					return;
+				}
+			}
+			rf12_endasyncrx();
+			_delay_ms(10+DEVICE);
+			rf12_txpacket(MASTER, DEVICE, status);
+			return;
+		}					
+	}
+}
+
+void init_timer() {
+	// Timer/Counter 0 initialization
+	// Clock source: System Clock
+	// Clock value: 7,813 kHz
+	// Mode: Normal top=0xFF
+	// OC0A output: Disconnected
+	// OC0B output: Disconnected
+	// Timer Period: 21,504 ms
+	TCCR0A = (0<<COM0A1) | (0<<COM0A0) | (0<<COM0B1) | (0<<COM0B0) | (0<<WGM01) | (0<<WGM00);
+	TCCR0B = (0<<WGM02) | (1<<CS02) | (0<<CS01) | (1<<CS00);
+	TCNT0 = 0x58;
+	
+	// Timer/Counter 0 Interrupt(s) initialization
+	TIMSK0=(0<<OCIE0B) | (0<<OCIE0A) | (1<<TOIE0);
+}
+
+ISR(TIM0_OVF_vect) {
+	// Reinitialize Timer 0 value
+	TCNT0=0x58;
+	
+	if(status == SLEEP) {
+		if(pwm_led > 50) {
+			PORTB ^= (1<<PINB1);
+			pwm_led = 0;
+		}					
+	} else if(status == ACTIVE) {
+		if(pwm_led > 5) {
+			PORTB ^= (1<<PINB1);
+			pwm_led = 0;
+		}
+	} else if(status == RUN) {
+		if(pwm_led > 1) {
+			PORTB ^= (1<<PINB1);
+			pwm_led = 0;
+		}
+	}
+	pwm_led++;	
+	
+	DDRB |= (1<<PINB0);
+	PORTB |= (1<<PINB0);
+	_delay_us(LEFT);
+	for(int i=0;i<servopos;i++) {
+		_delay_us(STEP);
+	}
+	PORTB &= ~(1<<PINB0);
+}
+
+int main(void)
+{
+	
+	rf12_init();					// ein paar Register setzen (z.B. CLK auf 10MHz)
+	rf12_setfreq(RF12FREQ(433.92));	// Sende/Empfangsfrequenz auf 433,92MHz einstellen
+	rf12_setbandwidth(1, 0, 7);		// 400kHz Bandbreite, 0dB Verstärkung, DRSSI threshold: -61dBm
+	rf12_setbaud(9600);				// 19200 baud
+	rf12_setpower(0, 6);			// 1mW Ausgangsleistung, 120kHz Frequenzshift
+		
+	init_timer();
+	DDRB |= (1<<PINB1); //Led Auf Ausgang
+	DDRA &= ~(1<<PINA4); //SCK Eingang
+	PORTA |= (1<<PINA4); //SCK Pullup
+	DDRA |= (1<<PINA6); //MOSI Ausgang
+	PORTA &= ~(1<<PINA6); //MOSI 0
+	sei();
+	
+	//DDRB |= (1<<PINB1);
+    while(1)
+    {
+		recive();
+		//PORTB ^= (1<<PINB1);
+		//_delay_ms(100);
+    }
+}
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/Reciver.cproj b/V5B/Reciver/Reciver/Reciver.cproj
new file mode 100644
index 0000000..53354c6
--- /dev/null
+++ b/V5B/Reciver/Reciver/Reciver.cproj
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>6.0</ProjectVersion>
+    <ToolchainName>com.Atmel.AVRGCC8</ToolchainName>
+    <ProjectGuid>{762e00f9-912f-4c48-851f-1f51c060e5ae}</ProjectGuid>
+    <avrdevice>ATtiny24A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>C</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Reciver</AssemblyName>
+    <Name>Reciver</Name>
+    <RootNamespace>Reciver</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <OverrideVtorValue />
+    <eraseonlaunchrule>0</eraseonlaunchrule>
+    <AsfVersion>3.5.1</AsfVersion>
+    <avrtool>com.atmel.avrdbg.tool.ispmk2</avrtool>
+    <avrtoolinterface>ISP</avrtoolinterface>
+    <com_atmel_avrdbg_tool_ispmk2>
+      <ToolType>com.atmel.avrdbg.tool.ispmk2</ToolType>
+      <ToolName>AVRISP mkII</ToolName>
+      <ToolNumber>0000000000000</ToolNumber>
+      <KeepTimersRunning>true</KeepTimersRunning>
+      <OverrideVtor>false</OverrideVtor>
+      <OverrideVtorValue>
+      </OverrideVtorValue>
+      <Channel>
+        <host>127.0.0.1</host>
+        <port>65052</port>
+        <ssl>False</ssl>
+      </Channel>
+      <ToolOptions>
+        <InterfaceName>ISP</InterfaceName>
+        <InterfaceProperties>
+          <JtagDbgClock>249000</JtagDbgClock>
+          <JtagProgClock>1000000</JtagProgClock>
+          <IspClock>250000</IspClock>
+          <JtagInChain>false</JtagInChain>
+          <JtagEnableExtResetOnStartSession>false</JtagEnableExtResetOnStartSession>
+          <JtagDevicesBefore>0</JtagDevicesBefore>
+          <JtagDevicesAfter>0</JtagDevicesAfter>
+          <JtagInstrBitsBefore>0</JtagInstrBitsBefore>
+          <JtagInstrBitsAfter>0</JtagInstrBitsAfter>
+        </InterfaceProperties>
+      </ToolOptions>
+    </com_atmel_avrdbg_tool_ispmk2>
+    <com_atmel_avrdbg_tool_simulator>
+      <ToolType>com.atmel.avrdbg.tool.simulator</ToolType>
+      <ToolName>AVR Simulator</ToolName>
+      <ToolNumber>
+      </ToolNumber>
+      <KeepTimersRunning>true</KeepTimersRunning>
+      <OverrideVtor>false</OverrideVtor>
+      <OverrideVtorValue>
+      </OverrideVtorValue>
+      <Channel>
+        <host>127.0.0.1</host>
+        <port>49418</port>
+        <ssl>False</ssl>
+      </Channel>
+    </com_atmel_avrdbg_tool_simulator>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <AvrGcc>
+        <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex>
+        <avrgcc.common.outputfiles.lss>True</avrgcc.common.outputfiles.lss>
+        <avrgcc.common.outputfiles.eep>True</avrgcc.common.outputfiles.eep>
+        <avrgcc.common.outputfiles.srec>True</avrgcc.common.outputfiles.srec>
+        <avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>
+        <avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>
+        <avrgcc.compiler.optimization.level>Optimize for size (-Os)</avrgcc.compiler.optimization.level>
+        <avrgcc.compiler.optimization.OtherFlags>-fdata-sections</avrgcc.compiler.optimization.OtherFlags>
+        <avrgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</avrgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers>
+        <avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum>
+        <avrgcc.compiler.warnings.AllWarnings>True</avrgcc.compiler.warnings.AllWarnings>
+        <avrgcc.linker.libraries.Libraries>
+          <ListValues>
+            <Value>m</Value>
+          </ListValues>
+        </avrgcc.linker.libraries.Libraries>
+        <avrgcc.linker.optimization.GarbageCollectUnusedSections>True</avrgcc.linker.optimization.GarbageCollectUnusedSections>
+      </AvrGcc>
+    </ToolchainSettings>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <AvrGcc>
+        <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex>
+        <avrgcc.common.outputfiles.lss>True</avrgcc.common.outputfiles.lss>
+        <avrgcc.common.outputfiles.eep>True</avrgcc.common.outputfiles.eep>
+        <avrgcc.common.outputfiles.srec>True</avrgcc.common.outputfiles.srec>
+        <avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>
+        <avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>
+        <avrgcc.compiler.optimization.level>Optimize (-O1)</avrgcc.compiler.optimization.level>
+        <avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers>
+        <avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum>
+        <avrgcc.compiler.optimization.DebugLevel>Default (-g2)</avrgcc.compiler.optimization.DebugLevel>
+        <avrgcc.compiler.warnings.AllWarnings>True</avrgcc.compiler.warnings.AllWarnings>
+        <avrgcc.linker.libraries.Libraries>
+          <ListValues>
+            <Value>m</Value>
+          </ListValues>
+        </avrgcc.linker.libraries.Libraries>
+        <avrgcc.assembler.debugging.DebugLevel>Default (-Wa,-g)</avrgcc.assembler.debugging.DebugLevel>
+      </AvrGcc>
+    </ToolchainSettings>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="codes.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="global.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="Reciver.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="rf12.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="rf12.h">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/Release/Makefile b/V5B/Reciver/Reciver/Release/Makefile
new file mode 100644
index 0000000..adb74fb
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Makefile
@@ -0,0 +1,130 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS := 
+PROJ := 
+
+O_SRCS := 
+C_SRCS := 
+S_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+PREPROCESSING_SRCS := 
+OBJS := 
+OBJS_AS_ARGS := 
+C_DEPS := 
+C_DEPS_AS_ARGS := 
+EXECUTABLES := 
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := 
+
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS +=  \
+../Reciver.c \
+../rf12.c
+
+
+PREPROCESSING_SRCS += 
+
+
+ASM_SRCS += 
+
+
+OBJS +=  \
+Reciver.o \
+rf12.o
+
+
+OBJS_AS_ARGS +=  \
+Reciver.o \
+rf12.o
+
+
+C_DEPS +=  \
+Reciver.d \
+rf12.d
+
+
+C_DEPS_AS_ARGS +=  \
+Reciver.d \
+rf12.d
+
+
+OUTPUT_FILE_PATH +=Reciver.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +=Reciver.elf
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+# AVR32/GNU C Compiler
+
+
+
+
+
+./%.o: .././%.c
+	@echo Building file: $<
+	@echo Invoking: AVR/GNU C Compiler : (AVR_8_bit_GNU_Toolchain_3.4.1_830) 4.6.2
+	$(QUOTE)E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-gcc.exe$(QUOTE) -funsigned-char -funsigned-bitfields -Os -fpack-struct -fshort-enums -Wall -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"  -mmcu=atmega16a   -o"$@" "$<" 
+	@echo Finished building: $<
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables 
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP)
+	@echo Building target: $@
+	@echo Invoking: AVR/GNU Linker : (AVR_8_bit_GNU_Toolchain_3.4.1_830) 4.6.2
+	$(QUOTE)E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="Reciver.map" -Wl,--start-group -Wl,-lm  -Wl,--end-group  -mmcu=atmega16a  
+	@echo Finished building target: $@
+	"E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature  "Reciver.elf" "Reciver.hex"
+	"E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -j .eeprom  --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0  --no-change-warnings -O ihex "Reciver.elf" "Reciver.eep" || exit 0
+	"E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objdump.exe" -h -S "Reciver.elf" > "Reciver.lss"
+	"E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature  "Reciver.elf" "Reciver.srec"
+	"E:\Programme\Atmel\Atmel Studio 6.0\extensions\Atmel\AVRGCC\3.4.1.95\AVRToolchain\bin\avr-size.exe" "Reciver.elf"
+	
+
+
+
+
+
+# Other Targets
+clean:
+	-$(RM) $(OBJS_AS_ARGS)$(C_DEPS_AS_ARGS) $(EXECUTABLES) 
+	rm -rf "Reciver.elf" "Reciver.a" "Reciver.hex" "Reciver.lss" "Reciver.eep" "Reciver.map" "Reciver.srec"
+	
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/Release/Reciver.eep b/V5B/Reciver/Reciver/Release/Reciver.eep
new file mode 100644
index 0000000..1996e8f
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Reciver.eep
@@ -0,0 +1 @@
+:00000001FF
diff --git a/V5B/Reciver/Reciver/Release/Reciver.elf b/V5B/Reciver/Reciver/Release/Reciver.elf
new file mode 100644
index 0000000..ab9d5a5
Binary files /dev/null and b/V5B/Reciver/Reciver/Release/Reciver.elf differ
diff --git a/V5B/Reciver/Reciver/Release/Reciver.hex b/V5B/Reciver/Reciver/Release/Reciver.hex
new file mode 100644
index 0000000..76a0b44
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Reciver.hex
@@ -0,0 +1,118 @@
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+:100720004F4F5F4F0895F6F79095809570956195BE
+:0C0730007F4F8F4F9F4F0895F894FFCF2C
+:04073C00B400020003
+:00000001FF
diff --git a/V5B/Reciver/Reciver/Release/Reciver.lss b/V5B/Reciver/Reciver/Release/Reciver.lss
new file mode 100644
index 0000000..92e7be9
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Reciver.lss
@@ -0,0 +1,862 @@
+
+Reciver.elf:     file format elf32-avr
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         0000073c  00000000  00000000  00000094  2**1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         00000004  00800060  0000073c  000007d0  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000002  00800064  00800064  000007d4  2**0
+                  ALLOC
+  3 .stab         000006cc  00000000  00000000  000007d4  2**2
+                  CONTENTS, READONLY, DEBUGGING
+  4 .stabstr      00000085  00000000  00000000  00000ea0  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  5 .debug_aranges 000000a0  00000000  00000000  00000f28  2**3
+                  CONTENTS, READONLY, DEBUGGING
+  6 .debug_info   00000451  00000000  00000000  00000fc8  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  7 .debug_abbrev 00000064  00000000  00000000  00001419  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  8 .debug_line   000002f0  00000000  00000000  0000147d  2**0
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <__vectors>:
+   0:	0c 94 2a 00 	jmp	0x54	; 0x54 <__ctors_end>
+   4:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+   8:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+   c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  10:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  14:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  18:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  1c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  20:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  24:	0c 94 48 01 	jmp	0x290	; 0x290 <__vector_9>
+  28:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  2c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  30:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  34:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  38:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  3c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  40:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  44:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  48:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  4c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+  50:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
+
+00000054 <__ctors_end>:
+  54:	11 24       	eor	r1, r1
+  56:	1f be       	out	0x3f, r1	; 63
+  58:	cf e5       	ldi	r28, 0x5F	; 95
+  5a:	d4 e0       	ldi	r29, 0x04	; 4
+  5c:	de bf       	out	0x3e, r29	; 62
+  5e:	cd bf       	out	0x3d, r28	; 61
+
+00000060 <__do_copy_data>:
+  60:	10 e0       	ldi	r17, 0x00	; 0
+  62:	a0 e6       	ldi	r26, 0x60	; 96
+  64:	b0 e0       	ldi	r27, 0x00	; 0
+  66:	ec e3       	ldi	r30, 0x3C	; 60
+  68:	f7 e0       	ldi	r31, 0x07	; 7
+  6a:	02 c0       	rjmp	.+4      	; 0x70 <__do_copy_data+0x10>
+  6c:	05 90       	lpm	r0, Z+
+  6e:	0d 92       	st	X+, r0
+  70:	a4 36       	cpi	r26, 0x64	; 100
+  72:	b1 07       	cpc	r27, r17
+  74:	d9 f7       	brne	.-10     	; 0x6c <__do_copy_data+0xc>
+
+00000076 <__do_clear_bss>:
+  76:	10 e0       	ldi	r17, 0x00	; 0
+  78:	a4 e6       	ldi	r26, 0x64	; 100
+  7a:	b0 e0       	ldi	r27, 0x00	; 0
+  7c:	01 c0       	rjmp	.+2      	; 0x80 <.do_clear_bss_start>
+
+0000007e <.do_clear_bss_loop>:
+  7e:	1d 92       	st	X+, r1
+
+00000080 <.do_clear_bss_start>:
+  80:	a6 36       	cpi	r26, 0x66	; 102
+  82:	b1 07       	cpc	r27, r17
+  84:	e1 f7       	brne	.-8      	; 0x7e <.do_clear_bss_loop>
+  86:	0e 94 41 03 	call	0x682	; 0x682 <main>
+  8a:	0c 94 9c 03 	jmp	0x738	; 0x738 <_exit>
+
+0000008e <__bad_interrupt>:
+  8e:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>
+
+00000092 <turn>:
+  92:	80 91 62 00 	lds	r24, 0x0062
+  96:	90 91 63 00 	lds	r25, 0x0063
+  9a:	86 30       	cpi	r24, 0x06	; 6
+  9c:	91 05       	cpc	r25, r1
+  9e:	09 f4       	brne	.+2      	; 0xa2 <turn+0x10>
+  a0:	41 c0       	rjmp	.+130    	; 0x124 <turn+0x92>
+  a2:	86 e0       	ldi	r24, 0x06	; 6
+  a4:	90 e0       	ldi	r25, 0x00	; 0
+  a6:	90 93 63 00 	sts	0x0063, r25
+  aa:	80 93 62 00 	sts	0x0062, r24
+  ae:	88 e7       	ldi	r24, 0x78	; 120
+  b0:	90 e0       	ldi	r25, 0x00	; 0
+  b2:	90 93 61 00 	sts	0x0061, r25
+  b6:	80 93 60 00 	sts	0x0060, r24
+  ba:	8f e3       	ldi	r24, 0x3F	; 63
+  bc:	9c e9       	ldi	r25, 0x9C	; 156
+  be:	01 97       	sbiw	r24, 0x01	; 1
+  c0:	f1 f7       	brne	.-4      	; 0xbe <turn+0x2c>
+  c2:	00 c0       	rjmp	.+0      	; 0xc4 <turn+0x32>
+  c4:	00 00       	nop
+  c6:	40 91 62 00 	lds	r20, 0x0062
+  ca:	50 91 63 00 	lds	r21, 0x0063
+  ce:	81 e0       	ldi	r24, 0x01	; 1
+  d0:	6a e0       	ldi	r22, 0x0A	; 10
+  d2:	0e 94 e4 02 	call	0x5c8	; 0x5c8 <rf12_txpacket>
+  d6:	8f ef       	ldi	r24, 0xFF	; 255
+  d8:	96 e1       	ldi	r25, 0x16	; 22
+  da:	a1 e1       	ldi	r26, 0x11	; 17
+  dc:	81 50       	subi	r24, 0x01	; 1
+  de:	90 40       	sbci	r25, 0x00	; 0
+  e0:	a0 40       	sbci	r26, 0x00	; 0
+  e2:	e1 f7       	brne	.-8      	; 0xdc <turn+0x4a>
+  e4:	00 c0       	rjmp	.+0      	; 0xe6 <turn+0x54>
+  e6:	00 00       	nop
+  e8:	8c e3       	ldi	r24, 0x3C	; 60
+  ea:	90 e0       	ldi	r25, 0x00	; 0
+  ec:	90 93 61 00 	sts	0x0061, r25
+  f0:	80 93 60 00 	sts	0x0060, r24
+  f4:	8f ef       	ldi	r24, 0xFF	; 255
+  f6:	96 e1       	ldi	r25, 0x16	; 22
+  f8:	a1 e1       	ldi	r26, 0x11	; 17
+  fa:	81 50       	subi	r24, 0x01	; 1
+  fc:	90 40       	sbci	r25, 0x00	; 0
+  fe:	a0 40       	sbci	r26, 0x00	; 0
+ 100:	e1 f7       	brne	.-8      	; 0xfa <turn+0x68>
+ 102:	00 c0       	rjmp	.+0      	; 0x104 <turn+0x72>
+ 104:	00 00       	nop
+ 106:	84 eb       	ldi	r24, 0xB4	; 180
+ 108:	90 e0       	ldi	r25, 0x00	; 0
+ 10a:	90 93 61 00 	sts	0x0061, r25
+ 10e:	80 93 60 00 	sts	0x0060, r24
+ 112:	8f ef       	ldi	r24, 0xFF	; 255
+ 114:	96 e1       	ldi	r25, 0x16	; 22
+ 116:	a1 e1       	ldi	r26, 0x11	; 17
+ 118:	81 50       	subi	r24, 0x01	; 1
+ 11a:	90 40       	sbci	r25, 0x00	; 0
+ 11c:	a0 40       	sbci	r26, 0x00	; 0
+ 11e:	e1 f7       	brne	.-8      	; 0x118 <turn+0x86>
+ 120:	00 c0       	rjmp	.+0      	; 0x122 <turn+0x90>
+ 122:	00 00       	nop
+ 124:	08 95       	ret
+
+00000126 <poll>:
+ 126:	89 98       	cbi	0x11, 1	; 17
+ 128:	80 91 62 00 	lds	r24, 0x0062
+ 12c:	90 91 63 00 	lds	r25, 0x0063
+ 130:	83 30       	cpi	r24, 0x03	; 3
+ 132:	91 05       	cpc	r25, r1
+ 134:	41 f4       	brne	.+16     	; 0x146 <poll+0x20>
+ 136:	81 9b       	sbis	0x10, 1	; 16
+ 138:	06 c0       	rjmp	.+12     	; 0x146 <poll+0x20>
+ 13a:	0e 94 6e 02 	call	0x4dc	; 0x4dc <rf12_endasyncrx>
+ 13e:	0e 94 49 00 	call	0x92	; 0x92 <turn>
+ 142:	0e 94 57 02 	call	0x4ae	; 0x4ae <rf12_beginasyncrx>
+ 146:	80 91 62 00 	lds	r24, 0x0062
+ 14a:	90 91 63 00 	lds	r25, 0x0063
+ 14e:	82 30       	cpi	r24, 0x02	; 2
+ 150:	91 05       	cpc	r25, r1
+ 152:	59 f4       	brne	.+22     	; 0x16a <poll+0x44>
+ 154:	81 9b       	sbis	0x10, 1	; 16
+ 156:	09 c0       	rjmp	.+18     	; 0x16a <poll+0x44>
+ 158:	0e 94 6e 02 	call	0x4dc	; 0x4dc <rf12_endasyncrx>
+ 15c:	81 e0       	ldi	r24, 0x01	; 1
+ 15e:	6a e0       	ldi	r22, 0x0A	; 10
+ 160:	48 e0       	ldi	r20, 0x08	; 8
+ 162:	0e 94 e4 02 	call	0x5c8	; 0x5c8 <rf12_txpacket>
+ 166:	0e 94 57 02 	call	0x4ae	; 0x4ae <rf12_beginasyncrx>
+ 16a:	b7 99       	sbic	0x16, 7	; 22
+ 16c:	2e c0       	rjmp	.+92     	; 0x1ca <poll+0xa4>
+ 16e:	80 91 62 00 	lds	r24, 0x0062
+ 172:	90 91 63 00 	lds	r25, 0x0063
+ 176:	82 30       	cpi	r24, 0x02	; 2
+ 178:	91 05       	cpc	r25, r1
+ 17a:	39 f5       	brne	.+78     	; 0x1ca <poll+0xa4>
+ 17c:	86 e0       	ldi	r24, 0x06	; 6
+ 17e:	90 e0       	ldi	r25, 0x00	; 0
+ 180:	90 93 63 00 	sts	0x0063, r25
+ 184:	80 93 62 00 	sts	0x0062, r24
+ 188:	8f ef       	ldi	r24, 0xFF	; 255
+ 18a:	91 e1       	ldi	r25, 0x11	; 17
+ 18c:	aa e7       	ldi	r26, 0x7A	; 122
+ 18e:	81 50       	subi	r24, 0x01	; 1
+ 190:	90 40       	sbci	r25, 0x00	; 0
+ 192:	a0 40       	sbci	r26, 0x00	; 0
+ 194:	e1 f7       	brne	.-8      	; 0x18e <poll+0x68>
+ 196:	00 c0       	rjmp	.+0      	; 0x198 <poll+0x72>
+ 198:	00 00       	nop
+ 19a:	8f ef       	ldi	r24, 0xFF	; 255
+ 19c:	91 e1       	ldi	r25, 0x11	; 17
+ 19e:	aa e7       	ldi	r26, 0x7A	; 122
+ 1a0:	81 50       	subi	r24, 0x01	; 1
+ 1a2:	90 40       	sbci	r25, 0x00	; 0
+ 1a4:	a0 40       	sbci	r26, 0x00	; 0
+ 1a6:	e1 f7       	brne	.-8      	; 0x1a0 <poll+0x7a>
+ 1a8:	00 c0       	rjmp	.+0      	; 0x1aa <poll+0x84>
+ 1aa:	00 00       	nop
+ 1ac:	8f ef       	ldi	r24, 0xFF	; 255
+ 1ae:	91 e1       	ldi	r25, 0x11	; 17
+ 1b0:	aa e7       	ldi	r26, 0x7A	; 122
+ 1b2:	81 50       	subi	r24, 0x01	; 1
+ 1b4:	90 40       	sbci	r25, 0x00	; 0
+ 1b6:	a0 40       	sbci	r26, 0x00	; 0
+ 1b8:	e1 f7       	brne	.-8      	; 0x1b2 <poll+0x8c>
+ 1ba:	00 c0       	rjmp	.+0      	; 0x1bc <poll+0x96>
+ 1bc:	00 00       	nop
+ 1be:	83 e0       	ldi	r24, 0x03	; 3
+ 1c0:	90 e0       	ldi	r25, 0x00	; 0
+ 1c2:	90 93 63 00 	sts	0x0063, r25
+ 1c6:	80 93 62 00 	sts	0x0062, r24
+ 1ca:	08 95       	ret
+
+000001cc <recive>:
+ 1cc:	cf 93       	push	r28
+ 1ce:	0e 94 57 02 	call	0x4ae	; 0x4ae <rf12_beginasyncrx>
+ 1d2:	02 c0       	rjmp	.+4      	; 0x1d8 <recive+0xc>
+ 1d4:	0e 94 93 00 	call	0x126	; 0x126 <poll>
+ 1d8:	0e 94 64 02 	call	0x4c8	; 0x4c8 <rf12_hasdata>
+ 1dc:	88 23       	and	r24, r24
+ 1de:	d1 f7       	brne	.-12     	; 0x1d4 <recive+0x8>
+ 1e0:	0e 94 69 02 	call	0x4d2	; 0x4d2 <rf12_rxbyte>
+ 1e4:	88 23       	and	r24, r24
+ 1e6:	41 f0       	breq	.+16     	; 0x1f8 <recive+0x2c>
+ 1e8:	8a 30       	cpi	r24, 0x0A	; 10
+ 1ea:	31 f0       	breq	.+12     	; 0x1f8 <recive+0x2c>
+ 1ec:	80 3f       	cpi	r24, 0xF0	; 240
+ 1ee:	09 f0       	breq	.+2      	; 0x1f2 <recive+0x26>
+ 1f0:	45 c0       	rjmp	.+138    	; 0x27c <recive+0xb0>
+ 1f2:	02 c0       	rjmp	.+4      	; 0x1f8 <recive+0x2c>
+ 1f4:	0e 94 93 00 	call	0x126	; 0x126 <poll>
+ 1f8:	0e 94 64 02 	call	0x4c8	; 0x4c8 <rf12_hasdata>
+ 1fc:	88 23       	and	r24, r24
+ 1fe:	d1 f7       	brne	.-12     	; 0x1f4 <recive+0x28>
+ 200:	0e 94 69 02 	call	0x4d2	; 0x4d2 <rf12_rxbyte>
+ 204:	c8 2f       	mov	r28, r24
+ 206:	02 c0       	rjmp	.+4      	; 0x20c <recive+0x40>
+ 208:	0e 94 93 00 	call	0x126	; 0x126 <poll>
+ 20c:	0e 94 64 02 	call	0x4c8	; 0x4c8 <rf12_hasdata>
+ 210:	88 23       	and	r24, r24
+ 212:	d1 f7       	brne	.-12     	; 0x208 <recive+0x3c>
+ 214:	c1 30       	cpi	r28, 0x01	; 1
+ 216:	91 f5       	brne	.+100    	; 0x27c <recive+0xb0>
+ 218:	0e 94 69 02 	call	0x4d2	; 0x4d2 <rf12_rxbyte>
+ 21c:	84 30       	cpi	r24, 0x04	; 4
+ 21e:	51 f0       	breq	.+20     	; 0x234 <recive+0x68>
+ 220:	85 30       	cpi	r24, 0x05	; 5
+ 222:	18 f4       	brcc	.+6      	; 0x22a <recive+0x5e>
+ 224:	81 30       	cpi	r24, 0x01	; 1
+ 226:	b9 f4       	brne	.+46     	; 0x256 <recive+0x8a>
+ 228:	19 c0       	rjmp	.+50     	; 0x25c <recive+0x90>
+ 22a:	85 30       	cpi	r24, 0x05	; 5
+ 22c:	31 f0       	breq	.+12     	; 0x23a <recive+0x6e>
+ 22e:	87 30       	cpi	r24, 0x07	; 7
+ 230:	91 f4       	brne	.+36     	; 0x256 <recive+0x8a>
+ 232:	0a c0       	rjmp	.+20     	; 0x248 <recive+0x7c>
+ 234:	82 e0       	ldi	r24, 0x02	; 2
+ 236:	90 e0       	ldi	r25, 0x00	; 0
+ 238:	02 c0       	rjmp	.+4      	; 0x23e <recive+0x72>
+ 23a:	83 e0       	ldi	r24, 0x03	; 3
+ 23c:	90 e0       	ldi	r25, 0x00	; 0
+ 23e:	90 93 63 00 	sts	0x0063, r25
+ 242:	80 93 62 00 	sts	0x0062, r24
+ 246:	0a c0       	rjmp	.+20     	; 0x25c <recive+0x90>
+ 248:	0e 94 6e 02 	call	0x4dc	; 0x4dc <rf12_endasyncrx>
+ 24c:	0e 94 49 00 	call	0x92	; 0x92 <turn>
+ 250:	0e 94 57 02 	call	0x4ae	; 0x4ae <rf12_beginasyncrx>
+ 254:	13 c0       	rjmp	.+38     	; 0x27c <recive+0xb0>
+ 256:	0e 94 6e 02 	call	0x4dc	; 0x4dc <rf12_endasyncrx>
+ 25a:	10 c0       	rjmp	.+32     	; 0x27c <recive+0xb0>
+ 25c:	0e 94 6e 02 	call	0x4dc	; 0x4dc <rf12_endasyncrx>
+ 260:	8f e3       	ldi	r24, 0x3F	; 63
+ 262:	9c e9       	ldi	r25, 0x9C	; 156
+ 264:	01 97       	sbiw	r24, 0x01	; 1
+ 266:	f1 f7       	brne	.-4      	; 0x264 <recive+0x98>
+ 268:	00 c0       	rjmp	.+0      	; 0x26a <recive+0x9e>
+ 26a:	00 00       	nop
+ 26c:	40 91 62 00 	lds	r20, 0x0062
+ 270:	50 91 63 00 	lds	r21, 0x0063
+ 274:	81 e0       	ldi	r24, 0x01	; 1
+ 276:	6a e0       	ldi	r22, 0x0A	; 10
+ 278:	0e 94 e4 02 	call	0x5c8	; 0x5c8 <rf12_txpacket>
+ 27c:	cf 91       	pop	r28
+ 27e:	08 95       	ret
+
+00000280 <init_timer>:
+ 280:	85 e0       	ldi	r24, 0x05	; 5
+ 282:	83 bf       	out	0x33, r24	; 51
+ 284:	88 e5       	ldi	r24, 0x58	; 88
+ 286:	82 bf       	out	0x32, r24	; 50
+ 288:	1c be       	out	0x3c, r1	; 60
+ 28a:	81 e0       	ldi	r24, 0x01	; 1
+ 28c:	89 bf       	out	0x39, r24	; 57
+ 28e:	08 95       	ret
+
+00000290 <__vector_9>:
+ 290:	1f 92       	push	r1
+ 292:	0f 92       	push	r0
+ 294:	0f b6       	in	r0, 0x3f	; 63
+ 296:	0f 92       	push	r0
+ 298:	11 24       	eor	r1, r1
+ 29a:	2f 93       	push	r18
+ 29c:	3f 93       	push	r19
+ 29e:	8f 93       	push	r24
+ 2a0:	9f 93       	push	r25
+ 2a2:	88 e5       	ldi	r24, 0x58	; 88
+ 2a4:	82 bf       	out	0x32, r24	; 50
+ 2a6:	80 91 62 00 	lds	r24, 0x0062
+ 2aa:	90 91 63 00 	lds	r25, 0x0063
+ 2ae:	82 30       	cpi	r24, 0x02	; 2
+ 2b0:	91 05       	cpc	r25, r1
+ 2b2:	41 f4       	brne	.+16     	; 0x2c4 <__vector_9+0x34>
+ 2b4:	80 91 64 00 	lds	r24, 0x0064
+ 2b8:	90 91 65 00 	lds	r25, 0x0065
+ 2bc:	83 33       	cpi	r24, 0x33	; 51
+ 2be:	91 05       	cpc	r25, r1
+ 2c0:	34 f1       	brlt	.+76     	; 0x30e <__vector_9+0x7e>
+ 2c2:	1d c0       	rjmp	.+58     	; 0x2fe <__vector_9+0x6e>
+ 2c4:	80 91 62 00 	lds	r24, 0x0062
+ 2c8:	90 91 63 00 	lds	r25, 0x0063
+ 2cc:	83 30       	cpi	r24, 0x03	; 3
+ 2ce:	91 05       	cpc	r25, r1
+ 2d0:	41 f4       	brne	.+16     	; 0x2e2 <__vector_9+0x52>
+ 2d2:	80 91 64 00 	lds	r24, 0x0064
+ 2d6:	90 91 65 00 	lds	r25, 0x0065
+ 2da:	86 30       	cpi	r24, 0x06	; 6
+ 2dc:	91 05       	cpc	r25, r1
+ 2de:	bc f0       	brlt	.+46     	; 0x30e <__vector_9+0x7e>
+ 2e0:	0e c0       	rjmp	.+28     	; 0x2fe <__vector_9+0x6e>
+ 2e2:	80 91 62 00 	lds	r24, 0x0062
+ 2e6:	90 91 63 00 	lds	r25, 0x0063
+ 2ea:	86 30       	cpi	r24, 0x06	; 6
+ 2ec:	91 05       	cpc	r25, r1
+ 2ee:	79 f4       	brne	.+30     	; 0x30e <__vector_9+0x7e>
+ 2f0:	80 91 64 00 	lds	r24, 0x0064
+ 2f4:	90 91 65 00 	lds	r25, 0x0065
+ 2f8:	82 30       	cpi	r24, 0x02	; 2
+ 2fa:	91 05       	cpc	r25, r1
+ 2fc:	44 f0       	brlt	.+16     	; 0x30e <__vector_9+0x7e>
+ 2fe:	88 b3       	in	r24, 0x18	; 24
+ 300:	91 e0       	ldi	r25, 0x01	; 1
+ 302:	89 27       	eor	r24, r25
+ 304:	88 bb       	out	0x18, r24	; 24
+ 306:	10 92 65 00 	sts	0x0065, r1
+ 30a:	10 92 64 00 	sts	0x0064, r1
+ 30e:	80 91 64 00 	lds	r24, 0x0064
+ 312:	90 91 65 00 	lds	r25, 0x0065
+ 316:	01 96       	adiw	r24, 0x01	; 1
+ 318:	90 93 65 00 	sts	0x0065, r25
+ 31c:	80 93 64 00 	sts	0x0064, r24
+ 320:	b9 9a       	sbi	0x17, 1	; 23
+ 322:	c1 9a       	sbi	0x18, 1	; 24
+ 324:	8f ea       	ldi	r24, 0xAF	; 175
+ 326:	94 e0       	ldi	r25, 0x04	; 4
+ 328:	01 97       	sbiw	r24, 0x01	; 1
+ 32a:	f1 f7       	brne	.-4      	; 0x328 <__vector_9+0x98>
+ 32c:	00 c0       	rjmp	.+0      	; 0x32e <__vector_9+0x9e>
+ 32e:	00 00       	nop
+ 330:	80 e0       	ldi	r24, 0x00	; 0
+ 332:	90 e0       	ldi	r25, 0x00	; 0
+ 334:	05 c0       	rjmp	.+10     	; 0x340 <__vector_9+0xb0>
+ 336:	25 e1       	ldi	r18, 0x15	; 21
+ 338:	2a 95       	dec	r18
+ 33a:	f1 f7       	brne	.-4      	; 0x338 <__vector_9+0xa8>
+ 33c:	00 00       	nop
+ 33e:	01 96       	adiw	r24, 0x01	; 1
+ 340:	20 91 60 00 	lds	r18, 0x0060
+ 344:	30 91 61 00 	lds	r19, 0x0061
+ 348:	82 17       	cp	r24, r18
+ 34a:	93 07       	cpc	r25, r19
+ 34c:	a4 f3       	brlt	.-24     	; 0x336 <__vector_9+0xa6>
+ 34e:	c1 98       	cbi	0x18, 1	; 24
+ 350:	9f 91       	pop	r25
+ 352:	8f 91       	pop	r24
+ 354:	3f 91       	pop	r19
+ 356:	2f 91       	pop	r18
+ 358:	0f 90       	pop	r0
+ 35a:	0f be       	out	0x3f, r0	; 63
+ 35c:	0f 90       	pop	r0
+ 35e:	1f 90       	pop	r1
+ 360:	18 95       	reti
+
+00000362 <rf12_trans>:
+ 362:	94 98       	cbi	0x12, 4	; 18
+ 364:	40 e1       	ldi	r20, 0x10	; 16
+ 366:	20 e0       	ldi	r18, 0x00	; 0
+ 368:	30 e0       	ldi	r19, 0x00	; 0
+ 36a:	97 ff       	sbrs	r25, 7
+ 36c:	02 c0       	rjmp	.+4      	; 0x372 <rf12_trans+0x10>
+ 36e:	96 9a       	sbi	0x12, 6	; 18
+ 370:	01 c0       	rjmp	.+2      	; 0x374 <rf12_trans+0x12>
+ 372:	96 98       	cbi	0x12, 6	; 18
+ 374:	22 0f       	add	r18, r18
+ 376:	33 1f       	adc	r19, r19
+ 378:	83 99       	sbic	0x10, 3	; 16
+ 37a:	21 60       	ori	r18, 0x01	; 1
+ 37c:	95 9a       	sbi	0x12, 5	; 18
+ 37e:	88 0f       	add	r24, r24
+ 380:	99 1f       	adc	r25, r25
+ 382:	00 c0       	rjmp	.+0      	; 0x384 <rf12_trans+0x22>
+ 384:	00 00       	nop
+ 386:	95 98       	cbi	0x12, 5	; 18
+ 388:	41 50       	subi	r20, 0x01	; 1
+ 38a:	79 f7       	brne	.-34     	; 0x36a <rf12_trans+0x8>
+ 38c:	94 9a       	sbi	0x12, 4	; 18
+ 38e:	c9 01       	movw	r24, r18
+ 390:	08 95       	ret
+
+00000392 <rf12_init>:
+ 392:	81 b3       	in	r24, 0x11	; 17
+ 394:	80 67       	ori	r24, 0x70	; 112
+ 396:	81 bb       	out	0x11, r24	; 17
+ 398:	94 9a       	sbi	0x12, 4	; 18
+ 39a:	8f ef       	ldi	r24, 0xFF	; 255
+ 39c:	90 e7       	ldi	r25, 0x70	; 112
+ 39e:	a2 e0       	ldi	r26, 0x02	; 2
+ 3a0:	81 50       	subi	r24, 0x01	; 1
+ 3a2:	90 40       	sbci	r25, 0x00	; 0
+ 3a4:	a0 40       	sbci	r26, 0x00	; 0
+ 3a6:	e1 f7       	brne	.-8      	; 0x3a0 <rf12_init+0xe>
+ 3a8:	00 c0       	rjmp	.+0      	; 0x3aa <rf12_init+0x18>
+ 3aa:	00 00       	nop
+ 3ac:	80 ee       	ldi	r24, 0xE0	; 224
+ 3ae:	90 ec       	ldi	r25, 0xC0	; 192
+ 3b0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3b4:	87 ed       	ldi	r24, 0xD7	; 215
+ 3b6:	90 e8       	ldi	r25, 0x80	; 128
+ 3b8:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3bc:	8b ea       	ldi	r24, 0xAB	; 171
+ 3be:	92 ec       	ldi	r25, 0xC2	; 194
+ 3c0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3c4:	81 e8       	ldi	r24, 0x81	; 129
+ 3c6:	9a ec       	ldi	r25, 0xCA	; 202
+ 3c8:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3cc:	80 e0       	ldi	r24, 0x00	; 0
+ 3ce:	90 ee       	ldi	r25, 0xE0	; 224
+ 3d0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3d4:	80 e0       	ldi	r24, 0x00	; 0
+ 3d6:	98 ec       	ldi	r25, 0xC8	; 200
+ 3d8:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3dc:	87 ef       	ldi	r24, 0xF7	; 247
+ 3de:	94 ec       	ldi	r25, 0xC4	; 196
+ 3e0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 3e4:	08 95       	ret
+
+000003e6 <rf12_setbandwidth>:
+ 3e6:	28 2f       	mov	r18, r24
+ 3e8:	30 e0       	ldi	r19, 0x00	; 0
+ 3ea:	75 e0       	ldi	r23, 0x05	; 5
+ 3ec:	22 0f       	add	r18, r18
+ 3ee:	33 1f       	adc	r19, r19
+ 3f0:	7a 95       	dec	r23
+ 3f2:	e1 f7       	brne	.-8      	; 0x3ec <rf12_setbandwidth+0x6>
+ 3f4:	30 70       	andi	r19, 0x00	; 0
+ 3f6:	50 e0       	ldi	r21, 0x00	; 0
+ 3f8:	47 70       	andi	r20, 0x07	; 7
+ 3fa:	50 70       	andi	r21, 0x00	; 0
+ 3fc:	24 2b       	or	r18, r20
+ 3fe:	35 2b       	or	r19, r21
+ 400:	34 69       	ori	r19, 0x94	; 148
+ 402:	86 2f       	mov	r24, r22
+ 404:	90 e0       	ldi	r25, 0x00	; 0
+ 406:	83 70       	andi	r24, 0x03	; 3
+ 408:	90 70       	andi	r25, 0x00	; 0
+ 40a:	e3 e0       	ldi	r30, 0x03	; 3
+ 40c:	88 0f       	add	r24, r24
+ 40e:	99 1f       	adc	r25, r25
+ 410:	ea 95       	dec	r30
+ 412:	e1 f7       	brne	.-8      	; 0x40c <rf12_setbandwidth+0x26>
+ 414:	82 2b       	or	r24, r18
+ 416:	93 2b       	or	r25, r19
+ 418:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 41c:	08 95       	ret
+
+0000041e <rf12_setfreq>:
+ 41e:	80 36       	cpi	r24, 0x60	; 96
+ 420:	91 05       	cpc	r25, r1
+ 422:	38 f0       	brcs	.+14     	; 0x432 <rf12_setfreq+0x14>
+ 424:	2f e0       	ldi	r18, 0x0F	; 15
+ 426:	80 34       	cpi	r24, 0x40	; 64
+ 428:	92 07       	cpc	r25, r18
+ 42a:	28 f0       	brcs	.+10     	; 0x436 <rf12_setfreq+0x18>
+ 42c:	8f e3       	ldi	r24, 0x3F	; 63
+ 42e:	9f e0       	ldi	r25, 0x0F	; 15
+ 430:	02 c0       	rjmp	.+4      	; 0x436 <rf12_setfreq+0x18>
+ 432:	80 e6       	ldi	r24, 0x60	; 96
+ 434:	90 e0       	ldi	r25, 0x00	; 0
+ 436:	90 6a       	ori	r25, 0xA0	; 160
+ 438:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 43c:	08 95       	ret
+
+0000043e <rf12_setbaud>:
+ 43e:	22 e0       	ldi	r18, 0x02	; 2
+ 440:	87 39       	cpi	r24, 0x97	; 151
+ 442:	92 07       	cpc	r25, r18
+ 444:	f8 f0       	brcs	.+62     	; 0x484 <__stack+0x25>
+ 446:	9c 01       	movw	r18, r24
+ 448:	40 e0       	ldi	r20, 0x00	; 0
+ 44a:	50 e0       	ldi	r21, 0x00	; 0
+ 44c:	65 e1       	ldi	r22, 0x15	; 21
+ 44e:	88 31       	cpi	r24, 0x18	; 24
+ 450:	96 07       	cpc	r25, r22
+ 452:	68 f4       	brcc	.+26     	; 0x46e <__stack+0xf>
+ 454:	60 e6       	ldi	r22, 0x60	; 96
+ 456:	78 ea       	ldi	r23, 0xA8	; 168
+ 458:	80 e0       	ldi	r24, 0x00	; 0
+ 45a:	90 e0       	ldi	r25, 0x00	; 0
+ 45c:	0e 94 81 03 	call	0x702	; 0x702 <__divmodsi4>
+ 460:	c9 01       	movw	r24, r18
+ 462:	01 97       	sbiw	r24, 0x01	; 1
+ 464:	80 68       	ori	r24, 0x80	; 128
+ 466:	96 6c       	ori	r25, 0xC6	; 198
+ 468:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 46c:	08 95       	ret
+ 46e:	6c ef       	ldi	r22, 0xFC	; 252
+ 470:	72 e4       	ldi	r23, 0x42	; 66
+ 472:	85 e0       	ldi	r24, 0x05	; 5
+ 474:	90 e0       	ldi	r25, 0x00	; 0
+ 476:	0e 94 5f 03 	call	0x6be	; 0x6be <__udivmodsi4>
+ 47a:	c9 01       	movw	r24, r18
+ 47c:	01 97       	sbiw	r24, 0x01	; 1
+ 47e:	96 6c       	ori	r25, 0xC6	; 198
+ 480:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 484:	08 95       	ret
+
+00000486 <rf12_setpower>:
+ 486:	90 e0       	ldi	r25, 0x00	; 0
+ 488:	87 70       	andi	r24, 0x07	; 7
+ 48a:	90 70       	andi	r25, 0x00	; 0
+ 48c:	98 69       	ori	r25, 0x98	; 152
+ 48e:	70 e0       	ldi	r23, 0x00	; 0
+ 490:	f4 e0       	ldi	r31, 0x04	; 4
+ 492:	66 0f       	add	r22, r22
+ 494:	77 1f       	adc	r23, r23
+ 496:	fa 95       	dec	r31
+ 498:	e1 f7       	brne	.-8      	; 0x492 <rf12_setpower+0xc>
+ 49a:	70 70       	andi	r23, 0x00	; 0
+ 49c:	86 2b       	or	r24, r22
+ 49e:	97 2b       	or	r25, r23
+ 4a0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4a4:	08 95       	ret
+
+000004a6 <rf12_ready>:
+ 4a6:	94 98       	cbi	0x12, 4	; 18
+ 4a8:	83 9b       	sbis	0x10, 3	; 16
+ 4aa:	fe cf       	rjmp	.-4      	; 0x4a8 <rf12_ready+0x2>
+ 4ac:	08 95       	ret
+
+000004ae <rf12_beginasyncrx>:
+ 4ae:	88 ec       	ldi	r24, 0xC8	; 200
+ 4b0:	92 e8       	ldi	r25, 0x82	; 130
+ 4b2:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4b6:	81 e8       	ldi	r24, 0x81	; 129
+ 4b8:	9a ec       	ldi	r25, 0xCA	; 202
+ 4ba:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4be:	83 e8       	ldi	r24, 0x83	; 131
+ 4c0:	9a ec       	ldi	r25, 0xCA	; 202
+ 4c2:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4c6:	08 95       	ret
+
+000004c8 <rf12_hasdata>:
+ 4c8:	94 98       	cbi	0x12, 4	; 18
+ 4ca:	81 e0       	ldi	r24, 0x01	; 1
+ 4cc:	83 99       	sbic	0x10, 3	; 16
+ 4ce:	80 e0       	ldi	r24, 0x00	; 0
+ 4d0:	08 95       	ret
+
+000004d2 <rf12_rxbyte>:
+ 4d2:	80 e0       	ldi	r24, 0x00	; 0
+ 4d4:	90 eb       	ldi	r25, 0xB0	; 176
+ 4d6:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4da:	08 95       	ret
+
+000004dc <rf12_endasyncrx>:
+ 4dc:	88 e0       	ldi	r24, 0x08	; 8
+ 4de:	92 e8       	ldi	r25, 0x82	; 130
+ 4e0:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4e4:	08 95       	ret
+
+000004e6 <rf12_txdata>:
+ 4e6:	ff 92       	push	r15
+ 4e8:	0f 93       	push	r16
+ 4ea:	1f 93       	push	r17
+ 4ec:	cf 93       	push	r28
+ 4ee:	df 93       	push	r29
+ 4f0:	18 2f       	mov	r17, r24
+ 4f2:	09 2f       	mov	r16, r25
+ 4f4:	f6 2e       	mov	r15, r22
+ 4f6:	88 e3       	ldi	r24, 0x38	; 56
+ 4f8:	92 e8       	ldi	r25, 0x82	; 130
+ 4fa:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 4fe:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 502:	8a ea       	ldi	r24, 0xAA	; 170
+ 504:	98 eb       	ldi	r25, 0xB8	; 184
+ 506:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 50a:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 50e:	8a ea       	ldi	r24, 0xAA	; 170
+ 510:	98 eb       	ldi	r25, 0xB8	; 184
+ 512:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 516:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 51a:	8a ea       	ldi	r24, 0xAA	; 170
+ 51c:	98 eb       	ldi	r25, 0xB8	; 184
+ 51e:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 522:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 526:	8d e2       	ldi	r24, 0x2D	; 45
+ 528:	98 eb       	ldi	r25, 0xB8	; 184
+ 52a:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 52e:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 532:	84 ed       	ldi	r24, 0xD4	; 212
+ 534:	98 eb       	ldi	r25, 0xB8	; 184
+ 536:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 53a:	c1 2f       	mov	r28, r17
+ 53c:	d0 2f       	mov	r29, r16
+ 53e:	08 c0       	rjmp	.+16     	; 0x550 <rf12_txdata+0x6a>
+ 540:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 544:	29 91       	ld	r18, Y+
+ 546:	30 e0       	ldi	r19, 0x00	; 0
+ 548:	c9 01       	movw	r24, r18
+ 54a:	98 6b       	ori	r25, 0xB8	; 184
+ 54c:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 550:	8c 2f       	mov	r24, r28
+ 552:	81 1b       	sub	r24, r17
+ 554:	8f 15       	cp	r24, r15
+ 556:	a0 f3       	brcs	.-24     	; 0x540 <rf12_txdata+0x5a>
+ 558:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 55c:	88 e0       	ldi	r24, 0x08	; 8
+ 55e:	92 e8       	ldi	r25, 0x82	; 130
+ 560:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 564:	df 91       	pop	r29
+ 566:	cf 91       	pop	r28
+ 568:	1f 91       	pop	r17
+ 56a:	0f 91       	pop	r16
+ 56c:	ff 90       	pop	r15
+ 56e:	08 95       	ret
+
+00000570 <rf12_rxdata>:
+ 570:	ff 92       	push	r15
+ 572:	0f 93       	push	r16
+ 574:	1f 93       	push	r17
+ 576:	cf 93       	push	r28
+ 578:	df 93       	push	r29
+ 57a:	18 2f       	mov	r17, r24
+ 57c:	09 2f       	mov	r16, r25
+ 57e:	f6 2e       	mov	r15, r22
+ 580:	88 ec       	ldi	r24, 0xC8	; 200
+ 582:	92 e8       	ldi	r25, 0x82	; 130
+ 584:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 588:	81 e8       	ldi	r24, 0x81	; 129
+ 58a:	9a ec       	ldi	r25, 0xCA	; 202
+ 58c:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 590:	83 e8       	ldi	r24, 0x83	; 131
+ 592:	9a ec       	ldi	r25, 0xCA	; 202
+ 594:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 598:	c1 2f       	mov	r28, r17
+ 59a:	d0 2f       	mov	r29, r16
+ 59c:	07 c0       	rjmp	.+14     	; 0x5ac <rf12_rxdata+0x3c>
+ 59e:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 5a2:	80 e0       	ldi	r24, 0x00	; 0
+ 5a4:	90 eb       	ldi	r25, 0xB0	; 176
+ 5a6:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 5aa:	89 93       	st	Y+, r24
+ 5ac:	8c 2f       	mov	r24, r28
+ 5ae:	81 1b       	sub	r24, r17
+ 5b0:	8f 15       	cp	r24, r15
+ 5b2:	a8 f3       	brcs	.-22     	; 0x59e <rf12_rxdata+0x2e>
+ 5b4:	88 e0       	ldi	r24, 0x08	; 8
+ 5b6:	92 e8       	ldi	r25, 0x82	; 130
+ 5b8:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 5bc:	df 91       	pop	r29
+ 5be:	cf 91       	pop	r28
+ 5c0:	1f 91       	pop	r17
+ 5c2:	0f 91       	pop	r16
+ 5c4:	ff 90       	pop	r15
+ 5c6:	08 95       	ret
+
+000005c8 <rf12_txpacket>:
+ 5c8:	1f 93       	push	r17
+ 5ca:	cf 93       	push	r28
+ 5cc:	df 93       	push	r29
+ 5ce:	00 d0       	rcall	.+0      	; 0x5d0 <rf12_txpacket+0x8>
+ 5d0:	cd b7       	in	r28, 0x3d	; 61
+ 5d2:	de b7       	in	r29, 0x3e	; 62
+ 5d4:	18 2f       	mov	r17, r24
+ 5d6:	88 e3       	ldi	r24, 0x38	; 56
+ 5d8:	92 e8       	ldi	r25, 0x82	; 130
+ 5da:	4a 83       	std	Y+2, r20	; 0x02
+ 5dc:	69 83       	std	Y+1, r22	; 0x01
+ 5de:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 5e2:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 5e6:	8a ea       	ldi	r24, 0xAA	; 170
+ 5e8:	98 eb       	ldi	r25, 0xB8	; 184
+ 5ea:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 5ee:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 5f2:	8a ea       	ldi	r24, 0xAA	; 170
+ 5f4:	98 eb       	ldi	r25, 0xB8	; 184
+ 5f6:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 5fa:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 5fe:	8a ea       	ldi	r24, 0xAA	; 170
+ 600:	98 eb       	ldi	r25, 0xB8	; 184
+ 602:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 606:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 60a:	8d e2       	ldi	r24, 0x2D	; 45
+ 60c:	98 eb       	ldi	r25, 0xB8	; 184
+ 60e:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 612:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 616:	84 ed       	ldi	r24, 0xD4	; 212
+ 618:	98 eb       	ldi	r25, 0xB8	; 184
+ 61a:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 61e:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 622:	81 2f       	mov	r24, r17
+ 624:	90 e0       	ldi	r25, 0x00	; 0
+ 626:	98 6b       	ori	r25, 0xB8	; 184
+ 628:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 62c:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 630:	69 81       	ldd	r22, Y+1	; 0x01
+ 632:	86 2f       	mov	r24, r22
+ 634:	90 e0       	ldi	r25, 0x00	; 0
+ 636:	98 6b       	ori	r25, 0xB8	; 184
+ 638:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 63c:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 640:	4a 81       	ldd	r20, Y+2	; 0x02
+ 642:	84 2f       	mov	r24, r20
+ 644:	90 e0       	ldi	r25, 0x00	; 0
+ 646:	98 6b       	ori	r25, 0xB8	; 184
+ 648:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 64c:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 650:	80 e0       	ldi	r24, 0x00	; 0
+ 652:	98 eb       	ldi	r25, 0xB8	; 184
+ 654:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 658:	0e 94 53 02 	call	0x4a6	; 0x4a6 <rf12_ready>
+ 65c:	88 e0       	ldi	r24, 0x08	; 8
+ 65e:	92 e8       	ldi	r25, 0x82	; 130
+ 660:	0e 94 b1 01 	call	0x362	; 0x362 <rf12_trans>
+ 664:	8f ef       	ldi	r24, 0xFF	; 255
+ 666:	90 e7       	ldi	r25, 0x70	; 112
+ 668:	a2 e0       	ldi	r26, 0x02	; 2
+ 66a:	81 50       	subi	r24, 0x01	; 1
+ 66c:	90 40       	sbci	r25, 0x00	; 0
+ 66e:	a0 40       	sbci	r26, 0x00	; 0
+ 670:	e1 f7       	brne	.-8      	; 0x66a <rf12_txpacket+0xa2>
+ 672:	00 c0       	rjmp	.+0      	; 0x674 <rf12_txpacket+0xac>
+ 674:	00 00       	nop
+ 676:	0f 90       	pop	r0
+ 678:	0f 90       	pop	r0
+ 67a:	df 91       	pop	r29
+ 67c:	cf 91       	pop	r28
+ 67e:	1f 91       	pop	r17
+ 680:	08 95       	ret
+
+00000682 <main>:
+ 682:	0e 94 c9 01 	call	0x392	; 0x392 <rf12_init>
+ 686:	80 e2       	ldi	r24, 0x20	; 32
+ 688:	96 e0       	ldi	r25, 0x06	; 6
+ 68a:	0e 94 0f 02 	call	0x41e	; 0x41e <rf12_setfreq>
+ 68e:	81 e0       	ldi	r24, 0x01	; 1
+ 690:	60 e0       	ldi	r22, 0x00	; 0
+ 692:	47 e0       	ldi	r20, 0x07	; 7
+ 694:	0e 94 f3 01 	call	0x3e6	; 0x3e6 <rf12_setbandwidth>
+ 698:	80 e8       	ldi	r24, 0x80	; 128
+ 69a:	95 e2       	ldi	r25, 0x25	; 37
+ 69c:	0e 94 1f 02 	call	0x43e	; 0x43e <rf12_setbaud>
+ 6a0:	80 e0       	ldi	r24, 0x00	; 0
+ 6a2:	66 e0       	ldi	r22, 0x06	; 6
+ 6a4:	0e 94 43 02 	call	0x486	; 0x486 <rf12_setpower>
+ 6a8:	0e 94 40 01 	call	0x280	; 0x280 <init_timer>
+ 6ac:	b8 9a       	sbi	0x17, 0	; 23
+ 6ae:	bf 98       	cbi	0x17, 7	; 23
+ 6b0:	c7 9a       	sbi	0x18, 7	; 24
+ 6b2:	bd 9a       	sbi	0x17, 5	; 23
+ 6b4:	c5 98       	cbi	0x18, 5	; 24
+ 6b6:	78 94       	sei
+ 6b8:	0e 94 e6 00 	call	0x1cc	; 0x1cc <recive>
+ 6bc:	fd cf       	rjmp	.-6      	; 0x6b8 <main+0x36>
+
+000006be <__udivmodsi4>:
+ 6be:	a1 e2       	ldi	r26, 0x21	; 33
+ 6c0:	1a 2e       	mov	r1, r26
+ 6c2:	aa 1b       	sub	r26, r26
+ 6c4:	bb 1b       	sub	r27, r27
+ 6c6:	fd 01       	movw	r30, r26
+ 6c8:	0d c0       	rjmp	.+26     	; 0x6e4 <__udivmodsi4_ep>
+
+000006ca <__udivmodsi4_loop>:
+ 6ca:	aa 1f       	adc	r26, r26
+ 6cc:	bb 1f       	adc	r27, r27
+ 6ce:	ee 1f       	adc	r30, r30
+ 6d0:	ff 1f       	adc	r31, r31
+ 6d2:	a2 17       	cp	r26, r18
+ 6d4:	b3 07       	cpc	r27, r19
+ 6d6:	e4 07       	cpc	r30, r20
+ 6d8:	f5 07       	cpc	r31, r21
+ 6da:	20 f0       	brcs	.+8      	; 0x6e4 <__udivmodsi4_ep>
+ 6dc:	a2 1b       	sub	r26, r18
+ 6de:	b3 0b       	sbc	r27, r19
+ 6e0:	e4 0b       	sbc	r30, r20
+ 6e2:	f5 0b       	sbc	r31, r21
+
+000006e4 <__udivmodsi4_ep>:
+ 6e4:	66 1f       	adc	r22, r22
+ 6e6:	77 1f       	adc	r23, r23
+ 6e8:	88 1f       	adc	r24, r24
+ 6ea:	99 1f       	adc	r25, r25
+ 6ec:	1a 94       	dec	r1
+ 6ee:	69 f7       	brne	.-38     	; 0x6ca <__udivmodsi4_loop>
+ 6f0:	60 95       	com	r22
+ 6f2:	70 95       	com	r23
+ 6f4:	80 95       	com	r24
+ 6f6:	90 95       	com	r25
+ 6f8:	9b 01       	movw	r18, r22
+ 6fa:	ac 01       	movw	r20, r24
+ 6fc:	bd 01       	movw	r22, r26
+ 6fe:	cf 01       	movw	r24, r30
+ 700:	08 95       	ret
+
+00000702 <__divmodsi4>:
+ 702:	97 fb       	bst	r25, 7
+ 704:	09 2e       	mov	r0, r25
+ 706:	05 26       	eor	r0, r21
+ 708:	0e d0       	rcall	.+28     	; 0x726 <__divmodsi4_neg1>
+ 70a:	57 fd       	sbrc	r21, 7
+ 70c:	04 d0       	rcall	.+8      	; 0x716 <__divmodsi4_neg2>
+ 70e:	d7 df       	rcall	.-82     	; 0x6be <__udivmodsi4>
+ 710:	0a d0       	rcall	.+20     	; 0x726 <__divmodsi4_neg1>
+ 712:	00 1c       	adc	r0, r0
+ 714:	38 f4       	brcc	.+14     	; 0x724 <__divmodsi4_exit>
+
+00000716 <__divmodsi4_neg2>:
+ 716:	50 95       	com	r21
+ 718:	40 95       	com	r20
+ 71a:	30 95       	com	r19
+ 71c:	21 95       	neg	r18
+ 71e:	3f 4f       	sbci	r19, 0xFF	; 255
+ 720:	4f 4f       	sbci	r20, 0xFF	; 255
+ 722:	5f 4f       	sbci	r21, 0xFF	; 255
+
+00000724 <__divmodsi4_exit>:
+ 724:	08 95       	ret
+
+00000726 <__divmodsi4_neg1>:
+ 726:	f6 f7       	brtc	.-4      	; 0x724 <__divmodsi4_exit>
+ 728:	90 95       	com	r25
+ 72a:	80 95       	com	r24
+ 72c:	70 95       	com	r23
+ 72e:	61 95       	neg	r22
+ 730:	7f 4f       	sbci	r23, 0xFF	; 255
+ 732:	8f 4f       	sbci	r24, 0xFF	; 255
+ 734:	9f 4f       	sbci	r25, 0xFF	; 255
+ 736:	08 95       	ret
+
+00000738 <_exit>:
+ 738:	f8 94       	cli
+
+0000073a <__stop_program>:
+ 73a:	ff cf       	rjmp	.-2      	; 0x73a <__stop_program>
diff --git a/V5B/Reciver/Reciver/Release/Reciver.map b/V5B/Reciver/Reciver/Release/Reciver.map
new file mode 100644
index 0000000..1b35f51
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Reciver.map
@@ -0,0 +1,417 @@
+Archive member included because of file (symbol)
+
+e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+                              rf12.o (__udivmodsi4)
+e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+                              rf12.o (__divmodsi4)
+e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+                              e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o (exit)
+e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+                              Reciver.o (__do_copy_data)
+e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                              Reciver.o (__do_clear_bss)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+text             0x00000000         0x00020000         xr
+data             0x00800060         0x0000ffa0         rw !x
+eeprom           0x00810000         0x00010000         rw !x
+fuse             0x00820000         0x00000400         rw !x
+lock             0x00830000         0x00000400         rw !x
+signature        0x00840000         0x00000400         rw !x
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+LOAD Reciver.o
+LOAD rf12.o
+START GROUP
+LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5\libm.a
+END GROUP
+LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a
+LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5\libc.a
+LOAD e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a
+
+.hash
+ *(.hash)
+
+.dynsym
+ *(.dynsym)
+
+.dynstr
+ *(.dynstr)
+
+.gnu.version
+ *(.gnu.version)
+
+.gnu.version_d
+ *(.gnu.version_d)
+
+.gnu.version_r
+ *(.gnu.version_r)
+
+.rel.init
+ *(.rel.init)
+
+.rela.init
+ *(.rela.init)
+
+.rel.text
+ *(.rel.text)
+ *(.rel.text.*)
+ *(.rel.gnu.linkonce.t*)
+
+.rela.text
+ *(.rela.text)
+ *(.rela.text.*)
+ *(.rela.gnu.linkonce.t*)
+
+.rel.fini
+ *(.rel.fini)
+
+.rela.fini
+ *(.rela.fini)
+
+.rel.rodata
+ *(.rel.rodata)
+ *(.rel.rodata.*)
+ *(.rel.gnu.linkonce.r*)
+
+.rela.rodata
+ *(.rela.rodata)
+ *(.rela.rodata.*)
+ *(.rela.gnu.linkonce.r*)
+
+.rel.data
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.gnu.linkonce.d*)
+
+.rela.data
+ *(.rela.data)
+ *(.rela.data.*)
+ *(.rela.gnu.linkonce.d*)
+
+.rel.ctors
+ *(.rel.ctors)
+
+.rela.ctors
+ *(.rela.ctors)
+
+.rel.dtors
+ *(.rel.dtors)
+
+.rela.dtors
+ *(.rela.dtors)
+
+.rel.got
+ *(.rel.got)
+
+.rela.got
+ *(.rela.got)
+
+.rel.bss
+ *(.rel.bss)
+
+.rela.bss
+ *(.rela.bss)
+
+.rel.plt
+ *(.rel.plt)
+
+.rela.plt
+ *(.rela.plt)
+
+.text           0x00000000      0x73c
+ *(.vectors)
+ .vectors       0x00000000       0x54 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+                0x00000000                __vector_default
+                0x00000000                __vectors
+ *(.vectors)
+ *(.progmem.gcc*)
+ *(.progmem*)
+                0x00000054                . = ALIGN (0x2)
+                0x00000054                __trampolines_start = .
+ *(.trampolines)
+ .trampolines   0x00000054        0x0 linker stubs
+ *(.trampolines*)
+                0x00000054                __trampolines_end = .
+ *(.jumptables)
+ *(.jumptables*)
+ *(.lowtext)
+ *(.lowtext*)
+                0x00000054                __ctors_start = .
+ *(.ctors)
+                0x00000054                __ctors_end = .
+                0x00000054                __dtors_start = .
+ *(.dtors)
+                0x00000054                __dtors_end = .
+ SORT(*)(.ctors)
+ SORT(*)(.dtors)
+ *(.init0)
+ .init0         0x00000054        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+                0x00000054                __init
+ *(.init0)
+ *(.init1)
+ *(.init1)
+ *(.init2)
+ .init2         0x00000054        0xc e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+ *(.init2)
+ *(.init3)
+ *(.init3)
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+ .init4         0x00000060       0x16 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+                0x00000060                __do_copy_data
+ .init4         0x00000076       0x10 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                0x00000076                __do_clear_bss
+ *(.init4)
+ *(.init5)
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+ *(.init9)
+ *(.text)
+ .text          0x0000008e        0x4 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/../../../../avr/lib/avr5/crtm16a.o
+                0x0000008e                __vector_1
+                0x0000008e                __vector_12
+                0x0000008e                __bad_interrupt
+                0x0000008e                __vector_6
+                0x0000008e                __vector_3
+                0x0000008e                __vector_11
+                0x0000008e                __vector_13
+                0x0000008e                __vector_17
+                0x0000008e                __vector_19
+                0x0000008e                __vector_7
+                0x0000008e                __vector_5
+                0x0000008e                __vector_4
+                0x0000008e                __vector_2
+                0x0000008e                __vector_15
+                0x0000008e                __vector_8
+                0x0000008e                __vector_14
+                0x0000008e                __vector_10
+                0x0000008e                __vector_16
+                0x0000008e                __vector_18
+                0x0000008e                __vector_20
+ .text          0x00000092      0x2d0 Reciver.o
+                0x00000092                turn
+                0x00000126                poll
+                0x000001cc                recive
+                0x00000280                init_timer
+                0x00000290                __vector_9
+ .text          0x00000362      0x320 rf12.o
+                0x00000362                rf12_trans
+                0x00000392                rf12_init
+                0x000003e6                rf12_setbandwidth
+                0x0000041e                rf12_setfreq
+                0x0000043e                rf12_setbaud
+                0x00000486                rf12_setpower
+                0x000004a6                rf12_ready
+                0x000004ae                rf12_beginasyncrx
+                0x000004c8                rf12_hasdata
+                0x000004d2                rf12_rxbyte
+                0x000004dc                rf12_endasyncrx
+                0x000004e6                rf12_txdata
+                0x00000570                rf12_rxdata
+                0x000005c8                rf12_txpacket
+ .text          0x00000682        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+ .text          0x00000682        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+ .text          0x00000682        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .text          0x00000682        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+ .text          0x00000682        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                0x00000682                . = ALIGN (0x2)
+ *(.text.*)
+ .text.startup  0x00000682       0x3c Reciver.o
+                0x00000682                main
+ .text.libgcc   0x000006be       0x44 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_udivmodsi4.o)
+                0x000006be                __udivmodsi4
+ .text.libgcc   0x00000702       0x36 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_divmodsi4.o)
+                0x00000702                __divmodsi4
+ .text.libgcc   0x00000738        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+ .text.libgcc   0x00000738        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_copy_data.o)
+ .text.libgcc   0x00000738        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
+                0x00000738                . = ALIGN (0x2)
+ *(.fini9)
+ .fini9         0x00000738        0x0 e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_exit.o)
+                0x00000738                _exit
+                0x00000738                exit
+ *(.fini9)
+ *(.fini8)
+ *(.fini8)
+ *(.fini7)
+ *(.fini7)
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+ *(.fini6)
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+ *(.fini4)
+ *(.fini4)
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+ *(.fini0)
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+ .data          0x00800060        0x4 Reciver.o
+                0x00800060                servopos
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+                0x0000073c                __data_load_start = LOADADDR (.data)
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+ .debug_line    0x00000262       0x8e e:/programme/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.4.1.95/avrtoolchain/bin/../lib/gcc/avr/4.6.2/avr5\libgcc.a(_clear_bss.o)
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+OUTPUT(Reciver.elf elf32-avr)
+LOAD linker stubs
diff --git a/V5B/Reciver/Reciver/Release/Reciver.srec b/V5B/Reciver/Reciver/Release/Reciver.srec
new file mode 100644
index 0000000..d547104
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/Reciver.srec
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diff --git a/V5B/Reciver/Reciver/Release/makedep.mk b/V5B/Reciver/Reciver/Release/makedep.mk
new file mode 100644
index 0000000..562bd5a
--- /dev/null
+++ b/V5B/Reciver/Reciver/Release/makedep.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+Reciver.c
+
+rf12.c
+
diff --git a/V5B/Reciver/Reciver/codes.h b/V5B/Reciver/Reciver/codes.h
new file mode 100644
index 0000000..54dae38
--- /dev/null
+++ b/V5B/Reciver/Reciver/codes.h
@@ -0,0 +1,31 @@
+/*
+ * codes.h
+ *
+ * Created: 29.03.2013 13:58:28
+ *  Author: netz
+ */ 
+
+
+#ifndef CODES_H_
+#define CODES_H_
+
+#ifndef ALL
+#define ALL 0
+#define GROUP 240
+#define DEVICE 10
+#define MASTER 1
+#endif
+
+#ifndef PING
+#define PING 1
+#define SLEEP 2
+#define ACTIVE 3
+#define SETSLEEP 4
+#define SETACTIVE 5
+#define RUN 6
+#define SETRUN 7
+#define DEDECT 8
+#define SETDEDECT 9
+#endif
+
+#endif /* CODES_H_ */
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/global.h b/V5B/Reciver/Reciver/global.h
new file mode 100644
index 0000000..b57ba79
--- /dev/null
+++ b/V5B/Reciver/Reciver/global.h
@@ -0,0 +1,36 @@
+/*
+ * global.h
+ *
+ * Created: 25.03.2013 21:12:17
+ *  Author: netz
+ */ 
+
+
+
+#ifndef GLOBAL_H_
+#define GLOBAL_H_
+
+#ifndef F_CPU
+#define F_CPU 8000000
+#endif
+
+#ifndef LEFT
+#define LEFT 600
+#define RIGHT 180
+#define STEP 8
+#endif
+
+#ifndef RF_PORT
+#define RF_PORT PORTA
+#define RF_DDR DDRA
+#define RF_PIN PINA
+#endif
+
+#ifndef CS
+#define CS PINA1
+#define SCK PINA2
+#define SDI PINA3
+#define SDO PINA0
+#endif
+
+#endif /* GLOBAL_H_ */
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/rf12.c b/V5B/Reciver/Reciver/rf12.c
new file mode 100644
index 0000000..07a9a42
--- /dev/null
+++ b/V5B/Reciver/Reciver/rf12.c
@@ -0,0 +1,169 @@
+/*
+ * rf12.c
+ *
+ * Created: 24.03.2013 23:52:52
+ *  Author: netz
+ */
+
+#include <avr/io.h>
+#include "rf12.h"
+#include <util/delay.h>
+
+unsigned short rf12_trans(unsigned short wert)
+{	
+	unsigned short werti = 0;
+	unsigned char i;
+	
+	RF_PORT &= ~(1<<CS);
+	for (i=0; i<16; i++)
+	{	
+		if (wert&32768) {
+			RF_PORT |= (1<<SDI);
+		}		
+		else {
+			RF_PORT &= ~(1<<SDI);
+		}			
+		werti<<=1;
+		if (RF_PIN & (1<<SDO)) {
+			werti|=1;
+		}		
+		RF_PORT |= (1<<SCK);
+		wert<<=1;
+		_delay_us(0.3);
+		RF_PORT &= ~(1<<SCK);
+	}
+	RF_PORT |= (1<<CS);
+	return werti;
+}
+
+void rf12_init(void)
+{
+	RF_DDR |= (1<<SDI) | (1<<SCK) | (1<<CS);
+	RF_PORT |= (1<<CS);
+
+	_delay_ms(100);
+
+	rf12_trans(0xC0E0);			// AVR CLK: 10MHz
+	rf12_trans(0x80D7);			// Enable FIFO
+	rf12_trans(0xC2AB);			// Data Filter: internal
+	rf12_trans(0xCA81);			// Set FIFO mode
+	rf12_trans(0xE000);			// disable wakeuptimer
+	rf12_trans(0xC800);			// disable low duty cycle
+	rf12_trans(0xC4F7);			// AFC settings: autotuning: -10kHz...+7,5kHz
+}
+
+void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
+{
+	rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
+}
+
+void rf12_setfreq(unsigned short freq)
+{	
+	if (freq<96) {				// 430,2400MHz
+		freq=96;
+	} else if (freq>3903) {		// 439,7575MHz
+		freq=3903;
+	}	
+	rf12_trans(0xA000|freq);
+}
+
+void rf12_setbaud(unsigned short baud)
+{
+	if (baud<663) {
+		return;
+	}	
+	if (baud<5400) {				// Baudrate= 344827,58621/(R+1)/(1+CS*7)
+		rf12_trans(0xC680|((43104/baud)-1));
+	} else {
+		rf12_trans(0xC600|((344828UL/baud)-1));
+	}	
+}
+
+void rf12_setpower(unsigned char power, unsigned char mod)
+{
+	rf12_trans(0x9800|(power&7)|((mod&15)<<4));
+}
+
+void rf12_ready(void)
+{	
+	RF_PORT &= ~(1<<CS);
+	while (!(RF_PIN & (1<<SDO))); // wait until FIFO ready
+}
+
+void rf12_beginasyncrx() {
+	rf12_trans(0x82C8);			// RX on
+	rf12_trans(0xCA81);			// set FIFO mode
+	rf12_trans(0xCA83);			// enable FIFO
+}
+uint8_t rf12_hasdata() {
+	RF_PORT &= ~(1<<CS);
+	return !(RF_PIN & (1<<SDO));
+}
+uint8_t rf12_rxbyte() {
+	return rf12_trans(0xB000);
+}
+void rf12_endasyncrx() {
+	rf12_trans(0x8208);			// RX off
+}
+
+void rf12_txdata(unsigned char *data, unsigned char number)
+{	
+	unsigned char i;
+	rf12_trans(0x8238);			// TX on
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB82D);
+	rf12_ready();
+	rf12_trans(0xB8D4);
+	for (i=0; i<number; i++)
+	{		
+		rf12_ready();
+		rf12_trans(0xB800|(*data++));
+	}
+	rf12_ready();
+	rf12_trans(0x8208);			// TX off
+}
+
+void rf12_rxdata(unsigned char *data, unsigned char number)
+{	
+	unsigned char i;
+	rf12_trans(0x82C8);			// RX on
+	rf12_trans(0xCA81);			// set FIFO mode
+	rf12_trans(0xCA83);			// enable FIFO
+	for (i=0; i<number; i++)
+	{	
+		rf12_ready();
+		*data++=rf12_trans(0xB000);
+	}
+	rf12_trans(0x8208);			// RX off
+}
+
+void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) {
+	rf12_trans(0x8238);			// TX on
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB8AA);
+	rf12_ready();
+	rf12_trans(0xB82D);
+	rf12_ready();
+	rf12_trans(0xB8D4);
+	rf12_ready();
+	rf12_trans(0xB800|addr);
+	rf12_ready();
+	rf12_trans(0xB800|from);
+	rf12_ready();
+	rf12_trans(0xB800|data);
+	rf12_ready();
+	rf12_trans(0xB800);
+	rf12_ready();
+	rf12_trans(0x8208); // TX off
+	_delay_ms(100);
+}
\ No newline at end of file
diff --git a/V5B/Reciver/Reciver/rf12.h b/V5B/Reciver/Reciver/rf12.h
new file mode 100644
index 0000000..bf2ffd0
--- /dev/null
+++ b/V5B/Reciver/Reciver/rf12.h
@@ -0,0 +1,31 @@
+/*
+ * rf12.h
+ *
+ * Created: 25.03.2013 00:25:08
+ *  Author: netz
+ */ 
+
+
+#ifndef RF12_H_
+#define RF12_H_
+
+extern unsigned short rf12_trans(unsigned short wert);					// transfer 1 word to/from module
+extern void rf12_init(void);											// initialize module
+extern void rf12_setfreq(unsigned short freq);							// set center frequency
+extern void rf12_setbaud(unsigned short baud);							// set baudrate
+extern void rf12_setpower(unsigned char power, unsigned char mod);		// set transmission settings
+extern void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi);	// set receiver settings
+extern void rf12_txdata(unsigned char *data, unsigned char number);		// transmit number of bytes from array
+extern void rf12_rxdata(unsigned char *data, unsigned char number);		// receive number of bytes into array
+extern void rf12_ready(void);											// wait until FIFO ready (to transmit/read data)
+extern void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data);	// Send two bytes over the air
+void rf12_beginasyncrx();												// Init RX of Bytes
+uint8_t rf12_hasdata();													// Returns 0 if Bytes are there
+uint8_t rf12_rxbyte();													// Rx one Byte
+void rf12_endasyncrx();													// End RX of Bytes
+
+#define RF12FREQ(freq)	((freq-430.0)/0.0025)							// macro for calculating frequency value out of frequency in MHz
+
+#include "global.h"
+
+#endif /* RF12_H_ */
\ No newline at end of file