diff --git a/V5B/Reciver/Reciver.atsuo b/V5B/Reciver/Reciver.atsuo index 150a089..5b7cd7c 100644 Binary files a/V5B/Reciver/Reciver.atsuo and b/V5B/Reciver/Reciver.atsuo differ diff --git a/V5B/Reciver/Reciver/Debug/Reciver.elf b/V5B/Reciver/Reciver/Debug/Reciver.elf index 651d6ba..fc8efc3 100644 Binary files a/V5B/Reciver/Reciver/Debug/Reciver.elf and b/V5B/Reciver/Reciver/Debug/Reciver.elf differ diff --git a/V5B/Reciver/Reciver/Debug/Reciver.hex b/V5B/Reciver/Reciver/Debug/Reciver.hex index 4adf1d5..83dce53 100644 --- a/V5B/Reciver/Reciver/Debug/Reciver.hex +++ b/V5B/Reciver/Reciver/Debug/Reciver.hex @@ -1,93 +1,98 @@ :1000000010C028C027C026C025C024C023C022C0DD -:1000100021C020C01FC005C11DC01CC01BC01AC00C +:1000100021C020C01FC02AC11DC01CC01BC01AC0E7 :1000200019C011241FBECFEDCDBF10E0A0E6B0E097 -:10003000EAEAF5E002C005900D92A436B107D9F7BF +:10003000E4EFF5E002C005900D92A436B107D9F7C0 :1000400020E0A4E6B0E001C01D92A636B207E1F7B9 -:1000500061D1A9C2D5CF80916200909163000697CB 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diff --git a/V5B/Reciver/Reciver/Debug/Reciver.lss b/V5B/Reciver/Reciver/Debug/Reciver.lss index d86dcf9..4030479 100644 --- a/V5B/Reciver/Reciver/Debug/Reciver.lss +++ b/V5B/Reciver/Reciver/Debug/Reciver.lss @@ -3,33 +3,33 @@ Reciver.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn - 0 .text 000005aa 00000000 00000000 00000094 2**1 + 0 .text 000005f4 00000000 00000000 00000094 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 00000004 00800060 000005aa 0000063e 2**0 + 1 .data 00000004 00800060 000005f4 00000688 2**0 CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000002 00800064 00800064 00000642 2**0 + 2 .bss 00000002 00800064 00800064 0000068c 2**0 ALLOC - 3 .stab 000006b4 00000000 00000000 00000644 2**2 + 3 .stab 000006b4 00000000 00000000 0000068c 2**2 CONTENTS, READONLY, DEBUGGING - 4 .stabstr 00000082 00000000 00000000 00000cf8 2**0 + 4 .stabstr 00000082 00000000 00000000 00000d40 2**0 CONTENTS, READONLY, DEBUGGING - 5 .comment 0000002f 00000000 00000000 00000d7a 2**0 + 5 .comment 0000002f 00000000 00000000 00000dc2 2**0 CONTENTS, READONLY - 6 .debug_aranges 000000d0 00000000 00000000 00000da9 2**0 + 6 .debug_aranges 000000d0 00000000 00000000 00000df1 2**0 CONTENTS, READONLY, DEBUGGING - 7 .debug_info 00000f8f 00000000 00000000 00000e79 2**0 + 7 .debug_info 00001026 00000000 00000000 00000ec1 2**0 CONTENTS, READONLY, DEBUGGING - 8 .debug_abbrev 00000420 00000000 00000000 00001e08 2**0 + 8 .debug_abbrev 0000040a 00000000 00000000 00001ee7 2**0 CONTENTS, READONLY, DEBUGGING - 9 .debug_line 00000553 00000000 00000000 00002228 2**0 + 9 .debug_line 0000056e 00000000 00000000 000022f1 2**0 CONTENTS, READONLY, DEBUGGING - 10 .debug_frame 000001c8 00000000 00000000 0000277c 2**2 + 10 .debug_frame 000001c8 00000000 00000000 00002860 2**2 CONTENTS, READONLY, DEBUGGING - 11 .debug_str 00000243 00000000 00000000 00002944 2**0 + 11 .debug_str 00000243 00000000 00000000 00002a28 2**0 CONTENTS, READONLY, DEBUGGING - 12 .debug_loc 00000767 00000000 00000000 00002b87 2**0 + 12 .debug_loc 000007d0 00000000 00000000 00002c6b 2**0 CONTENTS, READONLY, DEBUGGING - 13 .debug_ranges 000000b0 00000000 00000000 000032ee 2**0 + 13 .debug_ranges 000000b0 00000000 00000000 0000343b 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: @@ -46,7 +46,7 @@ Disassembly of section .text: 10: 21 c0 rjmp .+66 ; 0x54 <__bad_interrupt> 12: 20 c0 rjmp .+64 ; 0x54 <__bad_interrupt> 14: 1f c0 rjmp .+62 ; 0x54 <__bad_interrupt> - 16: 05 c1 rjmp .+522 ; 0x222 <__vector_11> + 16: 2a c1 rjmp .+596 ; 0x26c <__vector_11> 18: 1d c0 rjmp .+58 ; 0x54 <__bad_interrupt> 1a: 1c c0 rjmp .+56 ; 0x54 <__bad_interrupt> 1c: 1b c0 rjmp .+54 ; 0x54 <__bad_interrupt> @@ -63,7 +63,7 @@ Disassembly of section .text: 2a: 10 e0 ldi r17, 0x00 ; 0 2c: a0 e6 ldi r26, 0x60 ; 96 2e: b0 e0 ldi r27, 0x00 ; 0 - 30: ea ea ldi r30, 0xAA ; 170 + 30: e4 ef ldi r30, 0xF4 ; 244 32: f5 e0 ldi r31, 0x05 ; 5 34: 02 c0 rjmp .+4 ; 0x3a <__do_copy_data+0x10> 36: 05 90 lpm r0, Z+ @@ -85,8 +85,8 @@ Disassembly of section .text: 4a: a6 36 cpi r26, 0x66 ; 102 4c: b2 07 cpc r27, r18 4e: e1 f7 brne .-8 ; 0x48 <.do_clear_bss_loop> - 50: 61 d1 rcall .+706 ; 0x314
- 52: a9 c2 rjmp .+1362 ; 0x5a6 <_exit> + 50: 86 d1 rcall .+780 ; 0x35e
+ 52: ce c2 rjmp .+1436 ; 0x5f0 <_exit> 00000054 <__bad_interrupt>: 54: d5 cf rjmp .-86 ; 0x0 <__vectors> @@ -102,15 +102,15 @@ void turn() { 5a: 90 91 63 00 lds r25, 0x0063 5e: 06 97 sbiw r24, 0x06 ; 6 60: 09 f4 brne .+2 ; 0x64 - 62: 40 c0 rjmp .+128 ; 0xe4 <__stack+0x5> + 62: 43 c0 rjmp .+134 ; 0xea <__stack+0xb> return; status = RUN; 64: 86 e0 ldi r24, 0x06 ; 6 66: 90 e0 ldi r25, 0x00 ; 0 68: 90 93 63 00 sts 0x0063, r25 6c: 80 93 62 00 sts 0x0062, r24 - servopos = RIGHT-90; - 70: 8a e5 ldi r24, 0x5A ; 90 + servopos = RIGHT-140; + 70: 88 e2 ldi r24, 0x28 ; 40 72: 90 e0 ldi r25, 0x00 ; 0 74: 90 93 61 00 sts 0x0061, r25 78: 80 93 60 00 sts 0x0060, r24 @@ -120,993 +120,1034 @@ void turn() { #endif __builtin_avr_delay_cycles(__ticks_dc); - 7c: 8f e3 ldi r24, 0x3F ; 63 - 7e: 9c e9 ldi r25, 0x9C ; 156 - 80: 01 97 sbiw r24, 0x01 ; 1 - 82: f1 f7 brne .-4 ; 0x80 - 84: 00 c0 rjmp .+0 ; 0x86 - 86: 00 00 nop + 7c: 2f e7 ldi r18, 0x7F ; 127 + 7e: 88 e3 ldi r24, 0x38 ; 56 + 80: 91 e0 ldi r25, 0x01 ; 1 + 82: 21 50 subi r18, 0x01 ; 1 + 84: 80 40 sbci r24, 0x00 ; 0 + 86: 90 40 sbci r25, 0x00 ; 0 + 88: e1 f7 brne .-8 ; 0x82 + 8a: 00 c0 rjmp .+0 ; 0x8c + 8c: 00 00 nop _delay_ms(10+DEVICE); rf12_txpacket(MASTER, DEVICE, status); - 88: 40 91 62 00 lds r20, 0x0062 - 8c: 50 91 63 00 lds r21, 0x0063 - 90: 6a e0 ldi r22, 0x0A ; 10 - 92: 81 e0 ldi r24, 0x01 ; 1 - 94: 0a d2 rcall .+1044 ; 0x4aa - 96: 9f ef ldi r25, 0xFF ; 255 - 98: 23 ec ldi r18, 0xC3 ; 195 - 9a: 89 e0 ldi r24, 0x09 ; 9 - 9c: 91 50 subi r25, 0x01 ; 1 - 9e: 20 40 sbci r18, 0x00 ; 0 - a0: 80 40 sbci r24, 0x00 ; 0 - a2: e1 f7 brne .-8 ; 0x9c - a4: 00 c0 rjmp .+0 ; 0xa6 - a6: 00 00 nop + 8e: 40 91 62 00 lds r20, 0x0062 + 92: 50 91 63 00 lds r21, 0x0063 + 96: 68 e2 ldi r22, 0x28 ; 40 + 98: 81 e0 ldi r24, 0x01 ; 1 + 9a: 2c d2 rcall .+1112 ; 0x4f4 + 9c: 2f ef ldi r18, 0xFF ; 255 + 9e: 83 ec ldi r24, 0xC3 ; 195 + a0: 99 e0 ldi r25, 0x09 ; 9 + a2: 21 50 subi r18, 0x01 ; 1 + a4: 80 40 sbci r24, 0x00 ; 0 + a6: 90 40 sbci r25, 0x00 ; 0 + a8: e1 f7 brne .-8 ; 0xa2 + aa: 00 c0 rjmp .+0 ; 0xac + ac: 00 00 nop _delay_ms(400); - servopos = RIGHT-140; - a8: 88 e2 ldi r24, 0x28 ; 40 - aa: 90 e0 ldi r25, 0x00 ; 0 - ac: 90 93 61 00 sts 0x0061, r25 - b0: 80 93 60 00 sts 0x0060, r24 - b4: 9f ef ldi r25, 0xFF ; 255 - b6: 22 e5 ldi r18, 0x52 ; 82 - b8: 87 e0 ldi r24, 0x07 ; 7 - ba: 91 50 subi r25, 0x01 ; 1 - bc: 20 40 sbci r18, 0x00 ; 0 - be: 80 40 sbci r24, 0x00 ; 0 - c0: e1 f7 brne .-8 ; 0xba - c2: 00 c0 rjmp .+0 ; 0xc4 - c4: 00 00 nop + servopos = RIGHT-160; + ae: 84 e1 ldi r24, 0x14 ; 20 + b0: 90 e0 ldi r25, 0x00 ; 0 + b2: 90 93 61 00 sts 0x0061, r25 + b6: 80 93 60 00 sts 0x0060, r24 + ba: 2f ef ldi r18, 0xFF ; 255 + bc: 82 e5 ldi r24, 0x52 ; 82 + be: 97 e0 ldi r25, 0x07 ; 7 + c0: 21 50 subi r18, 0x01 ; 1 + c2: 80 40 sbci r24, 0x00 ; 0 + c4: 90 40 sbci r25, 0x00 ; 0 + c6: e1 f7 brne .-8 ; 0xc0 + c8: 00 c0 rjmp .+0 ; 0xca + ca: 00 00 nop _delay_ms(300); servopos = RIGHT; - c6: 84 eb ldi r24, 0xB4 ; 180 - c8: 90 e0 ldi r25, 0x00 ; 0 - ca: 90 93 61 00 sts 0x0061, r25 - ce: 80 93 60 00 sts 0x0060, r24 - d2: 9f ef ldi r25, 0xFF ; 255 - d4: 26 e1 ldi r18, 0x16 ; 22 - d6: 81 e1 ldi r24, 0x11 ; 17 - d8: 91 50 subi r25, 0x01 ; 1 - da: 20 40 sbci r18, 0x00 ; 0 - dc: 80 40 sbci r24, 0x00 ; 0 - de: e1 f7 brne .-8 ; 0xd8 - e0: 00 c0 rjmp .+0 ; 0xe2 <__stack+0x3> - e2: 00 00 nop - e4: 08 95 ret + cc: 84 eb ldi r24, 0xB4 ; 180 + ce: 90 e0 ldi r25, 0x00 ; 0 + d0: 90 93 61 00 sts 0x0061, r25 + d4: 80 93 60 00 sts 0x0060, r24 + d8: 2f ef ldi r18, 0xFF ; 255 + da: 86 e1 ldi r24, 0x16 ; 22 + dc: 91 e1 ldi r25, 0x11 ; 17 + de: 21 50 subi r18, 0x01 ; 1 + e0: 80 40 sbci r24, 0x00 ; 0 + e2: 90 40 sbci r25, 0x00 ; 0 + e4: e1 f7 brne .-8 ; 0xde + e6: 00 c0 rjmp .+0 ; 0xe8 <__stack+0x9> + e8: 00 00 nop + ea: 08 95 ret -000000e6 : +000000ec : _delay_ms(700); } void poll() { DDRB &= ~(1< + ee: 80 91 62 00 lds r24, 0x0062 + f2: 90 91 63 00 lds r25, 0x0063 + f6: 03 97 sbiw r24, 0x03 ; 3 + f8: 29 f4 brne .+10 ; 0x104 if(PINB & (1< + fa: b2 9b sbis 0x16, 2 ; 22 + fc: 03 c0 rjmp .+6 ; 0x104 rf12_endasyncrx(); - f8: d4 d1 rcall .+936 ; 0x4a2 + fe: f6 d1 rcall .+1004 ; 0x4ec turn(); - fa: ad df rcall .-166 ; 0x56 + 100: aa df rcall .-172 ; 0x56 rf12_beginasyncrx(); - fc: bf d1 rcall .+894 ; 0x47c + 102: e1 d1 rcall .+962 ; 0x4c6 } } if(status == SLEEP) { - fe: 80 91 62 00 lds r24, 0x0062 - 102: 90 91 63 00 lds r25, 0x0063 - 106: 02 97 sbiw r24, 0x02 ; 2 - 108: 41 f4 brne .+16 ; 0x11a + 104: 80 91 62 00 lds r24, 0x0062 + 108: 90 91 63 00 lds r25, 0x0063 + 10c: 02 97 sbiw r24, 0x02 ; 2 + 10e: 41 f4 brne .+16 ; 0x120 if(PINB & (1< + 110: b2 9b sbis 0x16, 2 ; 22 + 112: 06 c0 rjmp .+12 ; 0x120 rf12_endasyncrx(); - 10e: c9 d1 rcall .+914 ; 0x4a2 + 114: eb d1 rcall .+982 ; 0x4ec rf12_txpacket(MASTER, DEVICE, DEDECT); - 110: 48 e0 ldi r20, 0x08 ; 8 - 112: 6a e0 ldi r22, 0x0A ; 10 - 114: 81 e0 ldi r24, 0x01 ; 1 - 116: c9 d1 rcall .+914 ; 0x4aa + 116: 48 e0 ldi r20, 0x08 ; 8 + 118: 68 e2 ldi r22, 0x28 ; 40 + 11a: 81 e0 ldi r24, 0x01 ; 1 + 11c: eb d1 rcall .+982 ; 0x4f4 rf12_beginasyncrx(); - 118: b1 d1 rcall .+866 ; 0x47c + 11e: d3 d1 rcall .+934 ; 0x4c6 } } if(!(PINA & (1< + 120: cc 99 sbic 0x19, 4 ; 25 + 122: 2d c0 rjmp .+90 ; 0x17e if(status == SLEEP) { - 11e: 80 91 62 00 lds r24, 0x0062 - 122: 90 91 63 00 lds r25, 0x0063 - 126: 02 97 sbiw r24, 0x02 ; 2 - 128: 39 f5 brne .+78 ; 0x178 + 124: 80 91 62 00 lds r24, 0x0062 + 128: 90 91 63 00 lds r25, 0x0063 + 12c: 02 97 sbiw r24, 0x02 ; 2 + 12e: 39 f5 brne .+78 ; 0x17e status = RUN; - 12a: 86 e0 ldi r24, 0x06 ; 6 - 12c: 90 e0 ldi r25, 0x00 ; 0 - 12e: 90 93 63 00 sts 0x0063, r25 - 132: 80 93 62 00 sts 0x0062, r24 - 136: 2f ef ldi r18, 0xFF ; 255 - 138: 81 e1 ldi r24, 0x11 ; 17 - 13a: 9a e7 ldi r25, 0x7A ; 122 - 13c: 21 50 subi r18, 0x01 ; 1 - 13e: 80 40 sbci r24, 0x00 ; 0 - 140: 90 40 sbci r25, 0x00 ; 0 - 142: e1 f7 brne .-8 ; 0x13c - 144: 00 c0 rjmp .+0 ; 0x146 - 146: 00 00 nop - 148: 2f ef ldi r18, 0xFF ; 255 - 14a: 81 e1 ldi r24, 0x11 ; 17 - 14c: 9a e7 ldi r25, 0x7A ; 122 - 14e: 21 50 subi r18, 0x01 ; 1 - 150: 80 40 sbci r24, 0x00 ; 0 - 152: 90 40 sbci r25, 0x00 ; 0 - 154: e1 f7 brne .-8 ; 0x14e - 156: 00 c0 rjmp .+0 ; 0x158 - 158: 00 00 nop - 15a: 2f ef ldi r18, 0xFF ; 255 - 15c: 81 e1 ldi r24, 0x11 ; 17 - 15e: 9a e7 ldi r25, 0x7A ; 122 - 160: 21 50 subi r18, 0x01 ; 1 - 162: 80 40 sbci r24, 0x00 ; 0 - 164: 90 40 sbci r25, 0x00 ; 0 - 166: e1 f7 brne .-8 ; 0x160 - 168: 00 c0 rjmp .+0 ; 0x16a - 16a: 00 00 nop + 130: 86 e0 ldi r24, 0x06 ; 6 + 132: 90 e0 ldi r25, 0x00 ; 0 + 134: 90 93 63 00 sts 0x0063, r25 + 138: 80 93 62 00 sts 0x0062, r24 + 13c: 2f ef ldi r18, 0xFF ; 255 + 13e: 81 e1 ldi r24, 0x11 ; 17 + 140: 9a e7 ldi r25, 0x7A ; 122 + 142: 21 50 subi r18, 0x01 ; 1 + 144: 80 40 sbci r24, 0x00 ; 0 + 146: 90 40 sbci r25, 0x00 ; 0 + 148: e1 f7 brne .-8 ; 0x142 + 14a: 00 c0 rjmp .+0 ; 0x14c + 14c: 00 00 nop + 14e: 2f ef ldi r18, 0xFF ; 255 + 150: 81 e1 ldi r24, 0x11 ; 17 + 152: 9a e7 ldi r25, 0x7A ; 122 + 154: 21 50 subi r18, 0x01 ; 1 + 156: 80 40 sbci r24, 0x00 ; 0 + 158: 90 40 sbci r25, 0x00 ; 0 + 15a: e1 f7 brne .-8 ; 0x154 + 15c: 00 c0 rjmp .+0 ; 0x15e + 15e: 00 00 nop + 160: 2f ef ldi r18, 0xFF ; 255 + 162: 81 e1 ldi r24, 0x11 ; 17 + 164: 9a e7 ldi r25, 0x7A ; 122 + 166: 21 50 subi r18, 0x01 ; 1 + 168: 80 40 sbci r24, 0x00 ; 0 + 16a: 90 40 sbci r25, 0x00 ; 0 + 16c: e1 f7 brne .-8 ; 0x166 + 16e: 00 c0 rjmp .+0 ; 0x170 + 170: 00 00 nop _delay_ms(5000); _delay_ms(5000); _delay_ms(5000); status = ACTIVE; - 16c: 83 e0 ldi r24, 0x03 ; 3 - 16e: 90 e0 ldi r25, 0x00 ; 0 - 170: 90 93 63 00 sts 0x0063, r25 - 174: 80 93 62 00 sts 0x0062, r24 - 178: 08 95 ret + 172: 83 e0 ldi r24, 0x03 ; 3 + 174: 90 e0 ldi r25, 0x00 ; 0 + 176: 90 93 63 00 sts 0x0063, r25 + 17a: 80 93 62 00 sts 0x0062, r24 + 17e: 08 95 ret -0000017a : +00000180 : } } } void recive() { - 17a: cf 93 push r28 + 180: cf 93 push r28 rf12_beginasyncrx(); - 17c: 7f d1 rcall .+766 ; 0x47c + 182: a1 d1 rcall .+834 ; 0x4c6 while(rf12_hasdata()) { - 17e: 01 c0 rjmp .+2 ; 0x182 + 184: 01 c0 rjmp .+2 ; 0x188 poll(); - 180: b2 df rcall .-156 ; 0xe6 + 186: b2 df rcall .-156 ; 0xec } } void recive() { rf12_beginasyncrx(); while(rf12_hasdata()) { - 182: 86 d1 rcall .+780 ; 0x490 - 184: 81 11 cpse r24, r1 - 186: fc cf rjmp .-8 ; 0x180 + 188: a8 d1 rcall .+848 ; 0x4da + 18a: 81 11 cpse r24, r1 + 18c: fc cf rjmp .-8 ; 0x186 poll(); } uint8_t addr = rf12_rxbyte(); - 188: 88 d1 rcall .+784 ; 0x49a + 18e: aa d1 rcall .+852 ; 0x4e4 if(addr == ALL || addr == DEVICE || addr == GROUP) { - 18a: 88 23 and r24, r24 - 18c: 31 f0 breq .+12 ; 0x19a - 18e: 8a 30 cpi r24, 0x0A ; 10 - 190: 21 f0 breq .+8 ; 0x19a - 192: 80 3f cpi r24, 0xF0 ; 240 - 194: e1 f5 brne .+120 ; 0x20e - 196: 01 c0 rjmp .+2 ; 0x19a + 190: 88 23 and r24, r24 + 192: 39 f0 breq .+14 ; 0x1a2 + 194: 88 32 cpi r24, 0x28 ; 40 + 196: 29 f0 breq .+10 ; 0x1a2 + 198: 80 3f cpi r24, 0xF0 ; 240 + 19a: 09 f0 breq .+2 ; 0x19e + 19c: 3f c0 rjmp .+126 ; 0x21c + 19e: 01 c0 rjmp .+2 ; 0x1a2 while(rf12_hasdata()) { poll(); - 198: a6 df rcall .-180 ; 0xe6 + 1a0: a5 df rcall .-182 ; 0xec while(rf12_hasdata()) { poll(); } uint8_t addr = rf12_rxbyte(); if(addr == ALL || addr == DEVICE || addr == GROUP) { while(rf12_hasdata()) { - 19a: 7a d1 rcall .+756 ; 0x490 - 19c: 81 11 cpse r24, r1 - 19e: fc cf rjmp .-8 ; 0x198 + 1a2: 9b d1 rcall .+822 ; 0x4da + 1a4: 81 11 cpse r24, r1 + 1a6: fc cf rjmp .-8 ; 0x1a0 poll(); } uint8_t from = rf12_rxbyte(); - 1a0: 7c d1 rcall .+760 ; 0x49a - 1a2: c8 2f mov r28, r24 + 1a8: 9d d1 rcall .+826 ; 0x4e4 + 1aa: c8 2f mov r28, r24 while(rf12_hasdata()) { - 1a4: 01 c0 rjmp .+2 ; 0x1a8 + 1ac: 01 c0 rjmp .+2 ; 0x1b0 poll(); - 1a6: 9f df rcall .-194 ; 0xe6 + 1ae: 9e df rcall .-196 ; 0xec if(addr == ALL || addr == DEVICE || addr == GROUP) { while(rf12_hasdata()) { poll(); } uint8_t from = rf12_rxbyte(); while(rf12_hasdata()) { - 1a8: 73 d1 rcall .+742 ; 0x490 - 1aa: 81 11 cpse r24, r1 - 1ac: fc cf rjmp .-8 ; 0x1a6 + 1b0: 94 d1 rcall .+808 ; 0x4da + 1b2: 81 11 cpse r24, r1 + 1b4: fc cf rjmp .-8 ; 0x1ae poll(); } if(from == MASTER) { - 1ae: c1 30 cpi r28, 0x01 ; 1 - 1b0: 71 f5 brne .+92 ; 0x20e + 1b6: c1 30 cpi r28, 0x01 ; 1 + 1b8: 89 f5 brne .+98 ; 0x21c uint8_t data = rf12_rxbyte(); - 1b2: 73 d1 rcall .+742 ; 0x49a + 1ba: 94 d1 rcall .+808 ; 0x4e4 switch(data) { - 1b4: 84 30 cpi r24, 0x04 ; 4 - 1b6: 49 f0 breq .+18 ; 0x1ca - 1b8: 18 f4 brcc .+6 ; 0x1c0 - 1ba: 81 30 cpi r24, 0x01 ; 1 - 1bc: c1 f4 brne .+48 ; 0x1ee - 1be: 19 c0 rjmp .+50 ; 0x1f2 - 1c0: 85 30 cpi r24, 0x05 ; 5 - 1c2: 51 f0 breq .+20 ; 0x1d8 - 1c4: 87 30 cpi r24, 0x07 ; 7 - 1c6: 99 f4 brne .+38 ; 0x1ee - 1c8: 0e c0 rjmp .+28 ; 0x1e6 + 1bc: 84 30 cpi r24, 0x04 ; 4 + 1be: 49 f0 breq .+18 ; 0x1d2 + 1c0: 18 f4 brcc .+6 ; 0x1c8 + 1c2: 81 30 cpi r24, 0x01 ; 1 + 1c4: c1 f4 brne .+48 ; 0x1f6 + 1c6: 19 c0 rjmp .+50 ; 0x1fa + 1c8: 85 30 cpi r24, 0x05 ; 5 + 1ca: 51 f0 breq .+20 ; 0x1e0 + 1cc: 87 30 cpi r24, 0x07 ; 7 + 1ce: 99 f4 brne .+38 ; 0x1f6 + 1d0: 0e c0 rjmp .+28 ; 0x1ee case PING: { break; } case SETSLEEP: { status = SLEEP; - 1ca: 82 e0 ldi r24, 0x02 ; 2 - 1cc: 90 e0 ldi r25, 0x00 ; 0 - 1ce: 90 93 63 00 sts 0x0063, r25 - 1d2: 80 93 62 00 sts 0x0062, r24 + 1d2: 82 e0 ldi r24, 0x02 ; 2 + 1d4: 90 e0 ldi r25, 0x00 ; 0 + 1d6: 90 93 63 00 sts 0x0063, r25 + 1da: 80 93 62 00 sts 0x0062, r24 break; - 1d6: 0d c0 rjmp .+26 ; 0x1f2 + 1de: 0d c0 rjmp .+26 ; 0x1fa } case SETACTIVE: { status = ACTIVE; - 1d8: 83 e0 ldi r24, 0x03 ; 3 - 1da: 90 e0 ldi r25, 0x00 ; 0 - 1dc: 90 93 63 00 sts 0x0063, r25 - 1e0: 80 93 62 00 sts 0x0062, r24 + 1e0: 83 e0 ldi r24, 0x03 ; 3 + 1e2: 90 e0 ldi r25, 0x00 ; 0 + 1e4: 90 93 63 00 sts 0x0063, r25 + 1e8: 80 93 62 00 sts 0x0062, r24 break; - 1e4: 06 c0 rjmp .+12 ; 0x1f2 + 1ec: 06 c0 rjmp .+12 ; 0x1fa } case SETRUN: { rf12_endasyncrx(); - 1e6: 5d d1 rcall .+698 ; 0x4a2 + 1ee: 7e d1 rcall .+764 ; 0x4ec turn(); - 1e8: 36 df rcall .-404 ; 0x56 + 1f0: 32 df rcall .-412 ; 0x56 rf12_beginasyncrx(); - 1ea: 48 d1 rcall .+656 ; 0x47c + 1f2: 69 d1 rcall .+722 ; 0x4c6 return; - 1ec: 10 c0 rjmp .+32 ; 0x20e + 1f4: 13 c0 rjmp .+38 ; 0x21c } default: { rf12_endasyncrx(); - 1ee: 59 d1 rcall .+690 ; 0x4a2 + 1f6: 7a d1 rcall .+756 ; 0x4ec return; - 1f0: 0e c0 rjmp .+28 ; 0x20e + 1f8: 11 c0 rjmp .+34 ; 0x21c } } rf12_endasyncrx(); - 1f2: 57 d1 rcall .+686 ; 0x4a2 - 1f4: 8f e3 ldi r24, 0x3F ; 63 - 1f6: 9c e9 ldi r25, 0x9C ; 156 - 1f8: 01 97 sbiw r24, 0x01 ; 1 - 1fa: f1 f7 brne .-4 ; 0x1f8 - 1fc: 00 c0 rjmp .+0 ; 0x1fe - 1fe: 00 00 nop + 1fa: 78 d1 rcall .+752 ; 0x4ec + 1fc: 2f e7 ldi r18, 0x7F ; 127 + 1fe: 88 e3 ldi r24, 0x38 ; 56 + 200: 91 e0 ldi r25, 0x01 ; 1 + 202: 21 50 subi r18, 0x01 ; 1 + 204: 80 40 sbci r24, 0x00 ; 0 + 206: 90 40 sbci r25, 0x00 ; 0 + 208: e1 f7 brne .-8 ; 0x202 + 20a: 00 c0 rjmp .+0 ; 0x20c + 20c: 00 00 nop _delay_ms(10+DEVICE); rf12_txpacket(MASTER, DEVICE, status); - 200: 40 91 62 00 lds r20, 0x0062 - 204: 50 91 63 00 lds r21, 0x0063 - 208: 6a e0 ldi r22, 0x0A ; 10 - 20a: 81 e0 ldi r24, 0x01 ; 1 - 20c: 4e d1 rcall .+668 ; 0x4aa + 20e: 40 91 62 00 lds r20, 0x0062 + 212: 50 91 63 00 lds r21, 0x0063 + 216: 68 e2 ldi r22, 0x28 ; 40 + 218: 81 e0 ldi r24, 0x01 ; 1 + 21a: 6c d1 rcall .+728 ; 0x4f4 return; } } } - 20e: cf 91 pop r28 - 210: 08 95 ret + 21c: cf 91 pop r28 + 21e: 08 95 ret -00000212 : +00000220 : // Clock value: 7,813 kHz // Mode: Normal top=0xFF // OC0A output: Disconnected // OC0B output: Disconnected // Timer Period: 21,504 ms TCCR0A = (0<: -} - -ISR(TIM0_OVF_vect) { - 222: 1f 92 push r1 - 224: 0f 92 push r0 - 226: 0f b6 in r0, 0x3f ; 63 - 228: 0f 92 push r0 - 22a: 11 24 eor r1, r1 - 22c: 2f 93 push r18 - 22e: 3f 93 push r19 - 230: 8f 93 push r24 - 232: 9f 93 push r25 - // Reinitialize Timer 0 value - TCNT0=0x58; - 234: 88 e5 ldi r24, 0x58 ; 88 - 236: 82 bf out 0x32, r24 ; 50 - - if(status == SLEEP) { - 238: 80 91 62 00 lds r24, 0x0062 - 23c: 90 91 63 00 lds r25, 0x0063 - 240: 02 97 sbiw r24, 0x02 ; 2 - 242: 79 f4 brne .+30 ; 0x262 <__vector_11+0x40> - if(pwm_led > 50) { - 244: 80 91 64 00 lds r24, 0x0064 - 248: 90 91 65 00 lds r25, 0x0065 - 24c: c3 97 sbiw r24, 0x33 ; 51 - 24e: 94 f1 brlt .+100 ; 0x2b4 <__vector_11+0x92> - PORTB ^= (1< - } - } else if(status == ACTIVE) { - 262: 80 91 62 00 lds r24, 0x0062 - 266: 90 91 63 00 lds r25, 0x0063 - 26a: 03 97 sbiw r24, 0x03 ; 3 - 26c: 79 f4 brne .+30 ; 0x28c <__vector_11+0x6a> - if(pwm_led > 5) { - 26e: 80 91 64 00 lds r24, 0x0064 - 272: 90 91 65 00 lds r25, 0x0065 - 276: 06 97 sbiw r24, 0x06 ; 6 - 278: ec f0 brlt .+58 ; 0x2b4 <__vector_11+0x92> - PORTB ^= (1< - } - } else if(status == RUN) { - 28c: 80 91 62 00 lds r24, 0x0062 - 290: 90 91 63 00 lds r25, 0x0063 - 294: 06 97 sbiw r24, 0x06 ; 6 - 296: 71 f4 brne .+28 ; 0x2b4 <__vector_11+0x92> - if(pwm_led > 1) { - 298: 80 91 64 00 lds r24, 0x0064 - 29c: 90 91 65 00 lds r25, 0x0065 - 2a0: 02 97 sbiw r24, 0x02 ; 2 - 2a2: 44 f0 brlt .+16 ; 0x2b4 <__vector_11+0x92> - PORTB ^= (1< - 2d2: 00 c0 rjmp .+0 ; 0x2d4 <__vector_11+0xb2> - 2d4: 00 00 nop + 232: 8f ea ldi r24, 0xAF ; 175 + 234: 94 e0 ldi r25, 0x04 ; 4 + 236: 01 97 sbiw r24, 0x01 ; 1 + 238: f1 f7 brne .-4 ; 0x236 + 23a: 00 c0 rjmp .+0 ; 0x23c + 23c: 00 00 nop _delay_us(LEFT); for(int i=0;i - 2e4: 80 e0 ldi r24, 0x00 ; 0 - 2e6: 90 e0 ldi r25, 0x00 ; 0 - 2e8: 25 e1 ldi r18, 0x15 ; 21 - 2ea: 2a 95 dec r18 - 2ec: f1 f7 brne .-4 ; 0x2ea <__vector_11+0xc8> - 2ee: 00 00 nop - 2f0: 01 96 adiw r24, 0x01 ; 1 - 2f2: 20 91 60 00 lds r18, 0x0060 - 2f6: 30 91 61 00 lds r19, 0x0061 - 2fa: 82 17 cp r24, r18 - 2fc: 93 07 cpc r25, r19 - 2fe: a4 f3 brlt .-24 ; 0x2e8 <__vector_11+0xc6> + 23e: 80 91 60 00 lds r24, 0x0060 + 242: 90 91 61 00 lds r25, 0x0061 + 246: 18 16 cp r1, r24 + 248: 19 06 cpc r1, r25 + 24a: 74 f4 brge .+28 ; 0x268 + 24c: 80 e0 ldi r24, 0x00 ; 0 + 24e: 90 e0 ldi r25, 0x00 ; 0 + 250: 25 e1 ldi r18, 0x15 ; 21 + 252: 2a 95 dec r18 + 254: f1 f7 brne .-4 ; 0x252 + 256: 00 00 nop + 258: 01 96 adiw r24, 0x01 ; 1 + 25a: 20 91 60 00 lds r18, 0x0060 + 25e: 30 91 61 00 lds r19, 0x0061 + 262: 82 17 cp r24, r18 + 264: 93 07 cpc r25, r19 + 266: a4 f3 brlt .-24 ; 0x250 _delay_us(STEP); } PORTB &= ~(1<: +0000026c <__vector_11>: +} + +ISR(TIM0_OVF_vect) { + 26c: 1f 92 push r1 + 26e: 0f 92 push r0 + 270: 0f b6 in r0, 0x3f ; 63 + 272: 0f 92 push r0 + 274: 11 24 eor r1, r1 + 276: 2f 93 push r18 + 278: 3f 93 push r19 + 27a: 8f 93 push r24 + 27c: 9f 93 push r25 + // Reinitialize Timer 0 value + TCNT0 = 0x58; + 27e: 88 e5 ldi r24, 0x58 ; 88 + 280: 82 bf out 0x32, r24 ; 50 + + if(status == SLEEP) { + 282: 80 91 62 00 lds r24, 0x0062 + 286: 90 91 63 00 lds r25, 0x0063 + 28a: 02 97 sbiw r24, 0x02 ; 2 + 28c: 79 f4 brne .+30 ; 0x2ac <__vector_11+0x40> + if(pwm_led > 50) { + 28e: 80 91 64 00 lds r24, 0x0064 + 292: 90 91 65 00 lds r25, 0x0065 + 296: c3 97 sbiw r24, 0x33 ; 51 + 298: 94 f1 brlt .+100 ; 0x2fe <__vector_11+0x92> + PORTB ^= (1< + } + } else if(status == ACTIVE) { + 2ac: 80 91 62 00 lds r24, 0x0062 + 2b0: 90 91 63 00 lds r25, 0x0063 + 2b4: 03 97 sbiw r24, 0x03 ; 3 + 2b6: 79 f4 brne .+30 ; 0x2d6 <__vector_11+0x6a> + if(pwm_led > 5) { + 2b8: 80 91 64 00 lds r24, 0x0064 + 2bc: 90 91 65 00 lds r25, 0x0065 + 2c0: 06 97 sbiw r24, 0x06 ; 6 + 2c2: ec f0 brlt .+58 ; 0x2fe <__vector_11+0x92> + PORTB ^= (1< + } + } else if(status == RUN) { + 2d6: 80 91 62 00 lds r24, 0x0062 + 2da: 90 91 63 00 lds r25, 0x0063 + 2de: 06 97 sbiw r24, 0x06 ; 6 + 2e0: 71 f4 brne .+28 ; 0x2fe <__vector_11+0x92> + if(pwm_led > 1) { + 2e2: 80 91 64 00 lds r24, 0x0064 + 2e6: 90 91 65 00 lds r25, 0x0065 + 2ea: 02 97 sbiw r24, 0x02 ; 2 + 2ec: 44 f0 brlt .+16 ; 0x2fe <__vector_11+0x92> + PORTB ^= (1< + 31c: 00 c0 rjmp .+0 ; 0x31e <__vector_11+0xb2> + 31e: 00 00 nop + _delay_us(LEFT); + for(int i=0;i + 32e: 80 e0 ldi r24, 0x00 ; 0 + 330: 90 e0 ldi r25, 0x00 ; 0 + 332: 25 e1 ldi r18, 0x15 ; 21 + 334: 2a 95 dec r18 + 336: f1 f7 brne .-4 ; 0x334 <__vector_11+0xc8> + 338: 00 00 nop + 33a: 01 96 adiw r24, 0x01 ; 1 + 33c: 20 91 60 00 lds r18, 0x0060 + 340: 30 91 61 00 lds r19, 0x0061 + 344: 82 17 cp r24, r18 + 346: 93 07 cpc r25, r19 + 348: a4 f3 brlt .-24 ; 0x332 <__vector_11+0xc6> + _delay_us(STEP); + } + PORTB &= ~(1<: int main(void) { rf12_init(); // ein paar Register setzen (z.B. CLK auf 10MHz) - 314: 2f d0 rcall .+94 ; 0x374 + 35e: 2f d0 rcall .+94 ; 0x3be rf12_setfreq(RF12FREQ(433.92)); // Sende/Empfangsfrequenz auf 433,92MHz einstellen - 316: 80 e2 ldi r24, 0x20 ; 32 - 318: 96 e0 ldi r25, 0x06 ; 6 - 31a: 6b d0 rcall .+214 ; 0x3f2 + 360: 80 e2 ldi r24, 0x20 ; 32 + 362: 96 e0 ldi r25, 0x06 ; 6 + 364: 6b d0 rcall .+214 ; 0x43c rf12_setbandwidth(1, 0, 7); // 400kHz Bandbreite, 0dB Verstärkung, DRSSI threshold: -61dBm - 31c: 47 e0 ldi r20, 0x07 ; 7 - 31e: 60 e0 ldi r22, 0x00 ; 0 - 320: 81 e0 ldi r24, 0x01 ; 1 - 322: 4b d0 rcall .+150 ; 0x3ba + 366: 47 e0 ldi r20, 0x07 ; 7 + 368: 60 e0 ldi r22, 0x00 ; 0 + 36a: 81 e0 ldi r24, 0x01 ; 1 + 36c: 4b d0 rcall .+150 ; 0x404 rf12_setbaud(9600); // 19200 baud - 324: 80 e8 ldi r24, 0x80 ; 128 - 326: 95 e2 ldi r25, 0x25 ; 37 - 328: 73 d0 rcall .+230 ; 0x410 + 36e: 80 e8 ldi r24, 0x80 ; 128 + 370: 95 e2 ldi r25, 0x25 ; 37 + 372: 73 d0 rcall .+230 ; 0x45a rf12_setpower(0, 6); // 1mW Ausgangsleistung, 120kHz Frequenzshift - 32a: 66 e0 ldi r22, 0x06 ; 6 - 32c: 80 e0 ldi r24, 0x00 ; 0 - 32e: 93 d0 rcall .+294 ; 0x456 + 374: 66 e0 ldi r22, 0x06 ; 6 + 376: 80 e0 ldi r24, 0x00 ; 0 + 378: 93 d0 rcall .+294 ; 0x4a0 init_timer(); - 330: 70 df rcall .-288 ; 0x212 + 37a: 52 df rcall .-348 ; 0x220 DDRB |= (1< - 340: fe cf rjmp .-4 ; 0x33e + 388: fb de rcall .-522 ; 0x180 + 38a: fe cf rjmp .-4 ; 0x388 -00000342 : +0000038c : unsigned short rf12_trans(unsigned short wert) { unsigned short werti = 0; unsigned char i; RF_PORT &= ~(1< unsigned short rf12_trans(unsigned short wert) { unsigned short werti = 0; - 346: 20 e0 ldi r18, 0x00 ; 0 - 348: 30 e0 ldi r19, 0x00 ; 0 + 390: 20 e0 ldi r18, 0x00 ; 0 + 392: 30 e0 ldi r19, 0x00 ; 0 unsigned char i; RF_PORT &= ~(1< + 394: 99 23 and r25, r25 + 396: 14 f4 brge .+4 ; 0x39c RF_PORT |= (1< + 398: db 9a sbi 0x1b, 3 ; 27 + 39a: 01 c0 rjmp .+2 ; 0x39e } else { RF_PORT &= ~(1< - 364: 00 00 nop + 3a8: 88 0f add r24, r24 + 3aa: 99 1f adc r25, r25 + 3ac: 00 c0 rjmp .+0 ; 0x3ae + 3ae: 00 00 nop _delay_us(0.3); RF_PORT &= ~(1< + 3b4: 79 f7 brne .-34 ; 0x394 RF_PORT |= (1<: +000003be : void rf12_init(void) { RF_DDR |= (1< - 38a: 00 c0 rjmp .+0 ; 0x38c - 38c: 00 00 nop + 3c6: 2f ef ldi r18, 0xFF ; 255 + 3c8: 80 e7 ldi r24, 0x70 ; 112 + 3ca: 92 e0 ldi r25, 0x02 ; 2 + 3cc: 21 50 subi r18, 0x01 ; 1 + 3ce: 80 40 sbci r24, 0x00 ; 0 + 3d0: 90 40 sbci r25, 0x00 ; 0 + 3d2: e1 f7 brne .-8 ; 0x3cc + 3d4: 00 c0 rjmp .+0 ; 0x3d6 + 3d6: 00 00 nop _delay_ms(100); rf12_trans(0xC0E0); // AVR CLK: 10MHz - 38e: 80 ee ldi r24, 0xE0 ; 224 - 390: 90 ec ldi r25, 0xC0 ; 192 - 392: d7 df rcall .-82 ; 0x342 + 3d8: 80 ee ldi r24, 0xE0 ; 224 + 3da: 90 ec ldi r25, 0xC0 ; 192 + 3dc: d7 df rcall .-82 ; 0x38c rf12_trans(0x80D7); // Enable FIFO - 394: 87 ed ldi r24, 0xD7 ; 215 - 396: 90 e8 ldi r25, 0x80 ; 128 - 398: d4 df rcall .-88 ; 0x342 + 3de: 87 ed ldi r24, 0xD7 ; 215 + 3e0: 90 e8 ldi r25, 0x80 ; 128 + 3e2: d4 df rcall .-88 ; 0x38c rf12_trans(0xC2AB); // Data Filter: internal - 39a: 8b ea ldi r24, 0xAB ; 171 - 39c: 92 ec ldi r25, 0xC2 ; 194 - 39e: d1 df rcall .-94 ; 0x342 + 3e4: 8b ea ldi r24, 0xAB ; 171 + 3e6: 92 ec ldi r25, 0xC2 ; 194 + 3e8: d1 df rcall .-94 ; 0x38c rf12_trans(0xCA81); // Set FIFO mode - 3a0: 81 e8 ldi r24, 0x81 ; 129 - 3a2: 9a ec ldi r25, 0xCA ; 202 - 3a4: ce df rcall .-100 ; 0x342 + 3ea: 81 e8 ldi r24, 0x81 ; 129 + 3ec: 9a ec ldi r25, 0xCA ; 202 + 3ee: ce df rcall .-100 ; 0x38c rf12_trans(0xE000); // disable wakeuptimer - 3a6: 80 e0 ldi r24, 0x00 ; 0 - 3a8: 90 ee ldi r25, 0xE0 ; 224 - 3aa: cb df rcall .-106 ; 0x342 + 3f0: 80 e0 ldi r24, 0x00 ; 0 + 3f2: 90 ee ldi r25, 0xE0 ; 224 + 3f4: cb df rcall .-106 ; 0x38c rf12_trans(0xC800); // disable low duty cycle - 3ac: 80 e0 ldi r24, 0x00 ; 0 - 3ae: 98 ec ldi r25, 0xC8 ; 200 - 3b0: c8 df rcall .-112 ; 0x342 + 3f6: 80 e0 ldi r24, 0x00 ; 0 + 3f8: 98 ec ldi r25, 0xC8 ; 200 + 3fa: c8 df rcall .-112 ; 0x38c rf12_trans(0xC4F7); // AFC settings: autotuning: -10kHz...+7,5kHz - 3b2: 87 ef ldi r24, 0xF7 ; 247 - 3b4: 94 ec ldi r25, 0xC4 ; 196 - 3b6: c5 df rcall .-118 ; 0x342 - 3b8: 08 95 ret + 3fc: 87 ef ldi r24, 0xF7 ; 247 + 3fe: 94 ec ldi r25, 0xC4 ; 196 + 400: c5 df rcall .-118 ; 0x38c + 402: 08 95 ret -000003ba : +00000404 : } void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi) { rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7)); - 3ba: 47 70 andi r20, 0x07 ; 7 - 3bc: 50 e0 ldi r21, 0x00 ; 0 - 3be: 54 69 ori r21, 0x94 ; 148 - 3c0: 63 70 andi r22, 0x03 ; 3 - 3c2: 26 2f mov r18, r22 - 3c4: 30 e0 ldi r19, 0x00 ; 0 - 3c6: 22 0f add r18, r18 - 3c8: 33 1f adc r19, r19 - 3ca: 22 0f add r18, r18 - 3cc: 33 1f adc r19, r19 - 3ce: 22 0f add r18, r18 - 3d0: 33 1f adc r19, r19 - 3d2: 90 e0 ldi r25, 0x00 ; 0 - 3d4: 88 0f add r24, r24 - 3d6: 99 1f adc r25, r25 - 3d8: 82 95 swap r24 - 3da: 92 95 swap r25 - 3dc: 90 7f andi r25, 0xF0 ; 240 - 3de: 98 27 eor r25, r24 - 3e0: 80 7f andi r24, 0xF0 ; 240 - 3e2: 98 27 eor r25, r24 - 3e4: 99 27 eor r25, r25 - 3e6: 82 2b or r24, r18 - 3e8: 93 2b or r25, r19 - 3ea: 84 2b or r24, r20 - 3ec: 95 2b or r25, r21 - 3ee: a9 df rcall .-174 ; 0x342 - 3f0: 08 95 ret + 404: 47 70 andi r20, 0x07 ; 7 + 406: 50 e0 ldi r21, 0x00 ; 0 + 408: 54 69 ori r21, 0x94 ; 148 + 40a: 63 70 andi r22, 0x03 ; 3 + 40c: 26 2f mov r18, r22 + 40e: 30 e0 ldi r19, 0x00 ; 0 + 410: 22 0f add r18, r18 + 412: 33 1f adc r19, r19 + 414: 22 0f add r18, r18 + 416: 33 1f adc r19, r19 + 418: 22 0f add r18, r18 + 41a: 33 1f adc r19, r19 + 41c: 90 e0 ldi r25, 0x00 ; 0 + 41e: 88 0f add r24, r24 + 420: 99 1f adc r25, r25 + 422: 82 95 swap r24 + 424: 92 95 swap r25 + 426: 90 7f andi r25, 0xF0 ; 240 + 428: 98 27 eor r25, r24 + 42a: 80 7f andi r24, 0xF0 ; 240 + 42c: 98 27 eor r25, r24 + 42e: 99 27 eor r25, r25 + 430: 82 2b or r24, r18 + 432: 93 2b or r25, r19 + 434: 84 2b or r24, r20 + 436: 95 2b or r25, r21 + 438: a9 df rcall .-174 ; 0x38c + 43a: 08 95 ret -000003f2 : +0000043c : } void rf12_setfreq(unsigned short freq) { if (freq<96) { // 430,2400MHz - 3f2: 80 36 cpi r24, 0x60 ; 96 - 3f4: 91 05 cpc r25, r1 - 3f6: 38 f0 brcs .+14 ; 0x406 - 3f8: 80 34 cpi r24, 0x40 ; 64 - 3fa: 2f e0 ldi r18, 0x0F ; 15 - 3fc: 92 07 cpc r25, r18 - 3fe: 28 f0 brcs .+10 ; 0x40a - 400: 8f e3 ldi r24, 0x3F ; 63 - 402: 9f e0 ldi r25, 0x0F ; 15 - 404: 02 c0 rjmp .+4 ; 0x40a + 43c: 80 36 cpi r24, 0x60 ; 96 + 43e: 91 05 cpc r25, r1 + 440: 38 f0 brcs .+14 ; 0x450 + 442: 80 34 cpi r24, 0x40 ; 64 + 444: 2f e0 ldi r18, 0x0F ; 15 + 446: 92 07 cpc r25, r18 + 448: 28 f0 brcs .+10 ; 0x454 + 44a: 8f e3 ldi r24, 0x3F ; 63 + 44c: 9f e0 ldi r25, 0x0F ; 15 + 44e: 02 c0 rjmp .+4 ; 0x454 freq=96; - 406: 80 e6 ldi r24, 0x60 ; 96 - 408: 90 e0 ldi r25, 0x00 ; 0 + 450: 80 e6 ldi r24, 0x60 ; 96 + 452: 90 e0 ldi r25, 0x00 ; 0 } else if (freq>3903) { // 439,7575MHz freq=3903; } rf12_trans(0xA000|freq); - 40a: 90 6a ori r25, 0xA0 ; 160 - 40c: 9a df rcall .-204 ; 0x342 - 40e: 08 95 ret + 454: 90 6a ori r25, 0xA0 ; 160 + 456: 9a df rcall .-204 ; 0x38c + 458: 08 95 ret -00000410 : +0000045a : } void rf12_setbaud(unsigned short baud) { if (baud<663) { - 410: 87 39 cpi r24, 0x97 ; 151 - 412: 22 e0 ldi r18, 0x02 ; 2 - 414: 92 07 cpc r25, r18 - 416: f0 f0 brcs .+60 ; 0x454 + 45a: 87 39 cpi r24, 0x97 ; 151 + 45c: 22 e0 ldi r18, 0x02 ; 2 + 45e: 92 07 cpc r25, r18 + 460: f0 f0 brcs .+60 ; 0x49e return; } if (baud<5400) { // Baudrate= 344827,58621/(R+1)/(1+CS*7) - 418: 88 31 cpi r24, 0x18 ; 24 - 41a: 25 e1 ldi r18, 0x15 ; 21 - 41c: 92 07 cpc r25, r18 - 41e: 70 f4 brcc .+28 ; 0x43c + 462: 88 31 cpi r24, 0x18 ; 24 + 464: 25 e1 ldi r18, 0x15 ; 21 + 466: 92 07 cpc r25, r18 + 468: 70 f4 brcc .+28 ; 0x486 rf12_trans(0xC680|((43104/baud)-1)); - 420: 9c 01 movw r18, r24 - 422: 40 e0 ldi r20, 0x00 ; 0 - 424: 50 e0 ldi r21, 0x00 ; 0 - 426: 60 e6 ldi r22, 0x60 ; 96 - 428: 78 ea ldi r23, 0xA8 ; 168 - 42a: 80 e0 ldi r24, 0x00 ; 0 - 42c: 90 e0 ldi r25, 0x00 ; 0 - 42e: a0 d0 rcall .+320 ; 0x570 <__divmodsi4> - 430: c9 01 movw r24, r18 - 432: 01 97 sbiw r24, 0x01 ; 1 - 434: 80 68 ori r24, 0x80 ; 128 - 436: 96 6c ori r25, 0xC6 ; 198 - 438: 84 df rcall .-248 ; 0x342 - 43a: 08 95 ret + 46a: 9c 01 movw r18, r24 + 46c: 40 e0 ldi r20, 0x00 ; 0 + 46e: 50 e0 ldi r21, 0x00 ; 0 + 470: 60 e6 ldi r22, 0x60 ; 96 + 472: 78 ea ldi r23, 0xA8 ; 168 + 474: 80 e0 ldi r24, 0x00 ; 0 + 476: 90 e0 ldi r25, 0x00 ; 0 + 478: a0 d0 rcall .+320 ; 0x5ba <__divmodsi4> + 47a: c9 01 movw r24, r18 + 47c: 01 97 sbiw r24, 0x01 ; 1 + 47e: 80 68 ori r24, 0x80 ; 128 + 480: 96 6c ori r25, 0xC6 ; 198 + 482: 84 df rcall .-248 ; 0x38c + 484: 08 95 ret } else { rf12_trans(0xC600|((344828UL/baud)-1)); - 43c: 9c 01 movw r18, r24 - 43e: 40 e0 ldi r20, 0x00 ; 0 - 440: 50 e0 ldi r21, 0x00 ; 0 - 442: 6c ef ldi r22, 0xFC ; 252 - 444: 72 e4 ldi r23, 0x42 ; 66 - 446: 85 e0 ldi r24, 0x05 ; 5 - 448: 90 e0 ldi r25, 0x00 ; 0 - 44a: 70 d0 rcall .+224 ; 0x52c <__udivmodsi4> - 44c: c9 01 movw r24, r18 - 44e: 01 97 sbiw r24, 0x01 ; 1 - 450: 96 6c ori r25, 0xC6 ; 198 - 452: 77 df rcall .-274 ; 0x342 - 454: 08 95 ret + 486: 9c 01 movw r18, r24 + 488: 40 e0 ldi r20, 0x00 ; 0 + 48a: 50 e0 ldi r21, 0x00 ; 0 + 48c: 6c ef ldi r22, 0xFC ; 252 + 48e: 72 e4 ldi r23, 0x42 ; 66 + 490: 85 e0 ldi r24, 0x05 ; 5 + 492: 90 e0 ldi r25, 0x00 ; 0 + 494: 70 d0 rcall .+224 ; 0x576 <__udivmodsi4> + 496: c9 01 movw r24, r18 + 498: 01 97 sbiw r24, 0x01 ; 1 + 49a: 96 6c ori r25, 0xC6 ; 198 + 49c: 77 df rcall .-274 ; 0x38c + 49e: 08 95 ret -00000456 : +000004a0 : } } void rf12_setpower(unsigned char power, unsigned char mod) { rf12_trans(0x9800|(power&7)|((mod&15)<<4)); - 456: 87 70 andi r24, 0x07 ; 7 - 458: 90 e0 ldi r25, 0x00 ; 0 - 45a: 98 69 ori r25, 0x98 ; 152 - 45c: 70 e0 ldi r23, 0x00 ; 0 - 45e: 62 95 swap r22 - 460: 72 95 swap r23 - 462: 70 7f andi r23, 0xF0 ; 240 - 464: 76 27 eor r23, r22 - 466: 60 7f andi r22, 0xF0 ; 240 - 468: 76 27 eor r23, r22 - 46a: 77 27 eor r23, r23 - 46c: 86 2b or r24, r22 - 46e: 97 2b or r25, r23 - 470: 68 df rcall .-304 ; 0x342 - 472: 08 95 ret + 4a0: 87 70 andi r24, 0x07 ; 7 + 4a2: 90 e0 ldi r25, 0x00 ; 0 + 4a4: 98 69 ori r25, 0x98 ; 152 + 4a6: 70 e0 ldi r23, 0x00 ; 0 + 4a8: 62 95 swap r22 + 4aa: 72 95 swap r23 + 4ac: 70 7f andi r23, 0xF0 ; 240 + 4ae: 76 27 eor r23, r22 + 4b0: 60 7f andi r22, 0xF0 ; 240 + 4b2: 76 27 eor r23, r22 + 4b4: 77 27 eor r23, r23 + 4b6: 86 2b or r24, r22 + 4b8: 97 2b or r25, r23 + 4ba: 68 df rcall .-304 ; 0x38c + 4bc: 08 95 ret -00000474 : +000004be : } void rf12_ready(void) { RF_PORT &= ~(1< + 4c0: c8 9b sbis 0x19, 0 ; 25 + 4c2: fe cf rjmp .-4 ; 0x4c0 } - 47a: 08 95 ret + 4c4: 08 95 ret -0000047c : +000004c6 : void rf12_beginasyncrx() { rf12_trans(0x82C8); // RX on - 47c: 88 ec ldi r24, 0xC8 ; 200 - 47e: 92 e8 ldi r25, 0x82 ; 130 - 480: 60 df rcall .-320 ; 0x342 + 4c6: 88 ec ldi r24, 0xC8 ; 200 + 4c8: 92 e8 ldi r25, 0x82 ; 130 + 4ca: 60 df rcall .-320 ; 0x38c rf12_trans(0xCA81); // set FIFO mode - 482: 81 e8 ldi r24, 0x81 ; 129 - 484: 9a ec ldi r25, 0xCA ; 202 - 486: 5d df rcall .-326 ; 0x342 + 4cc: 81 e8 ldi r24, 0x81 ; 129 + 4ce: 9a ec ldi r25, 0xCA ; 202 + 4d0: 5d df rcall .-326 ; 0x38c rf12_trans(0xCA83); // enable FIFO - 488: 83 e8 ldi r24, 0x83 ; 131 - 48a: 9a ec ldi r25, 0xCA ; 202 - 48c: 5a df rcall .-332 ; 0x342 - 48e: 08 95 ret + 4d2: 83 e8 ldi r24, 0x83 ; 131 + 4d4: 9a ec ldi r25, 0xCA ; 202 + 4d6: 5a df rcall .-332 ; 0x38c + 4d8: 08 95 ret -00000490 : +000004da : } uint8_t rf12_hasdata() { RF_PORT &= ~(1<: +000004e4 : uint8_t rf12_rxbyte() { return rf12_trans(0xB000); - 49a: 80 e0 ldi r24, 0x00 ; 0 - 49c: 90 eb ldi r25, 0xB0 ; 176 - 49e: 51 df rcall .-350 ; 0x342 + 4e4: 80 e0 ldi r24, 0x00 ; 0 + 4e6: 90 eb ldi r25, 0xB0 ; 176 + 4e8: 51 df rcall .-350 ; 0x38c } - 4a0: 08 95 ret + 4ea: 08 95 ret -000004a2 : +000004ec : void rf12_endasyncrx() { rf12_trans(0x8208); // RX off - 4a2: 88 e0 ldi r24, 0x08 ; 8 - 4a4: 92 e8 ldi r25, 0x82 ; 130 - 4a6: 4d df rcall .-358 ; 0x342 - 4a8: 08 95 ret + 4ec: 88 e0 ldi r24, 0x08 ; 8 + 4ee: 92 e8 ldi r25, 0x82 ; 130 + 4f0: 4d df rcall .-358 ; 0x38c + 4f2: 08 95 ret -000004aa : +000004f4 : *data++=rf12_trans(0xB000); } rf12_trans(0x8208); // RX off } void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) { - 4aa: 1f 93 push r17 - 4ac: cf 93 push r28 - 4ae: df 93 push r29 - 4b0: 18 2f mov r17, r24 - 4b2: d6 2f mov r29, r22 - 4b4: c4 2f mov r28, r20 + 4f4: 1f 93 push r17 + 4f6: cf 93 push r28 + 4f8: df 93 push r29 + 4fa: 18 2f mov r17, r24 + 4fc: d6 2f mov r29, r22 + 4fe: c4 2f mov r28, r20 rf12_trans(0x8238); // TX on - 4b6: 88 e3 ldi r24, 0x38 ; 56 - 4b8: 92 e8 ldi r25, 0x82 ; 130 - 4ba: 43 df rcall .-378 ; 0x342 + 500: 88 e3 ldi r24, 0x38 ; 56 + 502: 92 e8 ldi r25, 0x82 ; 130 + 504: 43 df rcall .-378 ; 0x38c rf12_ready(); - 4bc: db df rcall .-74 ; 0x474 + 506: db df rcall .-74 ; 0x4be rf12_trans(0xB8AA); - 4be: 8a ea ldi r24, 0xAA ; 170 - 4c0: 98 eb ldi r25, 0xB8 ; 184 - 4c2: 3f df rcall .-386 ; 0x342 + 508: 8a ea ldi r24, 0xAA ; 170 + 50a: 98 eb ldi r25, 0xB8 ; 184 + 50c: 3f df rcall .-386 ; 0x38c rf12_ready(); - 4c4: d7 df rcall .-82 ; 0x474 + 50e: d7 df rcall .-82 ; 0x4be rf12_trans(0xB8AA); - 4c6: 8a ea ldi r24, 0xAA ; 170 - 4c8: 98 eb ldi r25, 0xB8 ; 184 - 4ca: 3b df rcall .-394 ; 0x342 + 510: 8a ea ldi r24, 0xAA ; 170 + 512: 98 eb ldi r25, 0xB8 ; 184 + 514: 3b df rcall .-394 ; 0x38c rf12_ready(); - 4cc: d3 df rcall .-90 ; 0x474 + 516: d3 df rcall .-90 ; 0x4be rf12_trans(0xB8AA); - 4ce: 8a ea ldi r24, 0xAA ; 170 - 4d0: 98 eb ldi r25, 0xB8 ; 184 - 4d2: 37 df rcall .-402 ; 0x342 + 518: 8a ea ldi r24, 0xAA ; 170 + 51a: 98 eb ldi r25, 0xB8 ; 184 + 51c: 37 df rcall .-402 ; 0x38c rf12_ready(); - 4d4: cf df rcall .-98 ; 0x474 + 51e: cf df rcall .-98 ; 0x4be rf12_trans(0xB82D); - 4d6: 8d e2 ldi r24, 0x2D ; 45 - 4d8: 98 eb ldi r25, 0xB8 ; 184 - 4da: 33 df rcall .-410 ; 0x342 + 520: 8d e2 ldi r24, 0x2D ; 45 + 522: 98 eb ldi r25, 0xB8 ; 184 + 524: 33 df rcall .-410 ; 0x38c rf12_ready(); - 4dc: cb df rcall .-106 ; 0x474 + 526: cb df rcall .-106 ; 0x4be rf12_trans(0xB8D4); - 4de: 84 ed ldi r24, 0xD4 ; 212 - 4e0: 98 eb ldi r25, 0xB8 ; 184 - 4e2: 2f df rcall .-418 ; 0x342 + 528: 84 ed ldi r24, 0xD4 ; 212 + 52a: 98 eb ldi r25, 0xB8 ; 184 + 52c: 2f df rcall .-418 ; 0x38c rf12_ready(); - 4e4: c7 df rcall .-114 ; 0x474 + 52e: c7 df rcall .-114 ; 0x4be rf12_trans(0xB800|addr); - 4e6: 81 2f mov r24, r17 - 4e8: 90 e0 ldi r25, 0x00 ; 0 - 4ea: 98 6b ori r25, 0xB8 ; 184 - 4ec: 2a df rcall .-428 ; 0x342 + 530: 81 2f mov r24, r17 + 532: 90 e0 ldi r25, 0x00 ; 0 + 534: 98 6b ori r25, 0xB8 ; 184 + 536: 2a df rcall .-428 ; 0x38c rf12_ready(); - 4ee: c2 df rcall .-124 ; 0x474 + 538: c2 df rcall .-124 ; 0x4be rf12_trans(0xB800|from); - 4f0: 8d 2f mov r24, r29 - 4f2: 90 e0 ldi r25, 0x00 ; 0 - 4f4: 98 6b ori r25, 0xB8 ; 184 - 4f6: 25 df rcall .-438 ; 0x342 + 53a: 8d 2f mov r24, r29 + 53c: 90 e0 ldi r25, 0x00 ; 0 + 53e: 98 6b ori r25, 0xB8 ; 184 + 540: 25 df rcall .-438 ; 0x38c rf12_ready(); - 4f8: bd df rcall .-134 ; 0x474 + 542: bd df rcall .-134 ; 0x4be rf12_trans(0xB800|data); - 4fa: 8c 2f mov r24, r28 - 4fc: 90 e0 ldi r25, 0x00 ; 0 - 4fe: 98 6b ori r25, 0xB8 ; 184 - 500: 20 df rcall .-448 ; 0x342 + 544: 8c 2f mov r24, r28 + 546: 90 e0 ldi r25, 0x00 ; 0 + 548: 98 6b ori r25, 0xB8 ; 184 + 54a: 20 df rcall .-448 ; 0x38c rf12_ready(); - 502: b8 df rcall .-144 ; 0x474 + 54c: b8 df rcall .-144 ; 0x4be rf12_trans(0xB800); - 504: 80 e0 ldi r24, 0x00 ; 0 - 506: 98 eb ldi r25, 0xB8 ; 184 - 508: 1c df rcall .-456 ; 0x342 + 54e: 80 e0 ldi r24, 0x00 ; 0 + 550: 98 eb ldi r25, 0xB8 ; 184 + 552: 1c df rcall .-456 ; 0x38c rf12_ready(); - 50a: b4 df rcall .-152 ; 0x474 + 554: b4 df rcall .-152 ; 0x4be rf12_trans(0x8208); // TX off - 50c: 88 e0 ldi r24, 0x08 ; 8 - 50e: 92 e8 ldi r25, 0x82 ; 130 - 510: 18 df rcall .-464 ; 0x342 - 512: 2f ef ldi r18, 0xFF ; 255 - 514: 80 e7 ldi r24, 0x70 ; 112 - 516: 92 e0 ldi r25, 0x02 ; 2 - 518: 21 50 subi r18, 0x01 ; 1 - 51a: 80 40 sbci r24, 0x00 ; 0 - 51c: 90 40 sbci r25, 0x00 ; 0 - 51e: e1 f7 brne .-8 ; 0x518 - 520: 00 c0 rjmp .+0 ; 0x522 - 522: 00 00 nop + 556: 88 e0 ldi r24, 0x08 ; 8 + 558: 92 e8 ldi r25, 0x82 ; 130 + 55a: 18 df rcall .-464 ; 0x38c + 55c: 2f ef ldi r18, 0xFF ; 255 + 55e: 80 e7 ldi r24, 0x70 ; 112 + 560: 92 e0 ldi r25, 0x02 ; 2 + 562: 21 50 subi r18, 0x01 ; 1 + 564: 80 40 sbci r24, 0x00 ; 0 + 566: 90 40 sbci r25, 0x00 ; 0 + 568: e1 f7 brne .-8 ; 0x562 + 56a: 00 c0 rjmp .+0 ; 0x56c + 56c: 00 00 nop _delay_ms(100); - 524: df 91 pop r29 - 526: cf 91 pop r28 - 528: 1f 91 pop r17 - 52a: 08 95 ret + 56e: df 91 pop r29 + 570: cf 91 pop r28 + 572: 1f 91 pop r17 + 574: 08 95 ret -0000052c <__udivmodsi4>: - 52c: a1 e2 ldi r26, 0x21 ; 33 - 52e: 1a 2e mov r1, r26 - 530: aa 1b sub r26, r26 - 532: bb 1b sub r27, r27 - 534: fd 01 movw r30, r26 - 536: 0d c0 rjmp .+26 ; 0x552 <__udivmodsi4_ep> +00000576 <__udivmodsi4>: + 576: a1 e2 ldi r26, 0x21 ; 33 + 578: 1a 2e mov r1, r26 + 57a: aa 1b sub r26, r26 + 57c: bb 1b sub r27, r27 + 57e: fd 01 movw r30, r26 + 580: 0d c0 rjmp .+26 ; 0x59c <__udivmodsi4_ep> -00000538 <__udivmodsi4_loop>: - 538: aa 1f adc r26, r26 - 53a: bb 1f adc r27, r27 - 53c: ee 1f adc r30, r30 - 53e: ff 1f adc r31, r31 - 540: a2 17 cp r26, r18 - 542: b3 07 cpc r27, r19 - 544: e4 07 cpc r30, r20 - 546: f5 07 cpc r31, r21 - 548: 20 f0 brcs .+8 ; 0x552 <__udivmodsi4_ep> - 54a: a2 1b sub r26, r18 - 54c: b3 0b sbc r27, r19 - 54e: e4 0b sbc r30, r20 - 550: f5 0b sbc r31, r21 +00000582 <__udivmodsi4_loop>: + 582: aa 1f adc r26, r26 + 584: bb 1f adc r27, r27 + 586: ee 1f adc r30, r30 + 588: ff 1f adc r31, r31 + 58a: a2 17 cp r26, r18 + 58c: b3 07 cpc r27, r19 + 58e: e4 07 cpc r30, r20 + 590: f5 07 cpc r31, r21 + 592: 20 f0 brcs .+8 ; 0x59c <__udivmodsi4_ep> + 594: a2 1b sub r26, r18 + 596: b3 0b sbc r27, r19 + 598: e4 0b sbc r30, r20 + 59a: f5 0b sbc r31, r21 -00000552 <__udivmodsi4_ep>: - 552: 66 1f adc r22, r22 - 554: 77 1f adc r23, r23 - 556: 88 1f adc r24, r24 - 558: 99 1f adc r25, r25 - 55a: 1a 94 dec r1 - 55c: 69 f7 brne .-38 ; 0x538 <__udivmodsi4_loop> - 55e: 60 95 com r22 - 560: 70 95 com r23 - 562: 80 95 com r24 - 564: 90 95 com r25 - 566: 9b 01 movw r18, r22 - 568: ac 01 movw r20, r24 - 56a: bd 01 movw r22, r26 - 56c: cf 01 movw r24, r30 - 56e: 08 95 ret +0000059c <__udivmodsi4_ep>: + 59c: 66 1f adc r22, r22 + 59e: 77 1f adc r23, r23 + 5a0: 88 1f adc r24, r24 + 5a2: 99 1f adc r25, r25 + 5a4: 1a 94 dec r1 + 5a6: 69 f7 brne .-38 ; 0x582 <__udivmodsi4_loop> + 5a8: 60 95 com r22 + 5aa: 70 95 com r23 + 5ac: 80 95 com r24 + 5ae: 90 95 com r25 + 5b0: 9b 01 movw r18, r22 + 5b2: ac 01 movw r20, r24 + 5b4: bd 01 movw r22, r26 + 5b6: cf 01 movw r24, r30 + 5b8: 08 95 ret -00000570 <__divmodsi4>: - 570: 05 2e mov r0, r21 - 572: 97 fb bst r25, 7 - 574: 16 f4 brtc .+4 ; 0x57a <__divmodsi4+0xa> - 576: 00 94 com r0 - 578: 06 d0 rcall .+12 ; 0x586 <__divmodsi4_neg1> - 57a: 57 fd sbrc r21, 7 - 57c: 0c d0 rcall .+24 ; 0x596 <__divmodsi4_neg2> - 57e: d6 df rcall .-84 ; 0x52c <__udivmodsi4> - 580: 07 fc sbrc r0, 7 - 582: 09 d0 rcall .+18 ; 0x596 <__divmodsi4_neg2> - 584: 7e f4 brtc .+30 ; 0x5a4 <__divmodsi4_exit> +000005ba <__divmodsi4>: + 5ba: 05 2e mov r0, r21 + 5bc: 97 fb bst r25, 7 + 5be: 16 f4 brtc .+4 ; 0x5c4 <__divmodsi4+0xa> + 5c0: 00 94 com r0 + 5c2: 06 d0 rcall .+12 ; 0x5d0 <__divmodsi4_neg1> + 5c4: 57 fd sbrc r21, 7 + 5c6: 0c d0 rcall .+24 ; 0x5e0 <__divmodsi4_neg2> + 5c8: d6 df rcall .-84 ; 0x576 <__udivmodsi4> + 5ca: 07 fc sbrc r0, 7 + 5cc: 09 d0 rcall .+18 ; 0x5e0 <__divmodsi4_neg2> + 5ce: 7e f4 brtc .+30 ; 0x5ee <__divmodsi4_exit> -00000586 <__divmodsi4_neg1>: - 586: 90 95 com r25 - 588: 80 95 com r24 - 58a: 70 95 com r23 - 58c: 61 95 neg r22 - 58e: 7f 4f sbci r23, 0xFF ; 255 - 590: 8f 4f sbci r24, 0xFF ; 255 - 592: 9f 4f sbci r25, 0xFF ; 255 - 594: 08 95 ret +000005d0 <__divmodsi4_neg1>: + 5d0: 90 95 com r25 + 5d2: 80 95 com r24 + 5d4: 70 95 com r23 + 5d6: 61 95 neg r22 + 5d8: 7f 4f sbci r23, 0xFF ; 255 + 5da: 8f 4f sbci r24, 0xFF ; 255 + 5dc: 9f 4f sbci r25, 0xFF ; 255 + 5de: 08 95 ret -00000596 <__divmodsi4_neg2>: - 596: 50 95 com r21 - 598: 40 95 com r20 - 59a: 30 95 com r19 - 59c: 21 95 neg r18 - 59e: 3f 4f sbci r19, 0xFF ; 255 - 5a0: 4f 4f sbci r20, 0xFF ; 255 - 5a2: 5f 4f sbci r21, 0xFF ; 255 +000005e0 <__divmodsi4_neg2>: + 5e0: 50 95 com r21 + 5e2: 40 95 com r20 + 5e4: 30 95 com r19 + 5e6: 21 95 neg r18 + 5e8: 3f 4f sbci r19, 0xFF ; 255 + 5ea: 4f 4f sbci r20, 0xFF ; 255 + 5ec: 5f 4f sbci r21, 0xFF ; 255 -000005a4 <__divmodsi4_exit>: - 5a4: 08 95 ret +000005ee <__divmodsi4_exit>: + 5ee: 08 95 ret -000005a6 <_exit>: - 5a6: f8 94 cli +000005f0 <_exit>: + 5f0: f8 94 cli -000005a8 <__stop_program>: - 5a8: ff cf rjmp .-2 ; 0x5a8 <__stop_program> +000005f2 <__stop_program>: + 5f2: ff cf rjmp .-2 ; 0x5f2 <__stop_program> diff --git a/V5B/Reciver/Reciver/Debug/Reciver.map b/V5B/Reciver/Reciver/Debug/Reciver.map index 8dddce0..ca0b574 100644 --- a/V5B/Reciver/Reciver/Debug/Reciver.map +++ b/V5B/Reciver/Reciver/Debug/Reciver.map @@ -197,7 +197,7 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 .rela.plt *(.rela.plt) -.text 0x00000000 0x5aa +.text 0x00000000 0x5f4 *(.vectors) .vectors 0x00000000 0x22 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/../../../../avr/lib/avr25/tiny-stack/crttn24a.o 0x00000000 __vector_default @@ -271,67 +271,67 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 0x00000054 __vector_16 0x00000056 . = ALIGN (0x2) *(.text.*) - .text.turn 0x00000056 0x90 Reciver.o + .text.turn 0x00000056 0x96 Reciver.o 0x00000056 turn - .text.poll 0x000000e6 0x94 Reciver.o - 0x000000e6 poll - .text.recive 0x0000017a 0x98 Reciver.o - 0x0000017a recive + .text.poll 0x000000ec 0x94 Reciver.o + 0x000000ec poll + .text.recive 0x00000180 0xa0 Reciver.o + 0x00000180 recive .text.init_timer - 0x00000212 0x10 Reciver.o - 0x00000212 init_timer + 0x00000220 0x4c Reciver.o + 0x00000220 init_timer .text.__vector_11 - 0x00000222 0xf2 Reciver.o - 0x00000222 __vector_11 - .text.main 0x00000314 0x2e Reciver.o - 0x00000314 main + 0x0000026c 0xf2 Reciver.o + 0x0000026c __vector_11 + .text.main 0x0000035e 0x2e Reciver.o + 0x0000035e main .text.rf12_trans - 0x00000342 0x32 rf12.o - 0x00000342 rf12_trans + 0x0000038c 0x32 rf12.o + 0x0000038c rf12_trans .text.rf12_init - 0x00000374 0x46 rf12.o - 0x00000374 rf12_init + 0x000003be 0x46 rf12.o + 0x000003be rf12_init .text.rf12_setbandwidth - 0x000003ba 0x38 rf12.o - 0x000003ba rf12_setbandwidth + 0x00000404 0x38 rf12.o + 0x00000404 rf12_setbandwidth .text.rf12_setfreq - 0x000003f2 0x1e rf12.o - 0x000003f2 rf12_setfreq + 0x0000043c 0x1e rf12.o + 0x0000043c rf12_setfreq .text.rf12_setbaud - 0x00000410 0x46 rf12.o - 0x00000410 rf12_setbaud + 0x0000045a 0x46 rf12.o + 0x0000045a rf12_setbaud .text.rf12_setpower - 0x00000456 0x1e rf12.o - 0x00000456 rf12_setpower + 0x000004a0 0x1e rf12.o + 0x000004a0 rf12_setpower .text.rf12_ready - 0x00000474 0x8 rf12.o - 0x00000474 rf12_ready + 0x000004be 0x8 rf12.o + 0x000004be rf12_ready .text.rf12_beginasyncrx - 0x0000047c 0x14 rf12.o - 0x0000047c rf12_beginasyncrx + 0x000004c6 0x14 rf12.o + 0x000004c6 rf12_beginasyncrx .text.rf12_hasdata - 0x00000490 0xa rf12.o - 0x00000490 rf12_hasdata + 0x000004da 0xa rf12.o + 0x000004da rf12_hasdata .text.rf12_rxbyte - 0x0000049a 0x8 rf12.o - 0x0000049a rf12_rxbyte + 0x000004e4 0x8 rf12.o + 0x000004e4 rf12_rxbyte .text.rf12_endasyncrx - 0x000004a2 0x8 rf12.o - 0x000004a2 rf12_endasyncrx + 0x000004ec 0x8 rf12.o + 0x000004ec rf12_endasyncrx .text.rf12_txpacket - 0x000004aa 0x82 rf12.o - 0x000004aa rf12_txpacket + 0x000004f4 0x82 rf12.o + 0x000004f4 rf12_txpacket .text.libgcc.div - 0x0000052c 0x44 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_udivmodsi4.o) - 0x0000052c __udivmodsi4 + 0x00000576 0x44 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_udivmodsi4.o) + 0x00000576 __udivmodsi4 .text.libgcc.div - 0x00000570 0x36 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_divmodsi4.o) - 0x00000570 __divmodsi4 - 0x000005a6 . = ALIGN (0x2) + 0x000005ba 0x36 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_divmodsi4.o) + 0x000005ba __divmodsi4 + 0x000005f0 . = ALIGN (0x2) *(.fini9) - .fini9 0x000005a6 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o) - 0x000005a6 _exit - 0x000005a6 exit + .fini9 0x000005f0 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o) + 0x000005f0 _exit + 0x000005f0 exit *(.fini9) *(.fini8) *(.fini8) @@ -350,11 +350,11 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 *(.fini1) *(.fini1) *(.fini0) - .fini0 0x000005a6 0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o) + .fini0 0x000005f0 0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o) *(.fini0) - 0x000005aa _etext = . + 0x000005f4 _etext = . -.data 0x00800060 0x4 load address 0x000005aa +.data 0x00800060 0x4 load address 0x000005f4 0x00800060 PROVIDE (__data_start, .) *(.data) .data 0x00800060 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/../../../../avr/lib/avr25/tiny-stack/crttn24a.o @@ -383,8 +383,8 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 *(.bss*) *(COMMON) 0x00800066 PROVIDE (__bss_end, .) - 0x000005aa __data_load_start = LOADADDR (.data) - 0x000005ae __data_load_end = (__data_load_start + SIZEOF (.data)) + 0x000005f4 __data_load_start = LOADADDR (.data) + 0x000005f8 __data_load_end = (__data_load_start + SIZEOF (.data)) .noinit 0x00800066 0x0 0x00800066 PROVIDE (__noinit_start, .) @@ -460,21 +460,21 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 .debug_pubnames *(.debug_pubnames) -.debug_info 0x00000000 0xf8f +.debug_info 0x00000000 0x1026 *(.debug_info) - .debug_info 0x00000000 0x709 Reciver.o - .debug_info 0x00000709 0x886 rf12.o + .debug_info 0x00000000 0x7a0 Reciver.o + .debug_info 0x000007a0 0x886 rf12.o *(.gnu.linkonce.wi.*) -.debug_abbrev 0x00000000 0x420 +.debug_abbrev 0x00000000 0x40a *(.debug_abbrev) - .debug_abbrev 0x00000000 0x212 Reciver.o - .debug_abbrev 0x00000212 0x20e rf12.o + .debug_abbrev 0x00000000 0x1fc Reciver.o + .debug_abbrev 0x000001fc 0x20e rf12.o -.debug_line 0x00000000 0x553 +.debug_line 0x00000000 0x56e *(.debug_line) - .debug_line 0x00000000 0x284 Reciver.o - .debug_line 0x00000284 0x2cf rf12.o + .debug_line 0x00000000 0x29f Reciver.o + .debug_line 0x0000029f 0x2cf rf12.o .debug_frame 0x00000000 0x1c8 *(.debug_frame) @@ -488,10 +488,10 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8 .debug_str 0x000001ec 0x57 rf12.o 0x242 (size before relaxing) -.debug_loc 0x00000000 0x767 +.debug_loc 0x00000000 0x7d0 *(.debug_loc) - .debug_loc 0x00000000 0x393 Reciver.o - .debug_loc 0x00000393 0x3d4 rf12.o + .debug_loc 0x00000000 0x3fc Reciver.o + .debug_loc 0x000003fc 0x3d4 rf12.o .debug_macinfo *(.debug_macinfo) diff --git a/V5B/Reciver/Reciver/Debug/Reciver.srec b/V5B/Reciver/Reciver/Debug/Reciver.srec index 76da6c4..b6f786d 100644 --- a/V5B/Reciver/Reciver/Debug/Reciver.srec +++ b/V5B/Reciver/Reciver/Debug/Reciver.srec @@ -1,94 +1,99 @@ S00F0000526563697665722E7372656345 S113000010C028C027C026C025C024C023C022C0D9 -S113001021C020C01FC005C11DC01CC01BC01AC008 +S113001021C020C01FC02AC11DC01CC01BC01AC0E3 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+S11305B09B01AC01BD01CF010895052E97FB16F4F4 +S11305C0009406D057FD0CD0D6DF07FC09D07EF48A +S11305D090958095709561957F4F8F4F9F4F0895AB +S11305E050954095309521953F4F4F4F5F4F08955B +S10705F0F894FFCFA9 +S10705F4B400020049 S9030000FC diff --git a/V5B/Reciver/Reciver/Reciver.c b/V5B/Reciver/Reciver/Reciver.c index dd25550..ee50302 100644 --- a/V5B/Reciver/Reciver/Reciver.c +++ b/V5B/Reciver/Reciver/Reciver.c @@ -23,11 +23,11 @@ void turn() { if(status == RUN) return; status = RUN; - servopos = RIGHT-90; + servopos = RIGHT-140; _delay_ms(10+DEVICE); rf12_txpacket(MASTER, DEVICE, status); _delay_ms(400); - servopos = RIGHT-140; + servopos = RIGHT-160; _delay_ms(300); servopos = RIGHT; _delay_ms(700); @@ -122,11 +122,19 @@ void init_timer() { // Timer/Counter 0 Interrupt(s) initialization TIMSK0=(0< 50) { diff --git a/V5B/Reciver/Reciver/codes.h b/V5B/Reciver/Reciver/codes.h index 54dae38..112ae8f 100644 --- a/V5B/Reciver/Reciver/codes.h +++ b/V5B/Reciver/Reciver/codes.h @@ -12,7 +12,7 @@ #ifndef ALL #define ALL 0 #define GROUP 240 -#define DEVICE 10 +#define DEVICE 40 #define MASTER 1 #endif