diff --git a/V5B/Reciver/Reciver.atsuo b/V5B/Reciver/Reciver.atsuo
index 93819c0..150a089 100644
Binary files a/V5B/Reciver/Reciver.atsuo and b/V5B/Reciver/Reciver.atsuo differ
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.elf b/V5B/Reciver/Reciver/Debug/Reciver.elf
index 7bdcb23..651d6ba 100644
Binary files a/V5B/Reciver/Reciver/Debug/Reciver.elf and b/V5B/Reciver/Reciver/Debug/Reciver.elf differ
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.hex b/V5B/Reciver/Reciver/Debug/Reciver.hex
index 1b19b2d..4adf1d5 100644
--- a/V5B/Reciver/Reciver/Debug/Reciver.hex
+++ b/V5B/Reciver/Reciver/Debug/Reciver.hex
@@ -1,94 +1,93 @@
 :1000000010C028C027C026C025C024C023C022C0DD
-:1000100021C020C01FC00CC11DC01CC01BC01AC005
+:1000100021C020C01FC005C11DC01CC01BC01AC00C
 :1000200019C011241FBECFEDCDBF10E0A0E6B0E097
-:10003000E8EBF5E002C005900D92A436B107D9F7C0
+:10003000EAEAF5E002C005900D92A436B107D9F7BF
 :1000400020E0A4E6B0E001C01D92A636B207E1F7B9
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+:1001700090936300809362000895CF937FD101C074
+:10018000B2DF86D18111FCCF88D1882331F08A304B
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+:1004400050E06CEF72E485E090E070D0C901019754
+:10045000966C77DF0895877090E0986970E06295F8
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+:1004D00098EB37DFCFDF8DE298EB33DFCBDF84EDB6
+:1004E00098EB2FDFC7DF812F90E0986B2ADFC2DF08
+:1004F0008D2F90E0986B25DFBDDF8C2F90E0986BFF
+:1005000020DFB8DF80E098EB1CDFB4DF88E092E802
+:1005100018DF2FEF80E792E0215080409040E1F714
+:1005200000C00000DF91CF911F910895A1E21A2E23
+:10053000AA1BBB1BFD010DC0AA1FBB1FEE1FFF1F87
+:10054000A217B307E407F50720F0A21BB30BE40BD7
+:10055000F50B661F771F881F991F1A9469F760951E
+:100560007095809590959B01AC01BD01CF010895D8
+:10057000052E97FB16F4009406D057FD0CD0D6DF5D
+:1005800007FC09D07EF490958095709561957F4F1A
+:100590008F4F9F4F089550954095309521953F4F2F
+:0A05A0004F4F5F4F0895F894FFCF0E
+:0405AA00B400020097
 :00000001FF
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.lss b/V5B/Reciver/Reciver/Debug/Reciver.lss
index 55bef54..d86dcf9 100644
--- a/V5B/Reciver/Reciver/Debug/Reciver.lss
+++ b/V5B/Reciver/Reciver/Debug/Reciver.lss
@@ -3,33 +3,33 @@ Reciver.elf:     file format elf32-avr
 
 Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         000005b8  00000000  00000000  00000094  2**1
+  0 .text         000005aa  00000000  00000000  00000094  2**1
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  1 .data         00000004  00800060  000005b8  0000064c  2**0
+  1 .data         00000004  00800060  000005aa  0000063e  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000002  00800064  00800064  00000650  2**0
+  2 .bss          00000002  00800064  00800064  00000642  2**0
                   ALLOC
-  3 .stab         000006b4  00000000  00000000  00000650  2**2
+  3 .stab         000006b4  00000000  00000000  00000644  2**2
                   CONTENTS, READONLY, DEBUGGING
-  4 .stabstr      00000082  00000000  00000000  00000d04  2**0
+  4 .stabstr      00000082  00000000  00000000  00000cf8  2**0
                   CONTENTS, READONLY, DEBUGGING
-  5 .comment      0000002f  00000000  00000000  00000d86  2**0
+  5 .comment      0000002f  00000000  00000000  00000d7a  2**0
                   CONTENTS, READONLY
-  6 .debug_aranges 000000d0  00000000  00000000  00000db5  2**0
+  6 .debug_aranges 000000d0  00000000  00000000  00000da9  2**0
                   CONTENTS, READONLY, DEBUGGING
-  7 .debug_info   00000f92  00000000  00000000  00000e85  2**0
+  7 .debug_info   00000f8f  00000000  00000000  00000e79  2**0
                   CONTENTS, READONLY, DEBUGGING
-  8 .debug_abbrev 00000420  00000000  00000000  00001e17  2**0
+  8 .debug_abbrev 00000420  00000000  00000000  00001e08  2**0
                   CONTENTS, READONLY, DEBUGGING
-  9 .debug_line   00000553  00000000  00000000  00002237  2**0
+  9 .debug_line   00000553  00000000  00000000  00002228  2**0
                   CONTENTS, READONLY, DEBUGGING
- 10 .debug_frame  000001c8  00000000  00000000  0000278c  2**2
+ 10 .debug_frame  000001c8  00000000  00000000  0000277c  2**2
                   CONTENTS, READONLY, DEBUGGING
- 11 .debug_str    00000243  00000000  00000000  00002954  2**0
+ 11 .debug_str    00000243  00000000  00000000  00002944  2**0
                   CONTENTS, READONLY, DEBUGGING
- 12 .debug_loc    00000767  00000000  00000000  00002b97  2**0
+ 12 .debug_loc    00000767  00000000  00000000  00002b87  2**0
                   CONTENTS, READONLY, DEBUGGING
- 13 .debug_ranges 000000b0  00000000  00000000  000032fe  2**0
+ 13 .debug_ranges 000000b0  00000000  00000000  000032ee  2**0
                   CONTENTS, READONLY, DEBUGGING
 
 Disassembly of section .text:
@@ -46,7 +46,7 @@ Disassembly of section .text:
   10:	21 c0       	rjmp	.+66     	; 0x54 <__bad_interrupt>
   12:	20 c0       	rjmp	.+64     	; 0x54 <__bad_interrupt>
   14:	1f c0       	rjmp	.+62     	; 0x54 <__bad_interrupt>
-  16:	0c c1       	rjmp	.+536    	; 0x230 <__vector_11>
+  16:	05 c1       	rjmp	.+522    	; 0x222 <__vector_11>
   18:	1d c0       	rjmp	.+58     	; 0x54 <__bad_interrupt>
   1a:	1c c0       	rjmp	.+56     	; 0x54 <__bad_interrupt>
   1c:	1b c0       	rjmp	.+54     	; 0x54 <__bad_interrupt>
@@ -63,7 +63,7 @@ Disassembly of section .text:
   2a:	10 e0       	ldi	r17, 0x00	; 0
   2c:	a0 e6       	ldi	r26, 0x60	; 96
   2e:	b0 e0       	ldi	r27, 0x00	; 0
-  30:	e8 eb       	ldi	r30, 0xB8	; 184
+  30:	ea ea       	ldi	r30, 0xAA	; 170
   32:	f5 e0       	ldi	r31, 0x05	; 5
   34:	02 c0       	rjmp	.+4      	; 0x3a <__do_copy_data+0x10>
   36:	05 90       	lpm	r0, Z+
@@ -85,8 +85,8 @@ Disassembly of section .text:
   4a:	a6 36       	cpi	r26, 0x66	; 102
   4c:	b2 07       	cpc	r27, r18
   4e:	e1 f7       	brne	.-8      	; 0x48 <.do_clear_bss_loop>
-  50:	68 d1       	rcall	.+720    	; 0x322 <main>
-  52:	b0 c2       	rjmp	.+1376   	; 0x5b4 <_exit>
+  50:	61 d1       	rcall	.+706    	; 0x314 <main>
+  52:	a9 c2       	rjmp	.+1362   	; 0x5a6 <_exit>
 
 00000054 <__bad_interrupt>:
   54:	d5 cf       	rjmp	.-86     	; 0x0 <__vectors>
@@ -102,7 +102,7 @@ void turn() {
   5a:	90 91 63 00 	lds	r25, 0x0063
   5e:	06 97       	sbiw	r24, 0x06	; 6
   60:	09 f4       	brne	.+2      	; 0x64 <turn+0xe>
-  62:	43 c0       	rjmp	.+134    	; 0xea <__stack+0xb>
+  62:	40 c0       	rjmp	.+128    	; 0xe4 <__stack+0x5>
 		return;
 	status = RUN;
   64:	86 e0       	ldi	r24, 0x06	; 6
@@ -120,1000 +120,993 @@ void turn() {
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
-  7c:	2f e7       	ldi	r18, 0x7F	; 127
-  7e:	88 e3       	ldi	r24, 0x38	; 56
-  80:	91 e0       	ldi	r25, 0x01	; 1
-  82:	21 50       	subi	r18, 0x01	; 1
-  84:	80 40       	sbci	r24, 0x00	; 0
-  86:	90 40       	sbci	r25, 0x00	; 0
-  88:	e1 f7       	brne	.-8      	; 0x82 <turn+0x2c>
-  8a:	00 c0       	rjmp	.+0      	; 0x8c <turn+0x36>
-  8c:	00 00       	nop
+  7c:	8f e3       	ldi	r24, 0x3F	; 63
+  7e:	9c e9       	ldi	r25, 0x9C	; 156
+  80:	01 97       	sbiw	r24, 0x01	; 1
+  82:	f1 f7       	brne	.-4      	; 0x80 <turn+0x2a>
+  84:	00 c0       	rjmp	.+0      	; 0x86 <turn+0x30>
+  86:	00 00       	nop
 	_delay_ms(10+DEVICE);
 	rf12_txpacket(MASTER, DEVICE, status);
-  8e:	40 91 62 00 	lds	r20, 0x0062
-  92:	50 91 63 00 	lds	r21, 0x0063
-  96:	68 e2       	ldi	r22, 0x28	; 40
-  98:	81 e0       	ldi	r24, 0x01	; 1
-  9a:	0e d2       	rcall	.+1052   	; 0x4b8 <rf12_txpacket>
-  9c:	2f ef       	ldi	r18, 0xFF	; 255
-  9e:	83 ec       	ldi	r24, 0xC3	; 195
-  a0:	99 e0       	ldi	r25, 0x09	; 9
-  a2:	21 50       	subi	r18, 0x01	; 1
-  a4:	80 40       	sbci	r24, 0x00	; 0
-  a6:	90 40       	sbci	r25, 0x00	; 0
-  a8:	e1 f7       	brne	.-8      	; 0xa2 <turn+0x4c>
-  aa:	00 c0       	rjmp	.+0      	; 0xac <turn+0x56>
-  ac:	00 00       	nop
+  88:	40 91 62 00 	lds	r20, 0x0062
+  8c:	50 91 63 00 	lds	r21, 0x0063
+  90:	6a e0       	ldi	r22, 0x0A	; 10
+  92:	81 e0       	ldi	r24, 0x01	; 1
+  94:	0a d2       	rcall	.+1044   	; 0x4aa <rf12_txpacket>
+  96:	9f ef       	ldi	r25, 0xFF	; 255
+  98:	23 ec       	ldi	r18, 0xC3	; 195
+  9a:	89 e0       	ldi	r24, 0x09	; 9
+  9c:	91 50       	subi	r25, 0x01	; 1
+  9e:	20 40       	sbci	r18, 0x00	; 0
+  a0:	80 40       	sbci	r24, 0x00	; 0
+  a2:	e1 f7       	brne	.-8      	; 0x9c <turn+0x46>
+  a4:	00 c0       	rjmp	.+0      	; 0xa6 <turn+0x50>
+  a6:	00 00       	nop
 	_delay_ms(400);
 	servopos = RIGHT-140;
-  ae:	88 e2       	ldi	r24, 0x28	; 40
-  b0:	90 e0       	ldi	r25, 0x00	; 0
-  b2:	90 93 61 00 	sts	0x0061, r25
-  b6:	80 93 60 00 	sts	0x0060, r24
-  ba:	2f ef       	ldi	r18, 0xFF	; 255
-  bc:	82 e5       	ldi	r24, 0x52	; 82
-  be:	97 e0       	ldi	r25, 0x07	; 7
-  c0:	21 50       	subi	r18, 0x01	; 1
-  c2:	80 40       	sbci	r24, 0x00	; 0
-  c4:	90 40       	sbci	r25, 0x00	; 0
-  c6:	e1 f7       	brne	.-8      	; 0xc0 <turn+0x6a>
-  c8:	00 c0       	rjmp	.+0      	; 0xca <turn+0x74>
-  ca:	00 00       	nop
+  a8:	88 e2       	ldi	r24, 0x28	; 40
+  aa:	90 e0       	ldi	r25, 0x00	; 0
+  ac:	90 93 61 00 	sts	0x0061, r25
+  b0:	80 93 60 00 	sts	0x0060, r24
+  b4:	9f ef       	ldi	r25, 0xFF	; 255
+  b6:	22 e5       	ldi	r18, 0x52	; 82
+  b8:	87 e0       	ldi	r24, 0x07	; 7
+  ba:	91 50       	subi	r25, 0x01	; 1
+  bc:	20 40       	sbci	r18, 0x00	; 0
+  be:	80 40       	sbci	r24, 0x00	; 0
+  c0:	e1 f7       	brne	.-8      	; 0xba <turn+0x64>
+  c2:	00 c0       	rjmp	.+0      	; 0xc4 <turn+0x6e>
+  c4:	00 00       	nop
 	_delay_ms(300);
 	servopos = RIGHT;
-  cc:	84 eb       	ldi	r24, 0xB4	; 180
-  ce:	90 e0       	ldi	r25, 0x00	; 0
-  d0:	90 93 61 00 	sts	0x0061, r25
-  d4:	80 93 60 00 	sts	0x0060, r24
-  d8:	2f ef       	ldi	r18, 0xFF	; 255
-  da:	86 e1       	ldi	r24, 0x16	; 22
-  dc:	91 e1       	ldi	r25, 0x11	; 17
-  de:	21 50       	subi	r18, 0x01	; 1
-  e0:	80 40       	sbci	r24, 0x00	; 0
-  e2:	90 40       	sbci	r25, 0x00	; 0
-  e4:	e1 f7       	brne	.-8      	; 0xde <turn+0x88>
-  e6:	00 c0       	rjmp	.+0      	; 0xe8 <__stack+0x9>
-  e8:	00 00       	nop
-  ea:	08 95       	ret
+  c6:	84 eb       	ldi	r24, 0xB4	; 180
+  c8:	90 e0       	ldi	r25, 0x00	; 0
+  ca:	90 93 61 00 	sts	0x0061, r25
+  ce:	80 93 60 00 	sts	0x0060, r24
+  d2:	9f ef       	ldi	r25, 0xFF	; 255
+  d4:	26 e1       	ldi	r18, 0x16	; 22
+  d6:	81 e1       	ldi	r24, 0x11	; 17
+  d8:	91 50       	subi	r25, 0x01	; 1
+  da:	20 40       	sbci	r18, 0x00	; 0
+  dc:	80 40       	sbci	r24, 0x00	; 0
+  de:	e1 f7       	brne	.-8      	; 0xd8 <turn+0x82>
+  e0:	00 c0       	rjmp	.+0      	; 0xe2 <__stack+0x3>
+  e2:	00 00       	nop
+  e4:	08 95       	ret
 
-000000ec <poll>:
+000000e6 <poll>:
 	_delay_ms(700);
 }
 
 void poll() {
 	DDRB &= ~(1<<PINB2);
-  ec:	ba 98       	cbi	0x17, 2	; 23
+  e6:	ba 98       	cbi	0x17, 2	; 23
 	if(status == ACTIVE) {
-  ee:	80 91 62 00 	lds	r24, 0x0062
-  f2:	90 91 63 00 	lds	r25, 0x0063
-  f6:	03 97       	sbiw	r24, 0x03	; 3
-  f8:	29 f4       	brne	.+10     	; 0x104 <poll+0x18>
+  e8:	80 91 62 00 	lds	r24, 0x0062
+  ec:	90 91 63 00 	lds	r25, 0x0063
+  f0:	03 97       	sbiw	r24, 0x03	; 3
+  f2:	29 f4       	brne	.+10     	; 0xfe <poll+0x18>
 		if(PINB & (1<<PINB2)) {
-  fa:	b2 9b       	sbis	0x16, 2	; 22
-  fc:	03 c0       	rjmp	.+6      	; 0x104 <poll+0x18>
+  f4:	b2 9b       	sbis	0x16, 2	; 22
+  f6:	03 c0       	rjmp	.+6      	; 0xfe <poll+0x18>
 			rf12_endasyncrx();
-  fe:	d8 d1       	rcall	.+944    	; 0x4b0 <rf12_endasyncrx>
+  f8:	d4 d1       	rcall	.+936    	; 0x4a2 <rf12_endasyncrx>
 			turn();
- 100:	aa df       	rcall	.-172    	; 0x56 <turn>
+  fa:	ad df       	rcall	.-166    	; 0x56 <turn>
 			rf12_beginasyncrx();
- 102:	c3 d1       	rcall	.+902    	; 0x48a <rf12_beginasyncrx>
+  fc:	bf d1       	rcall	.+894    	; 0x47c <rf12_beginasyncrx>
 		}
 	}
 	if(status == SLEEP) {
- 104:	80 91 62 00 	lds	r24, 0x0062
- 108:	90 91 63 00 	lds	r25, 0x0063
- 10c:	02 97       	sbiw	r24, 0x02	; 2
- 10e:	41 f4       	brne	.+16     	; 0x120 <poll+0x34>
+  fe:	80 91 62 00 	lds	r24, 0x0062
+ 102:	90 91 63 00 	lds	r25, 0x0063
+ 106:	02 97       	sbiw	r24, 0x02	; 2
+ 108:	41 f4       	brne	.+16     	; 0x11a <poll+0x34>
 		if(PINB & (1<<PINB2)) {
- 110:	b2 9b       	sbis	0x16, 2	; 22
- 112:	06 c0       	rjmp	.+12     	; 0x120 <poll+0x34>
+ 10a:	b2 9b       	sbis	0x16, 2	; 22
+ 10c:	06 c0       	rjmp	.+12     	; 0x11a <poll+0x34>
 			rf12_endasyncrx();
- 114:	cd d1       	rcall	.+922    	; 0x4b0 <rf12_endasyncrx>
+ 10e:	c9 d1       	rcall	.+914    	; 0x4a2 <rf12_endasyncrx>
 			rf12_txpacket(MASTER, DEVICE, DEDECT);
- 116:	48 e0       	ldi	r20, 0x08	; 8
- 118:	68 e2       	ldi	r22, 0x28	; 40
- 11a:	81 e0       	ldi	r24, 0x01	; 1
- 11c:	cd d1       	rcall	.+922    	; 0x4b8 <rf12_txpacket>
+ 110:	48 e0       	ldi	r20, 0x08	; 8
+ 112:	6a e0       	ldi	r22, 0x0A	; 10
+ 114:	81 e0       	ldi	r24, 0x01	; 1
+ 116:	c9 d1       	rcall	.+914    	; 0x4aa <rf12_txpacket>
 			rf12_beginasyncrx();
- 11e:	b5 d1       	rcall	.+874    	; 0x48a <rf12_beginasyncrx>
+ 118:	b1 d1       	rcall	.+866    	; 0x47c <rf12_beginasyncrx>
 		}			
 	}
 	if(!(PINA & (1<<PINA4))) { //SCK auf 0
- 120:	cc 99       	sbic	0x19, 4	; 25
- 122:	2d c0       	rjmp	.+90     	; 0x17e <poll+0x92>
+ 11a:	cc 99       	sbic	0x19, 4	; 25
+ 11c:	2d c0       	rjmp	.+90     	; 0x178 <poll+0x92>
 		if(status == SLEEP) {
- 124:	80 91 62 00 	lds	r24, 0x0062
- 128:	90 91 63 00 	lds	r25, 0x0063
- 12c:	02 97       	sbiw	r24, 0x02	; 2
- 12e:	39 f5       	brne	.+78     	; 0x17e <poll+0x92>
+ 11e:	80 91 62 00 	lds	r24, 0x0062
+ 122:	90 91 63 00 	lds	r25, 0x0063
+ 126:	02 97       	sbiw	r24, 0x02	; 2
+ 128:	39 f5       	brne	.+78     	; 0x178 <poll+0x92>
 			status = RUN;
- 130:	86 e0       	ldi	r24, 0x06	; 6
- 132:	90 e0       	ldi	r25, 0x00	; 0
- 134:	90 93 63 00 	sts	0x0063, r25
- 138:	80 93 62 00 	sts	0x0062, r24
- 13c:	2f ef       	ldi	r18, 0xFF	; 255
- 13e:	81 e1       	ldi	r24, 0x11	; 17
- 140:	9a e7       	ldi	r25, 0x7A	; 122
- 142:	21 50       	subi	r18, 0x01	; 1
- 144:	80 40       	sbci	r24, 0x00	; 0
- 146:	90 40       	sbci	r25, 0x00	; 0
- 148:	e1 f7       	brne	.-8      	; 0x142 <poll+0x56>
- 14a:	00 c0       	rjmp	.+0      	; 0x14c <poll+0x60>
- 14c:	00 00       	nop
- 14e:	2f ef       	ldi	r18, 0xFF	; 255
- 150:	81 e1       	ldi	r24, 0x11	; 17
- 152:	9a e7       	ldi	r25, 0x7A	; 122
- 154:	21 50       	subi	r18, 0x01	; 1
- 156:	80 40       	sbci	r24, 0x00	; 0
- 158:	90 40       	sbci	r25, 0x00	; 0
- 15a:	e1 f7       	brne	.-8      	; 0x154 <poll+0x68>
- 15c:	00 c0       	rjmp	.+0      	; 0x15e <poll+0x72>
- 15e:	00 00       	nop
- 160:	2f ef       	ldi	r18, 0xFF	; 255
- 162:	81 e1       	ldi	r24, 0x11	; 17
- 164:	9a e7       	ldi	r25, 0x7A	; 122
- 166:	21 50       	subi	r18, 0x01	; 1
- 168:	80 40       	sbci	r24, 0x00	; 0
- 16a:	90 40       	sbci	r25, 0x00	; 0
- 16c:	e1 f7       	brne	.-8      	; 0x166 <poll+0x7a>
- 16e:	00 c0       	rjmp	.+0      	; 0x170 <poll+0x84>
- 170:	00 00       	nop
+ 12a:	86 e0       	ldi	r24, 0x06	; 6
+ 12c:	90 e0       	ldi	r25, 0x00	; 0
+ 12e:	90 93 63 00 	sts	0x0063, r25
+ 132:	80 93 62 00 	sts	0x0062, r24
+ 136:	2f ef       	ldi	r18, 0xFF	; 255
+ 138:	81 e1       	ldi	r24, 0x11	; 17
+ 13a:	9a e7       	ldi	r25, 0x7A	; 122
+ 13c:	21 50       	subi	r18, 0x01	; 1
+ 13e:	80 40       	sbci	r24, 0x00	; 0
+ 140:	90 40       	sbci	r25, 0x00	; 0
+ 142:	e1 f7       	brne	.-8      	; 0x13c <poll+0x56>
+ 144:	00 c0       	rjmp	.+0      	; 0x146 <poll+0x60>
+ 146:	00 00       	nop
+ 148:	2f ef       	ldi	r18, 0xFF	; 255
+ 14a:	81 e1       	ldi	r24, 0x11	; 17
+ 14c:	9a e7       	ldi	r25, 0x7A	; 122
+ 14e:	21 50       	subi	r18, 0x01	; 1
+ 150:	80 40       	sbci	r24, 0x00	; 0
+ 152:	90 40       	sbci	r25, 0x00	; 0
+ 154:	e1 f7       	brne	.-8      	; 0x14e <poll+0x68>
+ 156:	00 c0       	rjmp	.+0      	; 0x158 <poll+0x72>
+ 158:	00 00       	nop
+ 15a:	2f ef       	ldi	r18, 0xFF	; 255
+ 15c:	81 e1       	ldi	r24, 0x11	; 17
+ 15e:	9a e7       	ldi	r25, 0x7A	; 122
+ 160:	21 50       	subi	r18, 0x01	; 1
+ 162:	80 40       	sbci	r24, 0x00	; 0
+ 164:	90 40       	sbci	r25, 0x00	; 0
+ 166:	e1 f7       	brne	.-8      	; 0x160 <poll+0x7a>
+ 168:	00 c0       	rjmp	.+0      	; 0x16a <poll+0x84>
+ 16a:	00 00       	nop
 			_delay_ms(5000);
 			_delay_ms(5000);
 			_delay_ms(5000);
 			status = ACTIVE;
- 172:	83 e0       	ldi	r24, 0x03	; 3
- 174:	90 e0       	ldi	r25, 0x00	; 0
- 176:	90 93 63 00 	sts	0x0063, r25
- 17a:	80 93 62 00 	sts	0x0062, r24
- 17e:	08 95       	ret
+ 16c:	83 e0       	ldi	r24, 0x03	; 3
+ 16e:	90 e0       	ldi	r25, 0x00	; 0
+ 170:	90 93 63 00 	sts	0x0063, r25
+ 174:	80 93 62 00 	sts	0x0062, r24
+ 178:	08 95       	ret
 
-00000180 <recive>:
+0000017a <recive>:
 		}
 	}
 }
 
 void recive() {
- 180:	cf 93       	push	r28
+ 17a:	cf 93       	push	r28
 	rf12_beginasyncrx();
- 182:	83 d1       	rcall	.+774    	; 0x48a <rf12_beginasyncrx>
+ 17c:	7f d1       	rcall	.+766    	; 0x47c <rf12_beginasyncrx>
 	while(rf12_hasdata()) {
- 184:	01 c0       	rjmp	.+2      	; 0x188 <recive+0x8>
+ 17e:	01 c0       	rjmp	.+2      	; 0x182 <recive+0x8>
 		poll();
- 186:	b2 df       	rcall	.-156    	; 0xec <poll>
+ 180:	b2 df       	rcall	.-156    	; 0xe6 <poll>
 	}
 }
 
 void recive() {
 	rf12_beginasyncrx();
 	while(rf12_hasdata()) {
- 188:	8a d1       	rcall	.+788    	; 0x49e <rf12_hasdata>
- 18a:	81 11       	cpse	r24, r1
- 18c:	fc cf       	rjmp	.-8      	; 0x186 <recive+0x6>
+ 182:	86 d1       	rcall	.+780    	; 0x490 <rf12_hasdata>
+ 184:	81 11       	cpse	r24, r1
+ 186:	fc cf       	rjmp	.-8      	; 0x180 <recive+0x6>
 		poll();
 	}
 	uint8_t addr = rf12_rxbyte();
- 18e:	8c d1       	rcall	.+792    	; 0x4a8 <rf12_rxbyte>
+ 188:	88 d1       	rcall	.+784    	; 0x49a <rf12_rxbyte>
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
- 190:	88 23       	and	r24, r24
- 192:	39 f0       	breq	.+14     	; 0x1a2 <recive+0x22>
- 194:	88 32       	cpi	r24, 0x28	; 40
- 196:	29 f0       	breq	.+10     	; 0x1a2 <recive+0x22>
- 198:	80 3f       	cpi	r24, 0xF0	; 240
- 19a:	09 f0       	breq	.+2      	; 0x19e <recive+0x1e>
- 19c:	3f c0       	rjmp	.+126    	; 0x21c <recive+0x9c>
- 19e:	01 c0       	rjmp	.+2      	; 0x1a2 <recive+0x22>
+ 18a:	88 23       	and	r24, r24
+ 18c:	31 f0       	breq	.+12     	; 0x19a <recive+0x20>
+ 18e:	8a 30       	cpi	r24, 0x0A	; 10
+ 190:	21 f0       	breq	.+8      	; 0x19a <recive+0x20>
+ 192:	80 3f       	cpi	r24, 0xF0	; 240
+ 194:	e1 f5       	brne	.+120    	; 0x20e <recive+0x94>
+ 196:	01 c0       	rjmp	.+2      	; 0x19a <recive+0x20>
 		while(rf12_hasdata()) {
 			poll();
- 1a0:	a5 df       	rcall	.-182    	; 0xec <poll>
+ 198:	a6 df       	rcall	.-180    	; 0xe6 <poll>
 	while(rf12_hasdata()) {
 		poll();
 	}
 	uint8_t addr = rf12_rxbyte();
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
 		while(rf12_hasdata()) {
- 1a2:	7d d1       	rcall	.+762    	; 0x49e <rf12_hasdata>
- 1a4:	81 11       	cpse	r24, r1
- 1a6:	fc cf       	rjmp	.-8      	; 0x1a0 <recive+0x20>
+ 19a:	7a d1       	rcall	.+756    	; 0x490 <rf12_hasdata>
+ 19c:	81 11       	cpse	r24, r1
+ 19e:	fc cf       	rjmp	.-8      	; 0x198 <recive+0x1e>
 			poll();
 		}
 		uint8_t from = rf12_rxbyte();
- 1a8:	7f d1       	rcall	.+766    	; 0x4a8 <rf12_rxbyte>
- 1aa:	c8 2f       	mov	r28, r24
+ 1a0:	7c d1       	rcall	.+760    	; 0x49a <rf12_rxbyte>
+ 1a2:	c8 2f       	mov	r28, r24
 		while(rf12_hasdata()) {
- 1ac:	01 c0       	rjmp	.+2      	; 0x1b0 <recive+0x30>
+ 1a4:	01 c0       	rjmp	.+2      	; 0x1a8 <recive+0x2e>
 			poll();
- 1ae:	9e df       	rcall	.-196    	; 0xec <poll>
+ 1a6:	9f df       	rcall	.-194    	; 0xe6 <poll>
 	if(addr == ALL || addr == DEVICE || addr == GROUP) {
 		while(rf12_hasdata()) {
 			poll();
 		}
 		uint8_t from = rf12_rxbyte();
 		while(rf12_hasdata()) {
- 1b0:	76 d1       	rcall	.+748    	; 0x49e <rf12_hasdata>
- 1b2:	81 11       	cpse	r24, r1
- 1b4:	fc cf       	rjmp	.-8      	; 0x1ae <recive+0x2e>
+ 1a8:	73 d1       	rcall	.+742    	; 0x490 <rf12_hasdata>
+ 1aa:	81 11       	cpse	r24, r1
+ 1ac:	fc cf       	rjmp	.-8      	; 0x1a6 <recive+0x2c>
 			poll();
 		}
 		if(from == MASTER) {
- 1b6:	c1 30       	cpi	r28, 0x01	; 1
- 1b8:	89 f5       	brne	.+98     	; 0x21c <recive+0x9c>
+ 1ae:	c1 30       	cpi	r28, 0x01	; 1
+ 1b0:	71 f5       	brne	.+92     	; 0x20e <recive+0x94>
 			uint8_t data = rf12_rxbyte();
- 1ba:	76 d1       	rcall	.+748    	; 0x4a8 <rf12_rxbyte>
+ 1b2:	73 d1       	rcall	.+742    	; 0x49a <rf12_rxbyte>
 			switch(data) {
- 1bc:	84 30       	cpi	r24, 0x04	; 4
- 1be:	49 f0       	breq	.+18     	; 0x1d2 <recive+0x52>
- 1c0:	18 f4       	brcc	.+6      	; 0x1c8 <recive+0x48>
- 1c2:	81 30       	cpi	r24, 0x01	; 1
- 1c4:	c1 f4       	brne	.+48     	; 0x1f6 <recive+0x76>
- 1c6:	19 c0       	rjmp	.+50     	; 0x1fa <recive+0x7a>
- 1c8:	85 30       	cpi	r24, 0x05	; 5
- 1ca:	51 f0       	breq	.+20     	; 0x1e0 <recive+0x60>
- 1cc:	87 30       	cpi	r24, 0x07	; 7
- 1ce:	99 f4       	brne	.+38     	; 0x1f6 <recive+0x76>
- 1d0:	0e c0       	rjmp	.+28     	; 0x1ee <recive+0x6e>
+ 1b4:	84 30       	cpi	r24, 0x04	; 4
+ 1b6:	49 f0       	breq	.+18     	; 0x1ca <recive+0x50>
+ 1b8:	18 f4       	brcc	.+6      	; 0x1c0 <recive+0x46>
+ 1ba:	81 30       	cpi	r24, 0x01	; 1
+ 1bc:	c1 f4       	brne	.+48     	; 0x1ee <recive+0x74>
+ 1be:	19 c0       	rjmp	.+50     	; 0x1f2 <recive+0x78>
+ 1c0:	85 30       	cpi	r24, 0x05	; 5
+ 1c2:	51 f0       	breq	.+20     	; 0x1d8 <recive+0x5e>
+ 1c4:	87 30       	cpi	r24, 0x07	; 7
+ 1c6:	99 f4       	brne	.+38     	; 0x1ee <recive+0x74>
+ 1c8:	0e c0       	rjmp	.+28     	; 0x1e6 <recive+0x6c>
 				case PING: {
 					break;
 				}
 				case SETSLEEP: {
 					status = SLEEP;
- 1d2:	82 e0       	ldi	r24, 0x02	; 2
- 1d4:	90 e0       	ldi	r25, 0x00	; 0
- 1d6:	90 93 63 00 	sts	0x0063, r25
- 1da:	80 93 62 00 	sts	0x0062, r24
+ 1ca:	82 e0       	ldi	r24, 0x02	; 2
+ 1cc:	90 e0       	ldi	r25, 0x00	; 0
+ 1ce:	90 93 63 00 	sts	0x0063, r25
+ 1d2:	80 93 62 00 	sts	0x0062, r24
 					break;
- 1de:	0d c0       	rjmp	.+26     	; 0x1fa <recive+0x7a>
+ 1d6:	0d c0       	rjmp	.+26     	; 0x1f2 <recive+0x78>
 				}
 				case SETACTIVE: {
 					status = ACTIVE;
- 1e0:	83 e0       	ldi	r24, 0x03	; 3
- 1e2:	90 e0       	ldi	r25, 0x00	; 0
- 1e4:	90 93 63 00 	sts	0x0063, r25
- 1e8:	80 93 62 00 	sts	0x0062, r24
+ 1d8:	83 e0       	ldi	r24, 0x03	; 3
+ 1da:	90 e0       	ldi	r25, 0x00	; 0
+ 1dc:	90 93 63 00 	sts	0x0063, r25
+ 1e0:	80 93 62 00 	sts	0x0062, r24
 					break;
- 1ec:	06 c0       	rjmp	.+12     	; 0x1fa <recive+0x7a>
+ 1e4:	06 c0       	rjmp	.+12     	; 0x1f2 <recive+0x78>
 				}
 				case SETRUN: {
 					rf12_endasyncrx();
- 1ee:	60 d1       	rcall	.+704    	; 0x4b0 <rf12_endasyncrx>
+ 1e6:	5d d1       	rcall	.+698    	; 0x4a2 <rf12_endasyncrx>
 					turn();
- 1f0:	32 df       	rcall	.-412    	; 0x56 <turn>
+ 1e8:	36 df       	rcall	.-404    	; 0x56 <turn>
 					rf12_beginasyncrx();
- 1f2:	4b d1       	rcall	.+662    	; 0x48a <rf12_beginasyncrx>
+ 1ea:	48 d1       	rcall	.+656    	; 0x47c <rf12_beginasyncrx>
 					return;
- 1f4:	13 c0       	rjmp	.+38     	; 0x21c <recive+0x9c>
+ 1ec:	10 c0       	rjmp	.+32     	; 0x20e <recive+0x94>
 				}
 				default:
 				{
 					rf12_endasyncrx();
- 1f6:	5c d1       	rcall	.+696    	; 0x4b0 <rf12_endasyncrx>
+ 1ee:	59 d1       	rcall	.+690    	; 0x4a2 <rf12_endasyncrx>
 					return;
- 1f8:	11 c0       	rjmp	.+34     	; 0x21c <recive+0x9c>
+ 1f0:	0e c0       	rjmp	.+28     	; 0x20e <recive+0x94>
 				}
 			}
 			rf12_endasyncrx();
- 1fa:	5a d1       	rcall	.+692    	; 0x4b0 <rf12_endasyncrx>
- 1fc:	2f e7       	ldi	r18, 0x7F	; 127
- 1fe:	88 e3       	ldi	r24, 0x38	; 56
- 200:	91 e0       	ldi	r25, 0x01	; 1
- 202:	21 50       	subi	r18, 0x01	; 1
- 204:	80 40       	sbci	r24, 0x00	; 0
- 206:	90 40       	sbci	r25, 0x00	; 0
- 208:	e1 f7       	brne	.-8      	; 0x202 <recive+0x82>
- 20a:	00 c0       	rjmp	.+0      	; 0x20c <recive+0x8c>
- 20c:	00 00       	nop
+ 1f2:	57 d1       	rcall	.+686    	; 0x4a2 <rf12_endasyncrx>
+ 1f4:	8f e3       	ldi	r24, 0x3F	; 63
+ 1f6:	9c e9       	ldi	r25, 0x9C	; 156
+ 1f8:	01 97       	sbiw	r24, 0x01	; 1
+ 1fa:	f1 f7       	brne	.-4      	; 0x1f8 <recive+0x7e>
+ 1fc:	00 c0       	rjmp	.+0      	; 0x1fe <recive+0x84>
+ 1fe:	00 00       	nop
 			_delay_ms(10+DEVICE);
 			rf12_txpacket(MASTER, DEVICE, status);
- 20e:	40 91 62 00 	lds	r20, 0x0062
- 212:	50 91 63 00 	lds	r21, 0x0063
- 216:	68 e2       	ldi	r22, 0x28	; 40
- 218:	81 e0       	ldi	r24, 0x01	; 1
- 21a:	4e d1       	rcall	.+668    	; 0x4b8 <rf12_txpacket>
+ 200:	40 91 62 00 	lds	r20, 0x0062
+ 204:	50 91 63 00 	lds	r21, 0x0063
+ 208:	6a e0       	ldi	r22, 0x0A	; 10
+ 20a:	81 e0       	ldi	r24, 0x01	; 1
+ 20c:	4e d1       	rcall	.+668    	; 0x4aa <rf12_txpacket>
 			return;
 		}					
 	}
 }
- 21c:	cf 91       	pop	r28
- 21e:	08 95       	ret
+ 20e:	cf 91       	pop	r28
+ 210:	08 95       	ret
 
-00000220 <init_timer>:
+00000212 <init_timer>:
 	// Clock value: 7,813 kHz
 	// Mode: Normal top=0xFF
 	// OC0A output: Disconnected
 	// OC0B output: Disconnected
 	// Timer Period: 21,504 ms
 	TCCR0A = (0<<COM0A1) | (0<<COM0A0) | (0<<COM0B1) | (0<<COM0B0) | (0<<WGM01) | (0<<WGM00);
- 220:	10 be       	out	0x30, r1	; 48
+ 212:	10 be       	out	0x30, r1	; 48
 	TCCR0B = (0<<WGM02) | (1<<CS02) | (0<<CS01) | (1<<CS00);
- 222:	85 e0       	ldi	r24, 0x05	; 5
- 224:	83 bf       	out	0x33, r24	; 51
+ 214:	85 e0       	ldi	r24, 0x05	; 5
+ 216:	83 bf       	out	0x33, r24	; 51
 	TCNT0 = 0x58;
- 226:	88 e5       	ldi	r24, 0x58	; 88
- 228:	82 bf       	out	0x32, r24	; 50
+ 218:	88 e5       	ldi	r24, 0x58	; 88
+ 21a:	82 bf       	out	0x32, r24	; 50
 	
 	// Timer/Counter 0 Interrupt(s) initialization
 	TIMSK0=(0<<OCIE0B) | (0<<OCIE0A) | (1<<TOIE0);
- 22a:	81 e0       	ldi	r24, 0x01	; 1
- 22c:	89 bf       	out	0x39, r24	; 57
- 22e:	08 95       	ret
+ 21c:	81 e0       	ldi	r24, 0x01	; 1
+ 21e:	89 bf       	out	0x39, r24	; 57
+ 220:	08 95       	ret
 
-00000230 <__vector_11>:
+00000222 <__vector_11>:
 }
 
 ISR(TIM0_OVF_vect) {
- 230:	1f 92       	push	r1
- 232:	0f 92       	push	r0
- 234:	0f b6       	in	r0, 0x3f	; 63
- 236:	0f 92       	push	r0
- 238:	11 24       	eor	r1, r1
- 23a:	2f 93       	push	r18
- 23c:	3f 93       	push	r19
- 23e:	8f 93       	push	r24
- 240:	9f 93       	push	r25
+ 222:	1f 92       	push	r1
+ 224:	0f 92       	push	r0
+ 226:	0f b6       	in	r0, 0x3f	; 63
+ 228:	0f 92       	push	r0
+ 22a:	11 24       	eor	r1, r1
+ 22c:	2f 93       	push	r18
+ 22e:	3f 93       	push	r19
+ 230:	8f 93       	push	r24
+ 232:	9f 93       	push	r25
 	// Reinitialize Timer 0 value
 	TCNT0=0x58;
- 242:	88 e5       	ldi	r24, 0x58	; 88
- 244:	82 bf       	out	0x32, r24	; 50
+ 234:	88 e5       	ldi	r24, 0x58	; 88
+ 236:	82 bf       	out	0x32, r24	; 50
 	
 	if(status == SLEEP) {
- 246:	80 91 62 00 	lds	r24, 0x0062
- 24a:	90 91 63 00 	lds	r25, 0x0063
- 24e:	02 97       	sbiw	r24, 0x02	; 2
- 250:	79 f4       	brne	.+30     	; 0x270 <__vector_11+0x40>
+ 238:	80 91 62 00 	lds	r24, 0x0062
+ 23c:	90 91 63 00 	lds	r25, 0x0063
+ 240:	02 97       	sbiw	r24, 0x02	; 2
+ 242:	79 f4       	brne	.+30     	; 0x262 <__vector_11+0x40>
 		if(pwm_led > 50) {
- 252:	80 91 64 00 	lds	r24, 0x0064
- 256:	90 91 65 00 	lds	r25, 0x0065
- 25a:	c3 97       	sbiw	r24, 0x33	; 51
- 25c:	94 f1       	brlt	.+100    	; 0x2c2 <__vector_11+0x92>
+ 244:	80 91 64 00 	lds	r24, 0x0064
+ 248:	90 91 65 00 	lds	r25, 0x0065
+ 24c:	c3 97       	sbiw	r24, 0x33	; 51
+ 24e:	94 f1       	brlt	.+100    	; 0x2b4 <__vector_11+0x92>
 			PORTB ^= (1<<PINB1);
- 25e:	98 b3       	in	r25, 0x18	; 24
- 260:	82 e0       	ldi	r24, 0x02	; 2
- 262:	89 27       	eor	r24, r25
- 264:	88 bb       	out	0x18, r24	; 24
+ 250:	98 b3       	in	r25, 0x18	; 24
+ 252:	82 e0       	ldi	r24, 0x02	; 2
+ 254:	89 27       	eor	r24, r25
+ 256:	88 bb       	out	0x18, r24	; 24
 			pwm_led = 0;
- 266:	10 92 65 00 	sts	0x0065, r1
- 26a:	10 92 64 00 	sts	0x0064, r1
- 26e:	29 c0       	rjmp	.+82     	; 0x2c2 <__vector_11+0x92>
+ 258:	10 92 65 00 	sts	0x0065, r1
+ 25c:	10 92 64 00 	sts	0x0064, r1
+ 260:	29 c0       	rjmp	.+82     	; 0x2b4 <__vector_11+0x92>
 		}					
 	} else if(status == ACTIVE) {
- 270:	80 91 62 00 	lds	r24, 0x0062
- 274:	90 91 63 00 	lds	r25, 0x0063
- 278:	03 97       	sbiw	r24, 0x03	; 3
- 27a:	79 f4       	brne	.+30     	; 0x29a <__vector_11+0x6a>
+ 262:	80 91 62 00 	lds	r24, 0x0062
+ 266:	90 91 63 00 	lds	r25, 0x0063
+ 26a:	03 97       	sbiw	r24, 0x03	; 3
+ 26c:	79 f4       	brne	.+30     	; 0x28c <__vector_11+0x6a>
 		if(pwm_led > 5) {
- 27c:	80 91 64 00 	lds	r24, 0x0064
- 280:	90 91 65 00 	lds	r25, 0x0065
- 284:	06 97       	sbiw	r24, 0x06	; 6
- 286:	ec f0       	brlt	.+58     	; 0x2c2 <__vector_11+0x92>
+ 26e:	80 91 64 00 	lds	r24, 0x0064
+ 272:	90 91 65 00 	lds	r25, 0x0065
+ 276:	06 97       	sbiw	r24, 0x06	; 6
+ 278:	ec f0       	brlt	.+58     	; 0x2b4 <__vector_11+0x92>
 			PORTB ^= (1<<PINB1);
- 288:	98 b3       	in	r25, 0x18	; 24
- 28a:	82 e0       	ldi	r24, 0x02	; 2
- 28c:	89 27       	eor	r24, r25
- 28e:	88 bb       	out	0x18, r24	; 24
+ 27a:	98 b3       	in	r25, 0x18	; 24
+ 27c:	82 e0       	ldi	r24, 0x02	; 2
+ 27e:	89 27       	eor	r24, r25
+ 280:	88 bb       	out	0x18, r24	; 24
 			pwm_led = 0;
- 290:	10 92 65 00 	sts	0x0065, r1
- 294:	10 92 64 00 	sts	0x0064, r1
- 298:	14 c0       	rjmp	.+40     	; 0x2c2 <__vector_11+0x92>
+ 282:	10 92 65 00 	sts	0x0065, r1
+ 286:	10 92 64 00 	sts	0x0064, r1
+ 28a:	14 c0       	rjmp	.+40     	; 0x2b4 <__vector_11+0x92>
 		}
 	} else if(status == RUN) {
- 29a:	80 91 62 00 	lds	r24, 0x0062
- 29e:	90 91 63 00 	lds	r25, 0x0063
- 2a2:	06 97       	sbiw	r24, 0x06	; 6
- 2a4:	71 f4       	brne	.+28     	; 0x2c2 <__vector_11+0x92>
+ 28c:	80 91 62 00 	lds	r24, 0x0062
+ 290:	90 91 63 00 	lds	r25, 0x0063
+ 294:	06 97       	sbiw	r24, 0x06	; 6
+ 296:	71 f4       	brne	.+28     	; 0x2b4 <__vector_11+0x92>
 		if(pwm_led > 1) {
- 2a6:	80 91 64 00 	lds	r24, 0x0064
- 2aa:	90 91 65 00 	lds	r25, 0x0065
- 2ae:	02 97       	sbiw	r24, 0x02	; 2
- 2b0:	44 f0       	brlt	.+16     	; 0x2c2 <__vector_11+0x92>
+ 298:	80 91 64 00 	lds	r24, 0x0064
+ 29c:	90 91 65 00 	lds	r25, 0x0065
+ 2a0:	02 97       	sbiw	r24, 0x02	; 2
+ 2a2:	44 f0       	brlt	.+16     	; 0x2b4 <__vector_11+0x92>
 			PORTB ^= (1<<PINB1);
- 2b2:	98 b3       	in	r25, 0x18	; 24
- 2b4:	82 e0       	ldi	r24, 0x02	; 2
- 2b6:	89 27       	eor	r24, r25
- 2b8:	88 bb       	out	0x18, r24	; 24
+ 2a4:	98 b3       	in	r25, 0x18	; 24
+ 2a6:	82 e0       	ldi	r24, 0x02	; 2
+ 2a8:	89 27       	eor	r24, r25
+ 2aa:	88 bb       	out	0x18, r24	; 24
 			pwm_led = 0;
- 2ba:	10 92 65 00 	sts	0x0065, r1
- 2be:	10 92 64 00 	sts	0x0064, r1
+ 2ac:	10 92 65 00 	sts	0x0065, r1
+ 2b0:	10 92 64 00 	sts	0x0064, r1
 		}
 	}
 	pwm_led++;	
- 2c2:	80 91 64 00 	lds	r24, 0x0064
- 2c6:	90 91 65 00 	lds	r25, 0x0065
- 2ca:	01 96       	adiw	r24, 0x01	; 1
- 2cc:	90 93 65 00 	sts	0x0065, r25
- 2d0:	80 93 64 00 	sts	0x0064, r24
+ 2b4:	80 91 64 00 	lds	r24, 0x0064
+ 2b8:	90 91 65 00 	lds	r25, 0x0065
+ 2bc:	01 96       	adiw	r24, 0x01	; 1
+ 2be:	90 93 65 00 	sts	0x0065, r25
+ 2c2:	80 93 64 00 	sts	0x0064, r24
 	
 	DDRB |= (1<<PINB0);
- 2d4:	b8 9a       	sbi	0x17, 0	; 23
+ 2c6:	b8 9a       	sbi	0x17, 0	; 23
 	PORTB |= (1<<PINB0);
- 2d6:	c0 9a       	sbi	0x18, 0	; 24
+ 2c8:	c0 9a       	sbi	0x18, 0	; 24
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
- 2d8:	8f ea       	ldi	r24, 0xAF	; 175
- 2da:	94 e0       	ldi	r25, 0x04	; 4
- 2dc:	01 97       	sbiw	r24, 0x01	; 1
- 2de:	f1 f7       	brne	.-4      	; 0x2dc <__vector_11+0xac>
- 2e0:	00 c0       	rjmp	.+0      	; 0x2e2 <__vector_11+0xb2>
- 2e2:	00 00       	nop
+ 2ca:	8f ea       	ldi	r24, 0xAF	; 175
+ 2cc:	94 e0       	ldi	r25, 0x04	; 4
+ 2ce:	01 97       	sbiw	r24, 0x01	; 1
+ 2d0:	f1 f7       	brne	.-4      	; 0x2ce <__vector_11+0xac>
+ 2d2:	00 c0       	rjmp	.+0      	; 0x2d4 <__vector_11+0xb2>
+ 2d4:	00 00       	nop
 	_delay_us(LEFT);
 	for(int i=0;i<servopos;i++) {
- 2e4:	80 91 60 00 	lds	r24, 0x0060
- 2e8:	90 91 61 00 	lds	r25, 0x0061
- 2ec:	18 16       	cp	r1, r24
- 2ee:	19 06       	cpc	r1, r25
- 2f0:	74 f4       	brge	.+28     	; 0x30e <__vector_11+0xde>
- 2f2:	80 e0       	ldi	r24, 0x00	; 0
- 2f4:	90 e0       	ldi	r25, 0x00	; 0
- 2f6:	25 e1       	ldi	r18, 0x15	; 21
- 2f8:	2a 95       	dec	r18
- 2fa:	f1 f7       	brne	.-4      	; 0x2f8 <__vector_11+0xc8>
- 2fc:	00 00       	nop
- 2fe:	01 96       	adiw	r24, 0x01	; 1
- 300:	20 91 60 00 	lds	r18, 0x0060
- 304:	30 91 61 00 	lds	r19, 0x0061
- 308:	82 17       	cp	r24, r18
- 30a:	93 07       	cpc	r25, r19
- 30c:	a4 f3       	brlt	.-24     	; 0x2f6 <__vector_11+0xc6>
+ 2d6:	80 91 60 00 	lds	r24, 0x0060
+ 2da:	90 91 61 00 	lds	r25, 0x0061
+ 2de:	18 16       	cp	r1, r24
+ 2e0:	19 06       	cpc	r1, r25
+ 2e2:	74 f4       	brge	.+28     	; 0x300 <__vector_11+0xde>
+ 2e4:	80 e0       	ldi	r24, 0x00	; 0
+ 2e6:	90 e0       	ldi	r25, 0x00	; 0
+ 2e8:	25 e1       	ldi	r18, 0x15	; 21
+ 2ea:	2a 95       	dec	r18
+ 2ec:	f1 f7       	brne	.-4      	; 0x2ea <__vector_11+0xc8>
+ 2ee:	00 00       	nop
+ 2f0:	01 96       	adiw	r24, 0x01	; 1
+ 2f2:	20 91 60 00 	lds	r18, 0x0060
+ 2f6:	30 91 61 00 	lds	r19, 0x0061
+ 2fa:	82 17       	cp	r24, r18
+ 2fc:	93 07       	cpc	r25, r19
+ 2fe:	a4 f3       	brlt	.-24     	; 0x2e8 <__vector_11+0xc6>
 		_delay_us(STEP);
 	}
 	PORTB &= ~(1<<PINB0);
- 30e:	c0 98       	cbi	0x18, 0	; 24
+ 300:	c0 98       	cbi	0x18, 0	; 24
 }
- 310:	9f 91       	pop	r25
- 312:	8f 91       	pop	r24
- 314:	3f 91       	pop	r19
- 316:	2f 91       	pop	r18
- 318:	0f 90       	pop	r0
- 31a:	0f be       	out	0x3f, r0	; 63
- 31c:	0f 90       	pop	r0
- 31e:	1f 90       	pop	r1
- 320:	18 95       	reti
+ 302:	9f 91       	pop	r25
+ 304:	8f 91       	pop	r24
+ 306:	3f 91       	pop	r19
+ 308:	2f 91       	pop	r18
+ 30a:	0f 90       	pop	r0
+ 30c:	0f be       	out	0x3f, r0	; 63
+ 30e:	0f 90       	pop	r0
+ 310:	1f 90       	pop	r1
+ 312:	18 95       	reti
 
-00000322 <main>:
+00000314 <main>:
 
 int main(void)
 {
 	
 	rf12_init();					// ein paar Register setzen (z.B. CLK auf 10MHz)
- 322:	2f d0       	rcall	.+94     	; 0x382 <rf12_init>
+ 314:	2f d0       	rcall	.+94     	; 0x374 <rf12_init>
 	rf12_setfreq(RF12FREQ(433.92));	// Sende/Empfangsfrequenz auf 433,92MHz einstellen
- 324:	80 e2       	ldi	r24, 0x20	; 32
- 326:	96 e0       	ldi	r25, 0x06	; 6
- 328:	6b d0       	rcall	.+214    	; 0x400 <rf12_setfreq>
+ 316:	80 e2       	ldi	r24, 0x20	; 32
+ 318:	96 e0       	ldi	r25, 0x06	; 6
+ 31a:	6b d0       	rcall	.+214    	; 0x3f2 <rf12_setfreq>
 	rf12_setbandwidth(1, 0, 7);		// 400kHz Bandbreite, 0dB Verstärkung, DRSSI threshold: -61dBm
- 32a:	47 e0       	ldi	r20, 0x07	; 7
- 32c:	60 e0       	ldi	r22, 0x00	; 0
- 32e:	81 e0       	ldi	r24, 0x01	; 1
- 330:	4b d0       	rcall	.+150    	; 0x3c8 <rf12_setbandwidth>
+ 31c:	47 e0       	ldi	r20, 0x07	; 7
+ 31e:	60 e0       	ldi	r22, 0x00	; 0
+ 320:	81 e0       	ldi	r24, 0x01	; 1
+ 322:	4b d0       	rcall	.+150    	; 0x3ba <rf12_setbandwidth>
 	rf12_setbaud(9600);				// 19200 baud
- 332:	80 e8       	ldi	r24, 0x80	; 128
- 334:	95 e2       	ldi	r25, 0x25	; 37
- 336:	73 d0       	rcall	.+230    	; 0x41e <rf12_setbaud>
+ 324:	80 e8       	ldi	r24, 0x80	; 128
+ 326:	95 e2       	ldi	r25, 0x25	; 37
+ 328:	73 d0       	rcall	.+230    	; 0x410 <rf12_setbaud>
 	rf12_setpower(0, 6);			// 1mW Ausgangsleistung, 120kHz Frequenzshift
- 338:	66 e0       	ldi	r22, 0x06	; 6
- 33a:	80 e0       	ldi	r24, 0x00	; 0
- 33c:	93 d0       	rcall	.+294    	; 0x464 <rf12_setpower>
+ 32a:	66 e0       	ldi	r22, 0x06	; 6
+ 32c:	80 e0       	ldi	r24, 0x00	; 0
+ 32e:	93 d0       	rcall	.+294    	; 0x456 <rf12_setpower>
 		
 	init_timer();
- 33e:	70 df       	rcall	.-288    	; 0x220 <init_timer>
+ 330:	70 df       	rcall	.-288    	; 0x212 <init_timer>
 	DDRB |= (1<<PINB1); //Led Auf Ausgang
- 340:	b9 9a       	sbi	0x17, 1	; 23
+ 332:	b9 9a       	sbi	0x17, 1	; 23
 	DDRA &= ~(1<<PINA4); //SCK Eingang
- 342:	d4 98       	cbi	0x1a, 4	; 26
+ 334:	d4 98       	cbi	0x1a, 4	; 26
 	PORTA |= (1<<PINA4); //SCK Pullup
- 344:	dc 9a       	sbi	0x1b, 4	; 27
+ 336:	dc 9a       	sbi	0x1b, 4	; 27
 	DDRA |= (1<<PINA6); //MOSI Ausgang
- 346:	d6 9a       	sbi	0x1a, 6	; 26
+ 338:	d6 9a       	sbi	0x1a, 6	; 26
 	PORTA &= ~(1<<PINA6); //MOSI 0
- 348:	de 98       	cbi	0x1b, 6	; 27
+ 33a:	de 98       	cbi	0x1b, 6	; 27
 	sei();
- 34a:	78 94       	sei
+ 33c:	78 94       	sei
 	
 	//DDRB |= (1<<PINB1);
     while(1)
     {
 		recive();
- 34c:	19 df       	rcall	.-462    	; 0x180 <recive>
- 34e:	fe cf       	rjmp	.-4      	; 0x34c <main+0x2a>
+ 33e:	1d df       	rcall	.-454    	; 0x17a <recive>
+ 340:	fe cf       	rjmp	.-4      	; 0x33e <main+0x2a>
 
-00000350 <rf12_trans>:
+00000342 <rf12_trans>:
 unsigned short rf12_trans(unsigned short wert)
 {	
 	unsigned short werti = 0;
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
- 350:	d9 98       	cbi	0x1b, 1	; 27
- 352:	40 e1       	ldi	r20, 0x10	; 16
+ 342:	d9 98       	cbi	0x1b, 1	; 27
+ 344:	40 e1       	ldi	r20, 0x10	; 16
 #include "rf12.h"
 #include <util/delay.h>
 
 unsigned short rf12_trans(unsigned short wert)
 {	
 	unsigned short werti = 0;
- 354:	20 e0       	ldi	r18, 0x00	; 0
- 356:	30 e0       	ldi	r19, 0x00	; 0
+ 346:	20 e0       	ldi	r18, 0x00	; 0
+ 348:	30 e0       	ldi	r19, 0x00	; 0
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
 	for (i=0; i<16; i++)
 	{	
 		if (wert&32768) {
- 358:	99 23       	and	r25, r25
- 35a:	14 f4       	brge	.+4      	; 0x360 <rf12_trans+0x10>
+ 34a:	99 23       	and	r25, r25
+ 34c:	14 f4       	brge	.+4      	; 0x352 <rf12_trans+0x10>
 			RF_PORT |= (1<<SDI);
- 35c:	db 9a       	sbi	0x1b, 3	; 27
- 35e:	01 c0       	rjmp	.+2      	; 0x362 <rf12_trans+0x12>
+ 34e:	db 9a       	sbi	0x1b, 3	; 27
+ 350:	01 c0       	rjmp	.+2      	; 0x354 <rf12_trans+0x12>
 		}		
 		else {
 			RF_PORT &= ~(1<<SDI);
- 360:	db 98       	cbi	0x1b, 3	; 27
+ 352:	db 98       	cbi	0x1b, 3	; 27
 		}			
 		werti<<=1;
- 362:	22 0f       	add	r18, r18
- 364:	33 1f       	adc	r19, r19
+ 354:	22 0f       	add	r18, r18
+ 356:	33 1f       	adc	r19, r19
 		if (RF_PIN & (1<<SDO)) {
- 366:	c8 99       	sbic	0x19, 0	; 25
+ 358:	c8 99       	sbic	0x19, 0	; 25
 			werti|=1;
- 368:	21 60       	ori	r18, 0x01	; 1
+ 35a:	21 60       	ori	r18, 0x01	; 1
 		}		
 		RF_PORT |= (1<<SCK);
- 36a:	da 9a       	sbi	0x1b, 2	; 27
+ 35c:	da 9a       	sbi	0x1b, 2	; 27
 		wert<<=1;
- 36c:	88 0f       	add	r24, r24
- 36e:	99 1f       	adc	r25, r25
- 370:	00 c0       	rjmp	.+0      	; 0x372 <rf12_trans+0x22>
- 372:	00 00       	nop
+ 35e:	88 0f       	add	r24, r24
+ 360:	99 1f       	adc	r25, r25
+ 362:	00 c0       	rjmp	.+0      	; 0x364 <rf12_trans+0x22>
+ 364:	00 00       	nop
 		_delay_us(0.3);
 		RF_PORT &= ~(1<<SCK);
- 374:	da 98       	cbi	0x1b, 2	; 27
- 376:	41 50       	subi	r20, 0x01	; 1
+ 366:	da 98       	cbi	0x1b, 2	; 27
+ 368:	41 50       	subi	r20, 0x01	; 1
 {	
 	unsigned short werti = 0;
 	unsigned char i;
 	
 	RF_PORT &= ~(1<<CS);
 	for (i=0; i<16; i++)
- 378:	79 f7       	brne	.-34     	; 0x358 <rf12_trans+0x8>
+ 36a:	79 f7       	brne	.-34     	; 0x34a <rf12_trans+0x8>
 		RF_PORT |= (1<<SCK);
 		wert<<=1;
 		_delay_us(0.3);
 		RF_PORT &= ~(1<<SCK);
 	}
 	RF_PORT |= (1<<CS);
- 37a:	d9 9a       	sbi	0x1b, 1	; 27
+ 36c:	d9 9a       	sbi	0x1b, 1	; 27
 	return werti;
 }
- 37c:	82 2f       	mov	r24, r18
- 37e:	93 2f       	mov	r25, r19
- 380:	08 95       	ret
+ 36e:	82 2f       	mov	r24, r18
+ 370:	93 2f       	mov	r25, r19
+ 372:	08 95       	ret
 
-00000382 <rf12_init>:
+00000374 <rf12_init>:
 
 void rf12_init(void)
 {
 	RF_DDR |= (1<<SDI) | (1<<SCK) | (1<<CS);
- 382:	8a b3       	in	r24, 0x1a	; 26
- 384:	8e 60       	ori	r24, 0x0E	; 14
- 386:	8a bb       	out	0x1a, r24	; 26
+ 374:	8a b3       	in	r24, 0x1a	; 26
+ 376:	8e 60       	ori	r24, 0x0E	; 14
+ 378:	8a bb       	out	0x1a, r24	; 26
 	RF_PORT |= (1<<CS);
- 388:	d9 9a       	sbi	0x1b, 1	; 27
+ 37a:	d9 9a       	sbi	0x1b, 1	; 27
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
- 38a:	2f ef       	ldi	r18, 0xFF	; 255
- 38c:	80 e7       	ldi	r24, 0x70	; 112
- 38e:	92 e0       	ldi	r25, 0x02	; 2
- 390:	21 50       	subi	r18, 0x01	; 1
- 392:	80 40       	sbci	r24, 0x00	; 0
- 394:	90 40       	sbci	r25, 0x00	; 0
- 396:	e1 f7       	brne	.-8      	; 0x390 <rf12_init+0xe>
- 398:	00 c0       	rjmp	.+0      	; 0x39a <rf12_init+0x18>
- 39a:	00 00       	nop
+ 37c:	2f ef       	ldi	r18, 0xFF	; 255
+ 37e:	80 e7       	ldi	r24, 0x70	; 112
+ 380:	92 e0       	ldi	r25, 0x02	; 2
+ 382:	21 50       	subi	r18, 0x01	; 1
+ 384:	80 40       	sbci	r24, 0x00	; 0
+ 386:	90 40       	sbci	r25, 0x00	; 0
+ 388:	e1 f7       	brne	.-8      	; 0x382 <rf12_init+0xe>
+ 38a:	00 c0       	rjmp	.+0      	; 0x38c <rf12_init+0x18>
+ 38c:	00 00       	nop
 
 	_delay_ms(100);
 
 	rf12_trans(0xC0E0);			// AVR CLK: 10MHz
- 39c:	80 ee       	ldi	r24, 0xE0	; 224
- 39e:	90 ec       	ldi	r25, 0xC0	; 192
- 3a0:	d7 df       	rcall	.-82     	; 0x350 <rf12_trans>
+ 38e:	80 ee       	ldi	r24, 0xE0	; 224
+ 390:	90 ec       	ldi	r25, 0xC0	; 192
+ 392:	d7 df       	rcall	.-82     	; 0x342 <rf12_trans>
 	rf12_trans(0x80D7);			// Enable FIFO
- 3a2:	87 ed       	ldi	r24, 0xD7	; 215
- 3a4:	90 e8       	ldi	r25, 0x80	; 128
- 3a6:	d4 df       	rcall	.-88     	; 0x350 <rf12_trans>
+ 394:	87 ed       	ldi	r24, 0xD7	; 215
+ 396:	90 e8       	ldi	r25, 0x80	; 128
+ 398:	d4 df       	rcall	.-88     	; 0x342 <rf12_trans>
 	rf12_trans(0xC2AB);			// Data Filter: internal
- 3a8:	8b ea       	ldi	r24, 0xAB	; 171
- 3aa:	92 ec       	ldi	r25, 0xC2	; 194
- 3ac:	d1 df       	rcall	.-94     	; 0x350 <rf12_trans>
+ 39a:	8b ea       	ldi	r24, 0xAB	; 171
+ 39c:	92 ec       	ldi	r25, 0xC2	; 194
+ 39e:	d1 df       	rcall	.-94     	; 0x342 <rf12_trans>
 	rf12_trans(0xCA81);			// Set FIFO mode
- 3ae:	81 e8       	ldi	r24, 0x81	; 129
- 3b0:	9a ec       	ldi	r25, 0xCA	; 202
- 3b2:	ce df       	rcall	.-100    	; 0x350 <rf12_trans>
+ 3a0:	81 e8       	ldi	r24, 0x81	; 129
+ 3a2:	9a ec       	ldi	r25, 0xCA	; 202
+ 3a4:	ce df       	rcall	.-100    	; 0x342 <rf12_trans>
 	rf12_trans(0xE000);			// disable wakeuptimer
- 3b4:	80 e0       	ldi	r24, 0x00	; 0
- 3b6:	90 ee       	ldi	r25, 0xE0	; 224
- 3b8:	cb df       	rcall	.-106    	; 0x350 <rf12_trans>
+ 3a6:	80 e0       	ldi	r24, 0x00	; 0
+ 3a8:	90 ee       	ldi	r25, 0xE0	; 224
+ 3aa:	cb df       	rcall	.-106    	; 0x342 <rf12_trans>
 	rf12_trans(0xC800);			// disable low duty cycle
- 3ba:	80 e0       	ldi	r24, 0x00	; 0
- 3bc:	98 ec       	ldi	r25, 0xC8	; 200
- 3be:	c8 df       	rcall	.-112    	; 0x350 <rf12_trans>
+ 3ac:	80 e0       	ldi	r24, 0x00	; 0
+ 3ae:	98 ec       	ldi	r25, 0xC8	; 200
+ 3b0:	c8 df       	rcall	.-112    	; 0x342 <rf12_trans>
 	rf12_trans(0xC4F7);			// AFC settings: autotuning: -10kHz...+7,5kHz
- 3c0:	87 ef       	ldi	r24, 0xF7	; 247
- 3c2:	94 ec       	ldi	r25, 0xC4	; 196
- 3c4:	c5 df       	rcall	.-118    	; 0x350 <rf12_trans>
- 3c6:	08 95       	ret
+ 3b2:	87 ef       	ldi	r24, 0xF7	; 247
+ 3b4:	94 ec       	ldi	r25, 0xC4	; 196
+ 3b6:	c5 df       	rcall	.-118    	; 0x342 <rf12_trans>
+ 3b8:	08 95       	ret
 
-000003c8 <rf12_setbandwidth>:
+000003ba <rf12_setbandwidth>:
 }
 
 void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
 {
 	rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
- 3c8:	47 70       	andi	r20, 0x07	; 7
- 3ca:	50 e0       	ldi	r21, 0x00	; 0
- 3cc:	54 69       	ori	r21, 0x94	; 148
- 3ce:	63 70       	andi	r22, 0x03	; 3
- 3d0:	26 2f       	mov	r18, r22
- 3d2:	30 e0       	ldi	r19, 0x00	; 0
- 3d4:	22 0f       	add	r18, r18
- 3d6:	33 1f       	adc	r19, r19
- 3d8:	22 0f       	add	r18, r18
- 3da:	33 1f       	adc	r19, r19
- 3dc:	22 0f       	add	r18, r18
- 3de:	33 1f       	adc	r19, r19
- 3e0:	90 e0       	ldi	r25, 0x00	; 0
- 3e2:	88 0f       	add	r24, r24
- 3e4:	99 1f       	adc	r25, r25
- 3e6:	82 95       	swap	r24
- 3e8:	92 95       	swap	r25
- 3ea:	90 7f       	andi	r25, 0xF0	; 240
- 3ec:	98 27       	eor	r25, r24
- 3ee:	80 7f       	andi	r24, 0xF0	; 240
- 3f0:	98 27       	eor	r25, r24
- 3f2:	99 27       	eor	r25, r25
- 3f4:	82 2b       	or	r24, r18
- 3f6:	93 2b       	or	r25, r19
- 3f8:	84 2b       	or	r24, r20
- 3fa:	95 2b       	or	r25, r21
- 3fc:	a9 df       	rcall	.-174    	; 0x350 <rf12_trans>
- 3fe:	08 95       	ret
+ 3ba:	47 70       	andi	r20, 0x07	; 7
+ 3bc:	50 e0       	ldi	r21, 0x00	; 0
+ 3be:	54 69       	ori	r21, 0x94	; 148
+ 3c0:	63 70       	andi	r22, 0x03	; 3
+ 3c2:	26 2f       	mov	r18, r22
+ 3c4:	30 e0       	ldi	r19, 0x00	; 0
+ 3c6:	22 0f       	add	r18, r18
+ 3c8:	33 1f       	adc	r19, r19
+ 3ca:	22 0f       	add	r18, r18
+ 3cc:	33 1f       	adc	r19, r19
+ 3ce:	22 0f       	add	r18, r18
+ 3d0:	33 1f       	adc	r19, r19
+ 3d2:	90 e0       	ldi	r25, 0x00	; 0
+ 3d4:	88 0f       	add	r24, r24
+ 3d6:	99 1f       	adc	r25, r25
+ 3d8:	82 95       	swap	r24
+ 3da:	92 95       	swap	r25
+ 3dc:	90 7f       	andi	r25, 0xF0	; 240
+ 3de:	98 27       	eor	r25, r24
+ 3e0:	80 7f       	andi	r24, 0xF0	; 240
+ 3e2:	98 27       	eor	r25, r24
+ 3e4:	99 27       	eor	r25, r25
+ 3e6:	82 2b       	or	r24, r18
+ 3e8:	93 2b       	or	r25, r19
+ 3ea:	84 2b       	or	r24, r20
+ 3ec:	95 2b       	or	r25, r21
+ 3ee:	a9 df       	rcall	.-174    	; 0x342 <rf12_trans>
+ 3f0:	08 95       	ret
 
-00000400 <rf12_setfreq>:
+000003f2 <rf12_setfreq>:
 }
 
 void rf12_setfreq(unsigned short freq)
 {	
 	if (freq<96) {				// 430,2400MHz
- 400:	80 36       	cpi	r24, 0x60	; 96
- 402:	91 05       	cpc	r25, r1
- 404:	38 f0       	brcs	.+14     	; 0x414 <rf12_setfreq+0x14>
- 406:	80 34       	cpi	r24, 0x40	; 64
- 408:	2f e0       	ldi	r18, 0x0F	; 15
- 40a:	92 07       	cpc	r25, r18
- 40c:	28 f0       	brcs	.+10     	; 0x418 <rf12_setfreq+0x18>
- 40e:	8f e3       	ldi	r24, 0x3F	; 63
- 410:	9f e0       	ldi	r25, 0x0F	; 15
- 412:	02 c0       	rjmp	.+4      	; 0x418 <rf12_setfreq+0x18>
+ 3f2:	80 36       	cpi	r24, 0x60	; 96
+ 3f4:	91 05       	cpc	r25, r1
+ 3f6:	38 f0       	brcs	.+14     	; 0x406 <rf12_setfreq+0x14>
+ 3f8:	80 34       	cpi	r24, 0x40	; 64
+ 3fa:	2f e0       	ldi	r18, 0x0F	; 15
+ 3fc:	92 07       	cpc	r25, r18
+ 3fe:	28 f0       	brcs	.+10     	; 0x40a <rf12_setfreq+0x18>
+ 400:	8f e3       	ldi	r24, 0x3F	; 63
+ 402:	9f e0       	ldi	r25, 0x0F	; 15
+ 404:	02 c0       	rjmp	.+4      	; 0x40a <rf12_setfreq+0x18>
 		freq=96;
- 414:	80 e6       	ldi	r24, 0x60	; 96
- 416:	90 e0       	ldi	r25, 0x00	; 0
+ 406:	80 e6       	ldi	r24, 0x60	; 96
+ 408:	90 e0       	ldi	r25, 0x00	; 0
 	} else if (freq>3903) {		// 439,7575MHz
 		freq=3903;
 	}	
 	rf12_trans(0xA000|freq);
- 418:	90 6a       	ori	r25, 0xA0	; 160
- 41a:	9a df       	rcall	.-204    	; 0x350 <rf12_trans>
- 41c:	08 95       	ret
+ 40a:	90 6a       	ori	r25, 0xA0	; 160
+ 40c:	9a df       	rcall	.-204    	; 0x342 <rf12_trans>
+ 40e:	08 95       	ret
 
-0000041e <rf12_setbaud>:
+00000410 <rf12_setbaud>:
 }
 
 void rf12_setbaud(unsigned short baud)
 {
 	if (baud<663) {
- 41e:	87 39       	cpi	r24, 0x97	; 151
- 420:	22 e0       	ldi	r18, 0x02	; 2
- 422:	92 07       	cpc	r25, r18
- 424:	f0 f0       	brcs	.+60     	; 0x462 <rf12_setbaud+0x44>
+ 410:	87 39       	cpi	r24, 0x97	; 151
+ 412:	22 e0       	ldi	r18, 0x02	; 2
+ 414:	92 07       	cpc	r25, r18
+ 416:	f0 f0       	brcs	.+60     	; 0x454 <rf12_setbaud+0x44>
 		return;
 	}	
 	if (baud<5400) {				// Baudrate= 344827,58621/(R+1)/(1+CS*7)
- 426:	88 31       	cpi	r24, 0x18	; 24
- 428:	25 e1       	ldi	r18, 0x15	; 21
- 42a:	92 07       	cpc	r25, r18
- 42c:	70 f4       	brcc	.+28     	; 0x44a <rf12_setbaud+0x2c>
+ 418:	88 31       	cpi	r24, 0x18	; 24
+ 41a:	25 e1       	ldi	r18, 0x15	; 21
+ 41c:	92 07       	cpc	r25, r18
+ 41e:	70 f4       	brcc	.+28     	; 0x43c <rf12_setbaud+0x2c>
 		rf12_trans(0xC680|((43104/baud)-1));
- 42e:	9c 01       	movw	r18, r24
- 430:	40 e0       	ldi	r20, 0x00	; 0
- 432:	50 e0       	ldi	r21, 0x00	; 0
- 434:	60 e6       	ldi	r22, 0x60	; 96
- 436:	78 ea       	ldi	r23, 0xA8	; 168
- 438:	80 e0       	ldi	r24, 0x00	; 0
- 43a:	90 e0       	ldi	r25, 0x00	; 0
- 43c:	a0 d0       	rcall	.+320    	; 0x57e <__divmodsi4>
- 43e:	c9 01       	movw	r24, r18
- 440:	01 97       	sbiw	r24, 0x01	; 1
- 442:	80 68       	ori	r24, 0x80	; 128
- 444:	96 6c       	ori	r25, 0xC6	; 198
- 446:	84 df       	rcall	.-248    	; 0x350 <rf12_trans>
- 448:	08 95       	ret
+ 420:	9c 01       	movw	r18, r24
+ 422:	40 e0       	ldi	r20, 0x00	; 0
+ 424:	50 e0       	ldi	r21, 0x00	; 0
+ 426:	60 e6       	ldi	r22, 0x60	; 96
+ 428:	78 ea       	ldi	r23, 0xA8	; 168
+ 42a:	80 e0       	ldi	r24, 0x00	; 0
+ 42c:	90 e0       	ldi	r25, 0x00	; 0
+ 42e:	a0 d0       	rcall	.+320    	; 0x570 <__divmodsi4>
+ 430:	c9 01       	movw	r24, r18
+ 432:	01 97       	sbiw	r24, 0x01	; 1
+ 434:	80 68       	ori	r24, 0x80	; 128
+ 436:	96 6c       	ori	r25, 0xC6	; 198
+ 438:	84 df       	rcall	.-248    	; 0x342 <rf12_trans>
+ 43a:	08 95       	ret
 	} else {
 		rf12_trans(0xC600|((344828UL/baud)-1));
- 44a:	9c 01       	movw	r18, r24
- 44c:	40 e0       	ldi	r20, 0x00	; 0
- 44e:	50 e0       	ldi	r21, 0x00	; 0
- 450:	6c ef       	ldi	r22, 0xFC	; 252
- 452:	72 e4       	ldi	r23, 0x42	; 66
- 454:	85 e0       	ldi	r24, 0x05	; 5
- 456:	90 e0       	ldi	r25, 0x00	; 0
- 458:	70 d0       	rcall	.+224    	; 0x53a <__udivmodsi4>
- 45a:	c9 01       	movw	r24, r18
- 45c:	01 97       	sbiw	r24, 0x01	; 1
- 45e:	96 6c       	ori	r25, 0xC6	; 198
- 460:	77 df       	rcall	.-274    	; 0x350 <rf12_trans>
- 462:	08 95       	ret
+ 43c:	9c 01       	movw	r18, r24
+ 43e:	40 e0       	ldi	r20, 0x00	; 0
+ 440:	50 e0       	ldi	r21, 0x00	; 0
+ 442:	6c ef       	ldi	r22, 0xFC	; 252
+ 444:	72 e4       	ldi	r23, 0x42	; 66
+ 446:	85 e0       	ldi	r24, 0x05	; 5
+ 448:	90 e0       	ldi	r25, 0x00	; 0
+ 44a:	70 d0       	rcall	.+224    	; 0x52c <__udivmodsi4>
+ 44c:	c9 01       	movw	r24, r18
+ 44e:	01 97       	sbiw	r24, 0x01	; 1
+ 450:	96 6c       	ori	r25, 0xC6	; 198
+ 452:	77 df       	rcall	.-274    	; 0x342 <rf12_trans>
+ 454:	08 95       	ret
 
-00000464 <rf12_setpower>:
+00000456 <rf12_setpower>:
 	}	
 }
 
 void rf12_setpower(unsigned char power, unsigned char mod)
 {
 	rf12_trans(0x9800|(power&7)|((mod&15)<<4));
- 464:	87 70       	andi	r24, 0x07	; 7
- 466:	90 e0       	ldi	r25, 0x00	; 0
- 468:	98 69       	ori	r25, 0x98	; 152
- 46a:	70 e0       	ldi	r23, 0x00	; 0
- 46c:	62 95       	swap	r22
- 46e:	72 95       	swap	r23
- 470:	70 7f       	andi	r23, 0xF0	; 240
- 472:	76 27       	eor	r23, r22
- 474:	60 7f       	andi	r22, 0xF0	; 240
- 476:	76 27       	eor	r23, r22
- 478:	77 27       	eor	r23, r23
- 47a:	86 2b       	or	r24, r22
- 47c:	97 2b       	or	r25, r23
- 47e:	68 df       	rcall	.-304    	; 0x350 <rf12_trans>
- 480:	08 95       	ret
+ 456:	87 70       	andi	r24, 0x07	; 7
+ 458:	90 e0       	ldi	r25, 0x00	; 0
+ 45a:	98 69       	ori	r25, 0x98	; 152
+ 45c:	70 e0       	ldi	r23, 0x00	; 0
+ 45e:	62 95       	swap	r22
+ 460:	72 95       	swap	r23
+ 462:	70 7f       	andi	r23, 0xF0	; 240
+ 464:	76 27       	eor	r23, r22
+ 466:	60 7f       	andi	r22, 0xF0	; 240
+ 468:	76 27       	eor	r23, r22
+ 46a:	77 27       	eor	r23, r23
+ 46c:	86 2b       	or	r24, r22
+ 46e:	97 2b       	or	r25, r23
+ 470:	68 df       	rcall	.-304    	; 0x342 <rf12_trans>
+ 472:	08 95       	ret
 
-00000482 <rf12_ready>:
+00000474 <rf12_ready>:
 }
 
 void rf12_ready(void)
 {	
 	RF_PORT &= ~(1<<CS);
- 482:	d9 98       	cbi	0x1b, 1	; 27
+ 474:	d9 98       	cbi	0x1b, 1	; 27
 	while (!(RF_PIN & (1<<SDO))); // wait until FIFO ready
- 484:	c8 9b       	sbis	0x19, 0	; 25
- 486:	fe cf       	rjmp	.-4      	; 0x484 <rf12_ready+0x2>
+ 476:	c8 9b       	sbis	0x19, 0	; 25
+ 478:	fe cf       	rjmp	.-4      	; 0x476 <rf12_ready+0x2>
 }
- 488:	08 95       	ret
+ 47a:	08 95       	ret
 
-0000048a <rf12_beginasyncrx>:
+0000047c <rf12_beginasyncrx>:
 
 void rf12_beginasyncrx() {
 	rf12_trans(0x82C8);			// RX on
- 48a:	88 ec       	ldi	r24, 0xC8	; 200
- 48c:	92 e8       	ldi	r25, 0x82	; 130
- 48e:	60 df       	rcall	.-320    	; 0x350 <rf12_trans>
+ 47c:	88 ec       	ldi	r24, 0xC8	; 200
+ 47e:	92 e8       	ldi	r25, 0x82	; 130
+ 480:	60 df       	rcall	.-320    	; 0x342 <rf12_trans>
 	rf12_trans(0xCA81);			// set FIFO mode
- 490:	81 e8       	ldi	r24, 0x81	; 129
- 492:	9a ec       	ldi	r25, 0xCA	; 202
- 494:	5d df       	rcall	.-326    	; 0x350 <rf12_trans>
+ 482:	81 e8       	ldi	r24, 0x81	; 129
+ 484:	9a ec       	ldi	r25, 0xCA	; 202
+ 486:	5d df       	rcall	.-326    	; 0x342 <rf12_trans>
 	rf12_trans(0xCA83);			// enable FIFO
- 496:	83 e8       	ldi	r24, 0x83	; 131
- 498:	9a ec       	ldi	r25, 0xCA	; 202
- 49a:	5a df       	rcall	.-332    	; 0x350 <rf12_trans>
- 49c:	08 95       	ret
+ 488:	83 e8       	ldi	r24, 0x83	; 131
+ 48a:	9a ec       	ldi	r25, 0xCA	; 202
+ 48c:	5a df       	rcall	.-332    	; 0x342 <rf12_trans>
+ 48e:	08 95       	ret
 
-0000049e <rf12_hasdata>:
+00000490 <rf12_hasdata>:
 }
 uint8_t rf12_hasdata() {
 	RF_PORT &= ~(1<<CS);
- 49e:	d9 98       	cbi	0x1b, 1	; 27
+ 490:	d9 98       	cbi	0x1b, 1	; 27
 	return !(RF_PIN & (1<<SDO));
- 4a0:	89 b3       	in	r24, 0x19	; 25
- 4a2:	80 95       	com	r24
+ 492:	89 b3       	in	r24, 0x19	; 25
+ 494:	80 95       	com	r24
 }
- 4a4:	81 70       	andi	r24, 0x01	; 1
- 4a6:	08 95       	ret
+ 496:	81 70       	andi	r24, 0x01	; 1
+ 498:	08 95       	ret
 
-000004a8 <rf12_rxbyte>:
+0000049a <rf12_rxbyte>:
 uint8_t rf12_rxbyte() {
 	return rf12_trans(0xB000);
- 4a8:	80 e0       	ldi	r24, 0x00	; 0
- 4aa:	90 eb       	ldi	r25, 0xB0	; 176
- 4ac:	51 df       	rcall	.-350    	; 0x350 <rf12_trans>
+ 49a:	80 e0       	ldi	r24, 0x00	; 0
+ 49c:	90 eb       	ldi	r25, 0xB0	; 176
+ 49e:	51 df       	rcall	.-350    	; 0x342 <rf12_trans>
 }
- 4ae:	08 95       	ret
+ 4a0:	08 95       	ret
 
-000004b0 <rf12_endasyncrx>:
+000004a2 <rf12_endasyncrx>:
 void rf12_endasyncrx() {
 	rf12_trans(0x8208);			// RX off
- 4b0:	88 e0       	ldi	r24, 0x08	; 8
- 4b2:	92 e8       	ldi	r25, 0x82	; 130
- 4b4:	4d df       	rcall	.-358    	; 0x350 <rf12_trans>
- 4b6:	08 95       	ret
+ 4a2:	88 e0       	ldi	r24, 0x08	; 8
+ 4a4:	92 e8       	ldi	r25, 0x82	; 130
+ 4a6:	4d df       	rcall	.-358    	; 0x342 <rf12_trans>
+ 4a8:	08 95       	ret
 
-000004b8 <rf12_txpacket>:
+000004aa <rf12_txpacket>:
 		*data++=rf12_trans(0xB000);
 	}
 	rf12_trans(0x8208);			// RX off
 }
 
 void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) {
- 4b8:	1f 93       	push	r17
- 4ba:	cf 93       	push	r28
- 4bc:	df 93       	push	r29
- 4be:	18 2f       	mov	r17, r24
- 4c0:	d6 2f       	mov	r29, r22
- 4c2:	c4 2f       	mov	r28, r20
+ 4aa:	1f 93       	push	r17
+ 4ac:	cf 93       	push	r28
+ 4ae:	df 93       	push	r29
+ 4b0:	18 2f       	mov	r17, r24
+ 4b2:	d6 2f       	mov	r29, r22
+ 4b4:	c4 2f       	mov	r28, r20
 	rf12_trans(0x8238);			// TX on
- 4c4:	88 e3       	ldi	r24, 0x38	; 56
- 4c6:	92 e8       	ldi	r25, 0x82	; 130
- 4c8:	43 df       	rcall	.-378    	; 0x350 <rf12_trans>
+ 4b6:	88 e3       	ldi	r24, 0x38	; 56
+ 4b8:	92 e8       	ldi	r25, 0x82	; 130
+ 4ba:	43 df       	rcall	.-378    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4ca:	db df       	rcall	.-74     	; 0x482 <rf12_ready>
+ 4bc:	db df       	rcall	.-74     	; 0x474 <rf12_ready>
 	rf12_trans(0xB8AA);
- 4cc:	8a ea       	ldi	r24, 0xAA	; 170
- 4ce:	98 eb       	ldi	r25, 0xB8	; 184
- 4d0:	3f df       	rcall	.-386    	; 0x350 <rf12_trans>
+ 4be:	8a ea       	ldi	r24, 0xAA	; 170
+ 4c0:	98 eb       	ldi	r25, 0xB8	; 184
+ 4c2:	3f df       	rcall	.-386    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4d2:	d7 df       	rcall	.-82     	; 0x482 <rf12_ready>
+ 4c4:	d7 df       	rcall	.-82     	; 0x474 <rf12_ready>
 	rf12_trans(0xB8AA);
- 4d4:	8a ea       	ldi	r24, 0xAA	; 170
- 4d6:	98 eb       	ldi	r25, 0xB8	; 184
- 4d8:	3b df       	rcall	.-394    	; 0x350 <rf12_trans>
+ 4c6:	8a ea       	ldi	r24, 0xAA	; 170
+ 4c8:	98 eb       	ldi	r25, 0xB8	; 184
+ 4ca:	3b df       	rcall	.-394    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4da:	d3 df       	rcall	.-90     	; 0x482 <rf12_ready>
+ 4cc:	d3 df       	rcall	.-90     	; 0x474 <rf12_ready>
 	rf12_trans(0xB8AA);
- 4dc:	8a ea       	ldi	r24, 0xAA	; 170
- 4de:	98 eb       	ldi	r25, 0xB8	; 184
- 4e0:	37 df       	rcall	.-402    	; 0x350 <rf12_trans>
+ 4ce:	8a ea       	ldi	r24, 0xAA	; 170
+ 4d0:	98 eb       	ldi	r25, 0xB8	; 184
+ 4d2:	37 df       	rcall	.-402    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4e2:	cf df       	rcall	.-98     	; 0x482 <rf12_ready>
+ 4d4:	cf df       	rcall	.-98     	; 0x474 <rf12_ready>
 	rf12_trans(0xB82D);
- 4e4:	8d e2       	ldi	r24, 0x2D	; 45
- 4e6:	98 eb       	ldi	r25, 0xB8	; 184
- 4e8:	33 df       	rcall	.-410    	; 0x350 <rf12_trans>
+ 4d6:	8d e2       	ldi	r24, 0x2D	; 45
+ 4d8:	98 eb       	ldi	r25, 0xB8	; 184
+ 4da:	33 df       	rcall	.-410    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4ea:	cb df       	rcall	.-106    	; 0x482 <rf12_ready>
+ 4dc:	cb df       	rcall	.-106    	; 0x474 <rf12_ready>
 	rf12_trans(0xB8D4);
- 4ec:	84 ed       	ldi	r24, 0xD4	; 212
- 4ee:	98 eb       	ldi	r25, 0xB8	; 184
- 4f0:	2f df       	rcall	.-418    	; 0x350 <rf12_trans>
+ 4de:	84 ed       	ldi	r24, 0xD4	; 212
+ 4e0:	98 eb       	ldi	r25, 0xB8	; 184
+ 4e2:	2f df       	rcall	.-418    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4f2:	c7 df       	rcall	.-114    	; 0x482 <rf12_ready>
+ 4e4:	c7 df       	rcall	.-114    	; 0x474 <rf12_ready>
 	rf12_trans(0xB800|addr);
- 4f4:	81 2f       	mov	r24, r17
- 4f6:	90 e0       	ldi	r25, 0x00	; 0
- 4f8:	98 6b       	ori	r25, 0xB8	; 184
- 4fa:	2a df       	rcall	.-428    	; 0x350 <rf12_trans>
+ 4e6:	81 2f       	mov	r24, r17
+ 4e8:	90 e0       	ldi	r25, 0x00	; 0
+ 4ea:	98 6b       	ori	r25, 0xB8	; 184
+ 4ec:	2a df       	rcall	.-428    	; 0x342 <rf12_trans>
 	rf12_ready();
- 4fc:	c2 df       	rcall	.-124    	; 0x482 <rf12_ready>
+ 4ee:	c2 df       	rcall	.-124    	; 0x474 <rf12_ready>
 	rf12_trans(0xB800|from);
- 4fe:	8d 2f       	mov	r24, r29
- 500:	90 e0       	ldi	r25, 0x00	; 0
- 502:	98 6b       	ori	r25, 0xB8	; 184
- 504:	25 df       	rcall	.-438    	; 0x350 <rf12_trans>
+ 4f0:	8d 2f       	mov	r24, r29
+ 4f2:	90 e0       	ldi	r25, 0x00	; 0
+ 4f4:	98 6b       	ori	r25, 0xB8	; 184
+ 4f6:	25 df       	rcall	.-438    	; 0x342 <rf12_trans>
 	rf12_ready();
- 506:	bd df       	rcall	.-134    	; 0x482 <rf12_ready>
+ 4f8:	bd df       	rcall	.-134    	; 0x474 <rf12_ready>
 	rf12_trans(0xB800|data);
- 508:	8c 2f       	mov	r24, r28
- 50a:	90 e0       	ldi	r25, 0x00	; 0
- 50c:	98 6b       	ori	r25, 0xB8	; 184
- 50e:	20 df       	rcall	.-448    	; 0x350 <rf12_trans>
+ 4fa:	8c 2f       	mov	r24, r28
+ 4fc:	90 e0       	ldi	r25, 0x00	; 0
+ 4fe:	98 6b       	ori	r25, 0xB8	; 184
+ 500:	20 df       	rcall	.-448    	; 0x342 <rf12_trans>
 	rf12_ready();
- 510:	b8 df       	rcall	.-144    	; 0x482 <rf12_ready>
+ 502:	b8 df       	rcall	.-144    	; 0x474 <rf12_ready>
 	rf12_trans(0xB800);
- 512:	80 e0       	ldi	r24, 0x00	; 0
- 514:	98 eb       	ldi	r25, 0xB8	; 184
- 516:	1c df       	rcall	.-456    	; 0x350 <rf12_trans>
+ 504:	80 e0       	ldi	r24, 0x00	; 0
+ 506:	98 eb       	ldi	r25, 0xB8	; 184
+ 508:	1c df       	rcall	.-456    	; 0x342 <rf12_trans>
 	rf12_ready();
- 518:	b4 df       	rcall	.-152    	; 0x482 <rf12_ready>
+ 50a:	b4 df       	rcall	.-152    	; 0x474 <rf12_ready>
 	rf12_trans(0x8208); // TX off
- 51a:	88 e0       	ldi	r24, 0x08	; 8
- 51c:	92 e8       	ldi	r25, 0x82	; 130
- 51e:	18 df       	rcall	.-464    	; 0x350 <rf12_trans>
- 520:	2f ef       	ldi	r18, 0xFF	; 255
- 522:	80 e7       	ldi	r24, 0x70	; 112
- 524:	92 e0       	ldi	r25, 0x02	; 2
- 526:	21 50       	subi	r18, 0x01	; 1
- 528:	80 40       	sbci	r24, 0x00	; 0
- 52a:	90 40       	sbci	r25, 0x00	; 0
- 52c:	e1 f7       	brne	.-8      	; 0x526 <rf12_txpacket+0x6e>
- 52e:	00 c0       	rjmp	.+0      	; 0x530 <rf12_txpacket+0x78>
- 530:	00 00       	nop
+ 50c:	88 e0       	ldi	r24, 0x08	; 8
+ 50e:	92 e8       	ldi	r25, 0x82	; 130
+ 510:	18 df       	rcall	.-464    	; 0x342 <rf12_trans>
+ 512:	2f ef       	ldi	r18, 0xFF	; 255
+ 514:	80 e7       	ldi	r24, 0x70	; 112
+ 516:	92 e0       	ldi	r25, 0x02	; 2
+ 518:	21 50       	subi	r18, 0x01	; 1
+ 51a:	80 40       	sbci	r24, 0x00	; 0
+ 51c:	90 40       	sbci	r25, 0x00	; 0
+ 51e:	e1 f7       	brne	.-8      	; 0x518 <rf12_txpacket+0x6e>
+ 520:	00 c0       	rjmp	.+0      	; 0x522 <rf12_txpacket+0x78>
+ 522:	00 00       	nop
 	_delay_ms(100);
- 532:	df 91       	pop	r29
- 534:	cf 91       	pop	r28
- 536:	1f 91       	pop	r17
- 538:	08 95       	ret
+ 524:	df 91       	pop	r29
+ 526:	cf 91       	pop	r28
+ 528:	1f 91       	pop	r17
+ 52a:	08 95       	ret
 
-0000053a <__udivmodsi4>:
- 53a:	a1 e2       	ldi	r26, 0x21	; 33
- 53c:	1a 2e       	mov	r1, r26
- 53e:	aa 1b       	sub	r26, r26
- 540:	bb 1b       	sub	r27, r27
- 542:	fd 01       	movw	r30, r26
- 544:	0d c0       	rjmp	.+26     	; 0x560 <__udivmodsi4_ep>
+0000052c <__udivmodsi4>:
+ 52c:	a1 e2       	ldi	r26, 0x21	; 33
+ 52e:	1a 2e       	mov	r1, r26
+ 530:	aa 1b       	sub	r26, r26
+ 532:	bb 1b       	sub	r27, r27
+ 534:	fd 01       	movw	r30, r26
+ 536:	0d c0       	rjmp	.+26     	; 0x552 <__udivmodsi4_ep>
 
-00000546 <__udivmodsi4_loop>:
- 546:	aa 1f       	adc	r26, r26
- 548:	bb 1f       	adc	r27, r27
- 54a:	ee 1f       	adc	r30, r30
- 54c:	ff 1f       	adc	r31, r31
- 54e:	a2 17       	cp	r26, r18
- 550:	b3 07       	cpc	r27, r19
- 552:	e4 07       	cpc	r30, r20
- 554:	f5 07       	cpc	r31, r21
- 556:	20 f0       	brcs	.+8      	; 0x560 <__udivmodsi4_ep>
- 558:	a2 1b       	sub	r26, r18
- 55a:	b3 0b       	sbc	r27, r19
- 55c:	e4 0b       	sbc	r30, r20
- 55e:	f5 0b       	sbc	r31, r21
+00000538 <__udivmodsi4_loop>:
+ 538:	aa 1f       	adc	r26, r26
+ 53a:	bb 1f       	adc	r27, r27
+ 53c:	ee 1f       	adc	r30, r30
+ 53e:	ff 1f       	adc	r31, r31
+ 540:	a2 17       	cp	r26, r18
+ 542:	b3 07       	cpc	r27, r19
+ 544:	e4 07       	cpc	r30, r20
+ 546:	f5 07       	cpc	r31, r21
+ 548:	20 f0       	brcs	.+8      	; 0x552 <__udivmodsi4_ep>
+ 54a:	a2 1b       	sub	r26, r18
+ 54c:	b3 0b       	sbc	r27, r19
+ 54e:	e4 0b       	sbc	r30, r20
+ 550:	f5 0b       	sbc	r31, r21
 
-00000560 <__udivmodsi4_ep>:
- 560:	66 1f       	adc	r22, r22
- 562:	77 1f       	adc	r23, r23
- 564:	88 1f       	adc	r24, r24
- 566:	99 1f       	adc	r25, r25
- 568:	1a 94       	dec	r1
- 56a:	69 f7       	brne	.-38     	; 0x546 <__udivmodsi4_loop>
- 56c:	60 95       	com	r22
- 56e:	70 95       	com	r23
- 570:	80 95       	com	r24
- 572:	90 95       	com	r25
- 574:	9b 01       	movw	r18, r22
- 576:	ac 01       	movw	r20, r24
- 578:	bd 01       	movw	r22, r26
- 57a:	cf 01       	movw	r24, r30
- 57c:	08 95       	ret
+00000552 <__udivmodsi4_ep>:
+ 552:	66 1f       	adc	r22, r22
+ 554:	77 1f       	adc	r23, r23
+ 556:	88 1f       	adc	r24, r24
+ 558:	99 1f       	adc	r25, r25
+ 55a:	1a 94       	dec	r1
+ 55c:	69 f7       	brne	.-38     	; 0x538 <__udivmodsi4_loop>
+ 55e:	60 95       	com	r22
+ 560:	70 95       	com	r23
+ 562:	80 95       	com	r24
+ 564:	90 95       	com	r25
+ 566:	9b 01       	movw	r18, r22
+ 568:	ac 01       	movw	r20, r24
+ 56a:	bd 01       	movw	r22, r26
+ 56c:	cf 01       	movw	r24, r30
+ 56e:	08 95       	ret
 
-0000057e <__divmodsi4>:
- 57e:	05 2e       	mov	r0, r21
- 580:	97 fb       	bst	r25, 7
- 582:	16 f4       	brtc	.+4      	; 0x588 <__divmodsi4+0xa>
- 584:	00 94       	com	r0
- 586:	06 d0       	rcall	.+12     	; 0x594 <__divmodsi4_neg1>
- 588:	57 fd       	sbrc	r21, 7
- 58a:	0c d0       	rcall	.+24     	; 0x5a4 <__divmodsi4_neg2>
- 58c:	d6 df       	rcall	.-84     	; 0x53a <__udivmodsi4>
- 58e:	07 fc       	sbrc	r0, 7
- 590:	09 d0       	rcall	.+18     	; 0x5a4 <__divmodsi4_neg2>
- 592:	7e f4       	brtc	.+30     	; 0x5b2 <__divmodsi4_exit>
+00000570 <__divmodsi4>:
+ 570:	05 2e       	mov	r0, r21
+ 572:	97 fb       	bst	r25, 7
+ 574:	16 f4       	brtc	.+4      	; 0x57a <__divmodsi4+0xa>
+ 576:	00 94       	com	r0
+ 578:	06 d0       	rcall	.+12     	; 0x586 <__divmodsi4_neg1>
+ 57a:	57 fd       	sbrc	r21, 7
+ 57c:	0c d0       	rcall	.+24     	; 0x596 <__divmodsi4_neg2>
+ 57e:	d6 df       	rcall	.-84     	; 0x52c <__udivmodsi4>
+ 580:	07 fc       	sbrc	r0, 7
+ 582:	09 d0       	rcall	.+18     	; 0x596 <__divmodsi4_neg2>
+ 584:	7e f4       	brtc	.+30     	; 0x5a4 <__divmodsi4_exit>
 
-00000594 <__divmodsi4_neg1>:
- 594:	90 95       	com	r25
- 596:	80 95       	com	r24
- 598:	70 95       	com	r23
- 59a:	61 95       	neg	r22
- 59c:	7f 4f       	sbci	r23, 0xFF	; 255
- 59e:	8f 4f       	sbci	r24, 0xFF	; 255
- 5a0:	9f 4f       	sbci	r25, 0xFF	; 255
- 5a2:	08 95       	ret
+00000586 <__divmodsi4_neg1>:
+ 586:	90 95       	com	r25
+ 588:	80 95       	com	r24
+ 58a:	70 95       	com	r23
+ 58c:	61 95       	neg	r22
+ 58e:	7f 4f       	sbci	r23, 0xFF	; 255
+ 590:	8f 4f       	sbci	r24, 0xFF	; 255
+ 592:	9f 4f       	sbci	r25, 0xFF	; 255
+ 594:	08 95       	ret
 
-000005a4 <__divmodsi4_neg2>:
- 5a4:	50 95       	com	r21
- 5a6:	40 95       	com	r20
- 5a8:	30 95       	com	r19
- 5aa:	21 95       	neg	r18
- 5ac:	3f 4f       	sbci	r19, 0xFF	; 255
- 5ae:	4f 4f       	sbci	r20, 0xFF	; 255
- 5b0:	5f 4f       	sbci	r21, 0xFF	; 255
+00000596 <__divmodsi4_neg2>:
+ 596:	50 95       	com	r21
+ 598:	40 95       	com	r20
+ 59a:	30 95       	com	r19
+ 59c:	21 95       	neg	r18
+ 59e:	3f 4f       	sbci	r19, 0xFF	; 255
+ 5a0:	4f 4f       	sbci	r20, 0xFF	; 255
+ 5a2:	5f 4f       	sbci	r21, 0xFF	; 255
 
-000005b2 <__divmodsi4_exit>:
- 5b2:	08 95       	ret
+000005a4 <__divmodsi4_exit>:
+ 5a4:	08 95       	ret
 
-000005b4 <_exit>:
- 5b4:	f8 94       	cli
+000005a6 <_exit>:
+ 5a6:	f8 94       	cli
 
-000005b6 <__stop_program>:
- 5b6:	ff cf       	rjmp	.-2      	; 0x5b6 <__stop_program>
+000005a8 <__stop_program>:
+ 5a8:	ff cf       	rjmp	.-2      	; 0x5a8 <__stop_program>
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.map b/V5B/Reciver/Reciver/Debug/Reciver.map
index 54da076..8dddce0 100644
--- a/V5B/Reciver/Reciver/Debug/Reciver.map
+++ b/V5B/Reciver/Reciver/Debug/Reciver.map
@@ -197,7 +197,7 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8
 .rela.plt
  *(.rela.plt)
 
-.text           0x00000000      0x5b8
+.text           0x00000000      0x5aa
  *(.vectors)
  .vectors       0x00000000       0x22 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/../../../../avr/lib/avr25/tiny-stack/crttn24a.o
                 0x00000000                __vector_default
@@ -271,67 +271,67 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8
                 0x00000054                __vector_16
                 0x00000056                . = ALIGN (0x2)
  *(.text.*)
- .text.turn     0x00000056       0x96 Reciver.o
+ .text.turn     0x00000056       0x90 Reciver.o
                 0x00000056                turn
- .text.poll     0x000000ec       0x94 Reciver.o
-                0x000000ec                poll
- .text.recive   0x00000180       0xa0 Reciver.o
-                0x00000180                recive
+ .text.poll     0x000000e6       0x94 Reciver.o
+                0x000000e6                poll
+ .text.recive   0x0000017a       0x98 Reciver.o
+                0x0000017a                recive
  .text.init_timer
-                0x00000220       0x10 Reciver.o
-                0x00000220                init_timer
+                0x00000212       0x10 Reciver.o
+                0x00000212                init_timer
  .text.__vector_11
-                0x00000230       0xf2 Reciver.o
-                0x00000230                __vector_11
- .text.main     0x00000322       0x2e Reciver.o
-                0x00000322                main
+                0x00000222       0xf2 Reciver.o
+                0x00000222                __vector_11
+ .text.main     0x00000314       0x2e Reciver.o
+                0x00000314                main
  .text.rf12_trans
-                0x00000350       0x32 rf12.o
-                0x00000350                rf12_trans
+                0x00000342       0x32 rf12.o
+                0x00000342                rf12_trans
  .text.rf12_init
-                0x00000382       0x46 rf12.o
-                0x00000382                rf12_init
+                0x00000374       0x46 rf12.o
+                0x00000374                rf12_init
  .text.rf12_setbandwidth
-                0x000003c8       0x38 rf12.o
-                0x000003c8                rf12_setbandwidth
+                0x000003ba       0x38 rf12.o
+                0x000003ba                rf12_setbandwidth
  .text.rf12_setfreq
-                0x00000400       0x1e rf12.o
-                0x00000400                rf12_setfreq
+                0x000003f2       0x1e rf12.o
+                0x000003f2                rf12_setfreq
  .text.rf12_setbaud
-                0x0000041e       0x46 rf12.o
-                0x0000041e                rf12_setbaud
+                0x00000410       0x46 rf12.o
+                0x00000410                rf12_setbaud
  .text.rf12_setpower
-                0x00000464       0x1e rf12.o
-                0x00000464                rf12_setpower
+                0x00000456       0x1e rf12.o
+                0x00000456                rf12_setpower
  .text.rf12_ready
-                0x00000482        0x8 rf12.o
-                0x00000482                rf12_ready
+                0x00000474        0x8 rf12.o
+                0x00000474                rf12_ready
  .text.rf12_beginasyncrx
-                0x0000048a       0x14 rf12.o
-                0x0000048a                rf12_beginasyncrx
+                0x0000047c       0x14 rf12.o
+                0x0000047c                rf12_beginasyncrx
  .text.rf12_hasdata
-                0x0000049e        0xa rf12.o
-                0x0000049e                rf12_hasdata
+                0x00000490        0xa rf12.o
+                0x00000490                rf12_hasdata
  .text.rf12_rxbyte
-                0x000004a8        0x8 rf12.o
-                0x000004a8                rf12_rxbyte
+                0x0000049a        0x8 rf12.o
+                0x0000049a                rf12_rxbyte
  .text.rf12_endasyncrx
-                0x000004b0        0x8 rf12.o
-                0x000004b0                rf12_endasyncrx
+                0x000004a2        0x8 rf12.o
+                0x000004a2                rf12_endasyncrx
  .text.rf12_txpacket
-                0x000004b8       0x82 rf12.o
-                0x000004b8                rf12_txpacket
+                0x000004aa       0x82 rf12.o
+                0x000004aa                rf12_txpacket
  .text.libgcc.div
-                0x0000053a       0x44 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_udivmodsi4.o)
-                0x0000053a                __udivmodsi4
+                0x0000052c       0x44 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_udivmodsi4.o)
+                0x0000052c                __udivmodsi4
  .text.libgcc.div
-                0x0000057e       0x36 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_divmodsi4.o)
-                0x0000057e                __divmodsi4
-                0x000005b4                . = ALIGN (0x2)
+                0x00000570       0x36 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_divmodsi4.o)
+                0x00000570                __divmodsi4
+                0x000005a6                . = ALIGN (0x2)
  *(.fini9)
- .fini9         0x000005b4        0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o)
-                0x000005b4                _exit
-                0x000005b4                exit
+ .fini9         0x000005a6        0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o)
+                0x000005a6                _exit
+                0x000005a6                exit
  *(.fini9)
  *(.fini8)
  *(.fini8)
@@ -350,11 +350,11 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8
  *(.fini1)
  *(.fini1)
  *(.fini0)
- .fini0         0x000005b4        0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o)
+ .fini0         0x000005a6        0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/avr25/tiny-stack\libgcc.a(_exit.o)
  *(.fini0)
-                0x000005b8                _etext = .
+                0x000005aa                _etext = .
 
-.data           0x00800060        0x4 load address 0x000005b8
+.data           0x00800060        0x4 load address 0x000005aa
                 0x00800060                PROVIDE (__data_start, .)
  *(.data)
  .data          0x00800060        0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.7.2/../../../../avr/lib/avr25/tiny-stack/crttn24a.o
@@ -383,8 +383,8 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8
  *(.bss*)
  *(COMMON)
                 0x00800066                PROVIDE (__bss_end, .)
-                0x000005b8                __data_load_start = LOADADDR (.data)
-                0x000005bc                __data_load_end = (__data_load_start + SIZEOF (.data))
+                0x000005aa                __data_load_start = LOADADDR (.data)
+                0x000005ae                __data_load_end = (__data_load_start + SIZEOF (.data))
 
 .noinit         0x00800066        0x0
                 0x00800066                PROVIDE (__noinit_start, .)
@@ -460,10 +460,10 @@ LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.2.876/avr8
 .debug_pubnames
  *(.debug_pubnames)
 
-.debug_info     0x00000000      0xf92
+.debug_info     0x00000000      0xf8f
  *(.debug_info)
- .debug_info    0x00000000      0x70c Reciver.o
- .debug_info    0x0000070c      0x886 rf12.o
+ .debug_info    0x00000000      0x709 Reciver.o
+ .debug_info    0x00000709      0x886 rf12.o
  *(.gnu.linkonce.wi.*)
 
 .debug_abbrev   0x00000000      0x420
diff --git a/V5B/Reciver/Reciver/Debug/Reciver.srec b/V5B/Reciver/Reciver/Debug/Reciver.srec
index e6fe7d7..76da6c4 100644
--- a/V5B/Reciver/Reciver/Debug/Reciver.srec
+++ b/V5B/Reciver/Reciver/Debug/Reciver.srec
@@ -1,95 +1,94 @@
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 S113002019C011241FBECFEDCDBF10E0A0E6B0E093
-S1130030E8EBF5E002C005900D92A436B107D9F7BC
+S1130030EAEAF5E002C005900D92A436B107D9F7BB
 S113004020E0A4E6B0E001C01D92A636B207E1F7B5
-S113005068D1B0C2D5CF80916200909163000697B9
-S113006009F443C086E090E09093630080936200BB
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-S11300A099E0215080409040E1F700C0000088E2D0
-S11300B090E090936100809360002FEF82E597E0D9
-S11300C0215080409040E1F700C0000084EB90E0B4
-S11300D090936100809360002FEF86E191E12150BD
-S11300E080409040E1F700C000000895BA988091E4
-S11300F0620090916300039729F4B29B03C0D8D1A6
-S1130100AADFC3D18091620090916300029741F409
-S1130110B29B06C0CDD148E068E281E0CDD1B5D133
-S1130120CC992DC08091620090916300029739F5BB
-S113013086E090E090936300809362002FEF81E16A
-S11301409AE7215080409040E1F700C000002FEF73
-S113015081E19AE7215080409040E1F700C000001F
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+S11305607095809590959B01AC01BD01CF010895D4
+S1130570052E97FB16F4009406D057FD0CD0D6DF59
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+S10705AAB400020093
 S9030000FC
diff --git a/V5B/Reciver/Reciver/codes.h b/V5B/Reciver/Reciver/codes.h
index 112ae8f..54dae38 100644
--- a/V5B/Reciver/Reciver/codes.h
+++ b/V5B/Reciver/Reciver/codes.h
@@ -12,7 +12,7 @@
 #ifndef ALL
 #define ALL 0
 #define GROUP 240
-#define DEVICE 40
+#define DEVICE 10
 #define MASTER 1
 #endif