1154 lines
38 KiB
Plaintext
1154 lines
38 KiB
Plaintext
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Reciver.elf: file format elf32-avr
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .text 000005f4 00000000 00000000 00000094 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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1 .data 00000004 00800060 000005f4 00000688 2**0
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CONTENTS, ALLOC, LOAD, DATA
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2 .bss 00000002 00800064 00800064 0000068c 2**0
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ALLOC
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3 .stab 000006b4 00000000 00000000 0000068c 2**2
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CONTENTS, READONLY, DEBUGGING
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4 .stabstr 00000082 00000000 00000000 00000d40 2**0
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CONTENTS, READONLY, DEBUGGING
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5 .comment 0000002f 00000000 00000000 00000dc2 2**0
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CONTENTS, READONLY
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6 .debug_aranges 000000d0 00000000 00000000 00000df1 2**0
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CONTENTS, READONLY, DEBUGGING
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7 .debug_info 00001026 00000000 00000000 00000ec1 2**0
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CONTENTS, READONLY, DEBUGGING
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8 .debug_abbrev 0000040a 00000000 00000000 00001ee7 2**0
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CONTENTS, READONLY, DEBUGGING
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9 .debug_line 0000056e 00000000 00000000 000022f1 2**0
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CONTENTS, READONLY, DEBUGGING
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10 .debug_frame 000001c8 00000000 00000000 00002860 2**2
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CONTENTS, READONLY, DEBUGGING
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11 .debug_str 00000243 00000000 00000000 00002a28 2**0
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CONTENTS, READONLY, DEBUGGING
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12 .debug_loc 000007d0 00000000 00000000 00002c6b 2**0
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CONTENTS, READONLY, DEBUGGING
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13 .debug_ranges 000000b0 00000000 00000000 0000343b 2**0
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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00000000 <__vectors>:
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0: 10 c0 rjmp .+32 ; 0x22 <__ctors_end>
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2: 28 c0 rjmp .+80 ; 0x54 <__bad_interrupt>
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4: 27 c0 rjmp .+78 ; 0x54 <__bad_interrupt>
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6: 26 c0 rjmp .+76 ; 0x54 <__bad_interrupt>
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8: 25 c0 rjmp .+74 ; 0x54 <__bad_interrupt>
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a: 24 c0 rjmp .+72 ; 0x54 <__bad_interrupt>
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c: 23 c0 rjmp .+70 ; 0x54 <__bad_interrupt>
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e: 22 c0 rjmp .+68 ; 0x54 <__bad_interrupt>
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10: 21 c0 rjmp .+66 ; 0x54 <__bad_interrupt>
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12: 20 c0 rjmp .+64 ; 0x54 <__bad_interrupt>
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14: 1f c0 rjmp .+62 ; 0x54 <__bad_interrupt>
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16: 2a c1 rjmp .+596 ; 0x26c <__vector_11>
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18: 1d c0 rjmp .+58 ; 0x54 <__bad_interrupt>
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1a: 1c c0 rjmp .+56 ; 0x54 <__bad_interrupt>
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1c: 1b c0 rjmp .+54 ; 0x54 <__bad_interrupt>
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1e: 1a c0 rjmp .+52 ; 0x54 <__bad_interrupt>
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20: 19 c0 rjmp .+50 ; 0x54 <__bad_interrupt>
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00000022 <__ctors_end>:
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22: 11 24 eor r1, r1
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24: 1f be out 0x3f, r1 ; 63
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26: cf ed ldi r28, 0xDF ; 223
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28: cd bf out 0x3d, r28 ; 61
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0000002a <__do_copy_data>:
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2a: 10 e0 ldi r17, 0x00 ; 0
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2c: a0 e6 ldi r26, 0x60 ; 96
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2e: b0 e0 ldi r27, 0x00 ; 0
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30: e4 ef ldi r30, 0xF4 ; 244
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32: f5 e0 ldi r31, 0x05 ; 5
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34: 02 c0 rjmp .+4 ; 0x3a <__do_copy_data+0x10>
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36: 05 90 lpm r0, Z+
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38: 0d 92 st X+, r0
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3a: a4 36 cpi r26, 0x64 ; 100
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3c: b1 07 cpc r27, r17
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3e: d9 f7 brne .-10 ; 0x36 <__do_copy_data+0xc>
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00000040 <__do_clear_bss>:
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40: 20 e0 ldi r18, 0x00 ; 0
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42: a4 e6 ldi r26, 0x64 ; 100
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44: b0 e0 ldi r27, 0x00 ; 0
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46: 01 c0 rjmp .+2 ; 0x4a <.do_clear_bss_start>
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00000048 <.do_clear_bss_loop>:
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48: 1d 92 st X+, r1
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0000004a <.do_clear_bss_start>:
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4a: a6 36 cpi r26, 0x66 ; 102
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4c: b2 07 cpc r27, r18
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4e: e1 f7 brne .-8 ; 0x48 <.do_clear_bss_loop>
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50: 86 d1 rcall .+780 ; 0x35e <main>
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52: ce c2 rjmp .+1436 ; 0x5f0 <_exit>
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00000054 <__bad_interrupt>:
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54: d5 cf rjmp .-86 ; 0x0 <__vectors>
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00000056 <turn>:
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volatile int pwm_led = 0;
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volatile int servopos = RIGHT;
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void turn() {
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if(status == RUN)
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56: 80 91 62 00 lds r24, 0x0062
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5a: 90 91 63 00 lds r25, 0x0063
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5e: 06 97 sbiw r24, 0x06 ; 6
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60: 09 f4 brne .+2 ; 0x64 <turn+0xe>
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62: 43 c0 rjmp .+134 ; 0xea <__stack+0xb>
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return;
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status = RUN;
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64: 86 e0 ldi r24, 0x06 ; 6
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66: 90 e0 ldi r25, 0x00 ; 0
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68: 90 93 63 00 sts 0x0063, r25
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6c: 80 93 62 00 sts 0x0062, r24
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servopos = RIGHT-140;
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70: 88 e2 ldi r24, 0x28 ; 40
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72: 90 e0 ldi r25, 0x00 ; 0
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74: 90 93 61 00 sts 0x0061, r25
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78: 80 93 60 00 sts 0x0060, r24
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#else
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//round up by default
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__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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7c: 2f e7 ldi r18, 0x7F ; 127
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7e: 88 e3 ldi r24, 0x38 ; 56
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80: 91 e0 ldi r25, 0x01 ; 1
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82: 21 50 subi r18, 0x01 ; 1
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84: 80 40 sbci r24, 0x00 ; 0
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86: 90 40 sbci r25, 0x00 ; 0
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88: e1 f7 brne .-8 ; 0x82 <turn+0x2c>
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8a: 00 c0 rjmp .+0 ; 0x8c <turn+0x36>
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8c: 00 00 nop
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_delay_ms(10+DEVICE);
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rf12_txpacket(MASTER, DEVICE, status);
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8e: 40 91 62 00 lds r20, 0x0062
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92: 50 91 63 00 lds r21, 0x0063
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96: 68 e2 ldi r22, 0x28 ; 40
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98: 81 e0 ldi r24, 0x01 ; 1
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9a: 2c d2 rcall .+1112 ; 0x4f4 <rf12_txpacket>
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9c: 2f ef ldi r18, 0xFF ; 255
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9e: 83 ec ldi r24, 0xC3 ; 195
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a0: 99 e0 ldi r25, 0x09 ; 9
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a2: 21 50 subi r18, 0x01 ; 1
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a4: 80 40 sbci r24, 0x00 ; 0
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a6: 90 40 sbci r25, 0x00 ; 0
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a8: e1 f7 brne .-8 ; 0xa2 <turn+0x4c>
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aa: 00 c0 rjmp .+0 ; 0xac <turn+0x56>
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ac: 00 00 nop
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_delay_ms(400);
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servopos = RIGHT-160;
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ae: 84 e1 ldi r24, 0x14 ; 20
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b0: 90 e0 ldi r25, 0x00 ; 0
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b2: 90 93 61 00 sts 0x0061, r25
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b6: 80 93 60 00 sts 0x0060, r24
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ba: 2f ef ldi r18, 0xFF ; 255
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bc: 82 e5 ldi r24, 0x52 ; 82
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be: 97 e0 ldi r25, 0x07 ; 7
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c0: 21 50 subi r18, 0x01 ; 1
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c2: 80 40 sbci r24, 0x00 ; 0
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c4: 90 40 sbci r25, 0x00 ; 0
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c6: e1 f7 brne .-8 ; 0xc0 <turn+0x6a>
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c8: 00 c0 rjmp .+0 ; 0xca <turn+0x74>
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ca: 00 00 nop
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_delay_ms(300);
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servopos = RIGHT;
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cc: 84 eb ldi r24, 0xB4 ; 180
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ce: 90 e0 ldi r25, 0x00 ; 0
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d0: 90 93 61 00 sts 0x0061, r25
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d4: 80 93 60 00 sts 0x0060, r24
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d8: 2f ef ldi r18, 0xFF ; 255
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da: 86 e1 ldi r24, 0x16 ; 22
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dc: 91 e1 ldi r25, 0x11 ; 17
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de: 21 50 subi r18, 0x01 ; 1
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e0: 80 40 sbci r24, 0x00 ; 0
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e2: 90 40 sbci r25, 0x00 ; 0
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e4: e1 f7 brne .-8 ; 0xde <turn+0x88>
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e6: 00 c0 rjmp .+0 ; 0xe8 <__stack+0x9>
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e8: 00 00 nop
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ea: 08 95 ret
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000000ec <poll>:
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_delay_ms(700);
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}
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void poll() {
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DDRB &= ~(1<<PINB2);
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ec: ba 98 cbi 0x17, 2 ; 23
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if(status == ACTIVE) {
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ee: 80 91 62 00 lds r24, 0x0062
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f2: 90 91 63 00 lds r25, 0x0063
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f6: 03 97 sbiw r24, 0x03 ; 3
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f8: 29 f4 brne .+10 ; 0x104 <poll+0x18>
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if(PINB & (1<<PINB2)) {
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fa: b2 9b sbis 0x16, 2 ; 22
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fc: 03 c0 rjmp .+6 ; 0x104 <poll+0x18>
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rf12_endasyncrx();
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fe: f6 d1 rcall .+1004 ; 0x4ec <rf12_endasyncrx>
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turn();
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100: aa df rcall .-172 ; 0x56 <turn>
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rf12_beginasyncrx();
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102: e1 d1 rcall .+962 ; 0x4c6 <rf12_beginasyncrx>
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}
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}
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if(status == SLEEP) {
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104: 80 91 62 00 lds r24, 0x0062
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108: 90 91 63 00 lds r25, 0x0063
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10c: 02 97 sbiw r24, 0x02 ; 2
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10e: 41 f4 brne .+16 ; 0x120 <poll+0x34>
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if(PINB & (1<<PINB2)) {
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110: b2 9b sbis 0x16, 2 ; 22
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112: 06 c0 rjmp .+12 ; 0x120 <poll+0x34>
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rf12_endasyncrx();
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114: eb d1 rcall .+982 ; 0x4ec <rf12_endasyncrx>
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rf12_txpacket(MASTER, DEVICE, DEDECT);
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116: 48 e0 ldi r20, 0x08 ; 8
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118: 68 e2 ldi r22, 0x28 ; 40
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11a: 81 e0 ldi r24, 0x01 ; 1
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11c: eb d1 rcall .+982 ; 0x4f4 <rf12_txpacket>
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rf12_beginasyncrx();
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11e: d3 d1 rcall .+934 ; 0x4c6 <rf12_beginasyncrx>
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}
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}
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if(!(PINA & (1<<PINA4))) { //SCK auf 0
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120: cc 99 sbic 0x19, 4 ; 25
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122: 2d c0 rjmp .+90 ; 0x17e <poll+0x92>
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if(status == SLEEP) {
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124: 80 91 62 00 lds r24, 0x0062
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128: 90 91 63 00 lds r25, 0x0063
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12c: 02 97 sbiw r24, 0x02 ; 2
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12e: 39 f5 brne .+78 ; 0x17e <poll+0x92>
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status = RUN;
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130: 86 e0 ldi r24, 0x06 ; 6
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132: 90 e0 ldi r25, 0x00 ; 0
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134: 90 93 63 00 sts 0x0063, r25
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138: 80 93 62 00 sts 0x0062, r24
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13c: 2f ef ldi r18, 0xFF ; 255
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13e: 81 e1 ldi r24, 0x11 ; 17
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140: 9a e7 ldi r25, 0x7A ; 122
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142: 21 50 subi r18, 0x01 ; 1
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144: 80 40 sbci r24, 0x00 ; 0
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146: 90 40 sbci r25, 0x00 ; 0
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148: e1 f7 brne .-8 ; 0x142 <poll+0x56>
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14a: 00 c0 rjmp .+0 ; 0x14c <poll+0x60>
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14c: 00 00 nop
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14e: 2f ef ldi r18, 0xFF ; 255
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150: 81 e1 ldi r24, 0x11 ; 17
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152: 9a e7 ldi r25, 0x7A ; 122
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154: 21 50 subi r18, 0x01 ; 1
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156: 80 40 sbci r24, 0x00 ; 0
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158: 90 40 sbci r25, 0x00 ; 0
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15a: e1 f7 brne .-8 ; 0x154 <poll+0x68>
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15c: 00 c0 rjmp .+0 ; 0x15e <poll+0x72>
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15e: 00 00 nop
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160: 2f ef ldi r18, 0xFF ; 255
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162: 81 e1 ldi r24, 0x11 ; 17
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164: 9a e7 ldi r25, 0x7A ; 122
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166: 21 50 subi r18, 0x01 ; 1
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168: 80 40 sbci r24, 0x00 ; 0
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16a: 90 40 sbci r25, 0x00 ; 0
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16c: e1 f7 brne .-8 ; 0x166 <poll+0x7a>
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16e: 00 c0 rjmp .+0 ; 0x170 <poll+0x84>
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170: 00 00 nop
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_delay_ms(5000);
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_delay_ms(5000);
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_delay_ms(5000);
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status = ACTIVE;
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172: 83 e0 ldi r24, 0x03 ; 3
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174: 90 e0 ldi r25, 0x00 ; 0
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176: 90 93 63 00 sts 0x0063, r25
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17a: 80 93 62 00 sts 0x0062, r24
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17e: 08 95 ret
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00000180 <recive>:
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}
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}
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}
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void recive() {
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180: cf 93 push r28
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rf12_beginasyncrx();
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182: a1 d1 rcall .+834 ; 0x4c6 <rf12_beginasyncrx>
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while(rf12_hasdata()) {
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184: 01 c0 rjmp .+2 ; 0x188 <recive+0x8>
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poll();
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186: b2 df rcall .-156 ; 0xec <poll>
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}
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}
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void recive() {
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rf12_beginasyncrx();
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while(rf12_hasdata()) {
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188: a8 d1 rcall .+848 ; 0x4da <rf12_hasdata>
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18a: 81 11 cpse r24, r1
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18c: fc cf rjmp .-8 ; 0x186 <recive+0x6>
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poll();
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}
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uint8_t addr = rf12_rxbyte();
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18e: aa d1 rcall .+852 ; 0x4e4 <rf12_rxbyte>
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if(addr == ALL || addr == DEVICE || addr == GROUP) {
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190: 88 23 and r24, r24
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192: 39 f0 breq .+14 ; 0x1a2 <recive+0x22>
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194: 88 32 cpi r24, 0x28 ; 40
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196: 29 f0 breq .+10 ; 0x1a2 <recive+0x22>
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198: 80 3f cpi r24, 0xF0 ; 240
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19a: 09 f0 breq .+2 ; 0x19e <recive+0x1e>
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19c: 3f c0 rjmp .+126 ; 0x21c <recive+0x9c>
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19e: 01 c0 rjmp .+2 ; 0x1a2 <recive+0x22>
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while(rf12_hasdata()) {
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poll();
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1a0: a5 df rcall .-182 ; 0xec <poll>
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while(rf12_hasdata()) {
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poll();
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}
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uint8_t addr = rf12_rxbyte();
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if(addr == ALL || addr == DEVICE || addr == GROUP) {
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while(rf12_hasdata()) {
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1a2: 9b d1 rcall .+822 ; 0x4da <rf12_hasdata>
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1a4: 81 11 cpse r24, r1
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1a6: fc cf rjmp .-8 ; 0x1a0 <recive+0x20>
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poll();
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}
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uint8_t from = rf12_rxbyte();
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1a8: 9d d1 rcall .+826 ; 0x4e4 <rf12_rxbyte>
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1aa: c8 2f mov r28, r24
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while(rf12_hasdata()) {
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1ac: 01 c0 rjmp .+2 ; 0x1b0 <recive+0x30>
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poll();
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1ae: 9e df rcall .-196 ; 0xec <poll>
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if(addr == ALL || addr == DEVICE || addr == GROUP) {
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while(rf12_hasdata()) {
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poll();
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}
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uint8_t from = rf12_rxbyte();
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while(rf12_hasdata()) {
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1b0: 94 d1 rcall .+808 ; 0x4da <rf12_hasdata>
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1b2: 81 11 cpse r24, r1
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1b4: fc cf rjmp .-8 ; 0x1ae <recive+0x2e>
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poll();
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}
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if(from == MASTER) {
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1b6: c1 30 cpi r28, 0x01 ; 1
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1b8: 89 f5 brne .+98 ; 0x21c <recive+0x9c>
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uint8_t data = rf12_rxbyte();
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1ba: 94 d1 rcall .+808 ; 0x4e4 <rf12_rxbyte>
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switch(data) {
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1bc: 84 30 cpi r24, 0x04 ; 4
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1be: 49 f0 breq .+18 ; 0x1d2 <recive+0x52>
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1c0: 18 f4 brcc .+6 ; 0x1c8 <recive+0x48>
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1c2: 81 30 cpi r24, 0x01 ; 1
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1c4: c1 f4 brne .+48 ; 0x1f6 <recive+0x76>
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1c6: 19 c0 rjmp .+50 ; 0x1fa <recive+0x7a>
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1c8: 85 30 cpi r24, 0x05 ; 5
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1ca: 51 f0 breq .+20 ; 0x1e0 <recive+0x60>
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1cc: 87 30 cpi r24, 0x07 ; 7
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1ce: 99 f4 brne .+38 ; 0x1f6 <recive+0x76>
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1d0: 0e c0 rjmp .+28 ; 0x1ee <recive+0x6e>
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case PING: {
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break;
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}
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case SETSLEEP: {
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status = SLEEP;
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1d2: 82 e0 ldi r24, 0x02 ; 2
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1d4: 90 e0 ldi r25, 0x00 ; 0
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1d6: 90 93 63 00 sts 0x0063, r25
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1da: 80 93 62 00 sts 0x0062, r24
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break;
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1de: 0d c0 rjmp .+26 ; 0x1fa <recive+0x7a>
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}
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case SETACTIVE: {
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status = ACTIVE;
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1e0: 83 e0 ldi r24, 0x03 ; 3
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1e2: 90 e0 ldi r25, 0x00 ; 0
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1e4: 90 93 63 00 sts 0x0063, r25
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1e8: 80 93 62 00 sts 0x0062, r24
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break;
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1ec: 06 c0 rjmp .+12 ; 0x1fa <recive+0x7a>
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}
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case SETRUN: {
|
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rf12_endasyncrx();
|
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1ee: 7e d1 rcall .+764 ; 0x4ec <rf12_endasyncrx>
|
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turn();
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1f0: 32 df rcall .-412 ; 0x56 <turn>
|
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rf12_beginasyncrx();
|
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1f2: 69 d1 rcall .+722 ; 0x4c6 <rf12_beginasyncrx>
|
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return;
|
||
1f4: 13 c0 rjmp .+38 ; 0x21c <recive+0x9c>
|
||
}
|
||
default:
|
||
{
|
||
rf12_endasyncrx();
|
||
1f6: 7a d1 rcall .+756 ; 0x4ec <rf12_endasyncrx>
|
||
return;
|
||
1f8: 11 c0 rjmp .+34 ; 0x21c <recive+0x9c>
|
||
}
|
||
}
|
||
rf12_endasyncrx();
|
||
1fa: 78 d1 rcall .+752 ; 0x4ec <rf12_endasyncrx>
|
||
1fc: 2f e7 ldi r18, 0x7F ; 127
|
||
1fe: 88 e3 ldi r24, 0x38 ; 56
|
||
200: 91 e0 ldi r25, 0x01 ; 1
|
||
202: 21 50 subi r18, 0x01 ; 1
|
||
204: 80 40 sbci r24, 0x00 ; 0
|
||
206: 90 40 sbci r25, 0x00 ; 0
|
||
208: e1 f7 brne .-8 ; 0x202 <recive+0x82>
|
||
20a: 00 c0 rjmp .+0 ; 0x20c <recive+0x8c>
|
||
20c: 00 00 nop
|
||
_delay_ms(10+DEVICE);
|
||
rf12_txpacket(MASTER, DEVICE, status);
|
||
20e: 40 91 62 00 lds r20, 0x0062
|
||
212: 50 91 63 00 lds r21, 0x0063
|
||
216: 68 e2 ldi r22, 0x28 ; 40
|
||
218: 81 e0 ldi r24, 0x01 ; 1
|
||
21a: 6c d1 rcall .+728 ; 0x4f4 <rf12_txpacket>
|
||
return;
|
||
}
|
||
}
|
||
}
|
||
21c: cf 91 pop r28
|
||
21e: 08 95 ret
|
||
|
||
00000220 <init_timer>:
|
||
// Clock value: 7,813 kHz
|
||
// Mode: Normal top=0xFF
|
||
// OC0A output: Disconnected
|
||
// OC0B output: Disconnected
|
||
// Timer Period: 21,504 ms
|
||
TCCR0A = (0<<COM0A1) | (0<<COM0A0) | (0<<COM0B1) | (0<<COM0B0) | (0<<WGM01) | (0<<WGM00);
|
||
220: 10 be out 0x30, r1 ; 48
|
||
TCCR0B = (0<<WGM02) | (1<<CS02) | (0<<CS01) | (1<<CS00);
|
||
222: 85 e0 ldi r24, 0x05 ; 5
|
||
224: 83 bf out 0x33, r24 ; 51
|
||
TCNT0 = 0x58;
|
||
226: 88 e5 ldi r24, 0x58 ; 88
|
||
228: 82 bf out 0x32, r24 ; 50
|
||
|
||
// Timer/Counter 0 Interrupt(s) initialization
|
||
TIMSK0=(0<<OCIE0B) | (0<<OCIE0A) | (1<<TOIE0);
|
||
22a: 81 e0 ldi r24, 0x01 ; 1
|
||
22c: 89 bf out 0x39, r24 ; 57
|
||
|
||
DDRB |= (1<<PINB0);
|
||
22e: b8 9a sbi 0x17, 0 ; 23
|
||
PORTB |= (1<<PINB0);
|
||
230: c0 9a sbi 0x18, 0 ; 24
|
||
#else
|
||
//round up by default
|
||
__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
|
||
#endif
|
||
|
||
__builtin_avr_delay_cycles(__ticks_dc);
|
||
232: 8f ea ldi r24, 0xAF ; 175
|
||
234: 94 e0 ldi r25, 0x04 ; 4
|
||
236: 01 97 sbiw r24, 0x01 ; 1
|
||
238: f1 f7 brne .-4 ; 0x236 <init_timer+0x16>
|
||
23a: 00 c0 rjmp .+0 ; 0x23c <init_timer+0x1c>
|
||
23c: 00 00 nop
|
||
_delay_us(LEFT);
|
||
for(int i=0;i<servopos;i++) {
|
||
23e: 80 91 60 00 lds r24, 0x0060
|
||
242: 90 91 61 00 lds r25, 0x0061
|
||
246: 18 16 cp r1, r24
|
||
248: 19 06 cpc r1, r25
|
||
24a: 74 f4 brge .+28 ; 0x268 <init_timer+0x48>
|
||
24c: 80 e0 ldi r24, 0x00 ; 0
|
||
24e: 90 e0 ldi r25, 0x00 ; 0
|
||
250: 25 e1 ldi r18, 0x15 ; 21
|
||
252: 2a 95 dec r18
|
||
254: f1 f7 brne .-4 ; 0x252 <init_timer+0x32>
|
||
256: 00 00 nop
|
||
258: 01 96 adiw r24, 0x01 ; 1
|
||
25a: 20 91 60 00 lds r18, 0x0060
|
||
25e: 30 91 61 00 lds r19, 0x0061
|
||
262: 82 17 cp r24, r18
|
||
264: 93 07 cpc r25, r19
|
||
266: a4 f3 brlt .-24 ; 0x250 <init_timer+0x30>
|
||
_delay_us(STEP);
|
||
}
|
||
PORTB &= ~(1<<PINB0);
|
||
268: c0 98 cbi 0x18, 0 ; 24
|
||
26a: 08 95 ret
|
||
|
||
0000026c <__vector_11>:
|
||
}
|
||
|
||
ISR(TIM0_OVF_vect) {
|
||
26c: 1f 92 push r1
|
||
26e: 0f 92 push r0
|
||
270: 0f b6 in r0, 0x3f ; 63
|
||
272: 0f 92 push r0
|
||
274: 11 24 eor r1, r1
|
||
276: 2f 93 push r18
|
||
278: 3f 93 push r19
|
||
27a: 8f 93 push r24
|
||
27c: 9f 93 push r25
|
||
// Reinitialize Timer 0 value
|
||
TCNT0 = 0x58;
|
||
27e: 88 e5 ldi r24, 0x58 ; 88
|
||
280: 82 bf out 0x32, r24 ; 50
|
||
|
||
if(status == SLEEP) {
|
||
282: 80 91 62 00 lds r24, 0x0062
|
||
286: 90 91 63 00 lds r25, 0x0063
|
||
28a: 02 97 sbiw r24, 0x02 ; 2
|
||
28c: 79 f4 brne .+30 ; 0x2ac <__vector_11+0x40>
|
||
if(pwm_led > 50) {
|
||
28e: 80 91 64 00 lds r24, 0x0064
|
||
292: 90 91 65 00 lds r25, 0x0065
|
||
296: c3 97 sbiw r24, 0x33 ; 51
|
||
298: 94 f1 brlt .+100 ; 0x2fe <__vector_11+0x92>
|
||
PORTB ^= (1<<PINB1);
|
||
29a: 98 b3 in r25, 0x18 ; 24
|
||
29c: 82 e0 ldi r24, 0x02 ; 2
|
||
29e: 89 27 eor r24, r25
|
||
2a0: 88 bb out 0x18, r24 ; 24
|
||
pwm_led = 0;
|
||
2a2: 10 92 65 00 sts 0x0065, r1
|
||
2a6: 10 92 64 00 sts 0x0064, r1
|
||
2aa: 29 c0 rjmp .+82 ; 0x2fe <__vector_11+0x92>
|
||
}
|
||
} else if(status == ACTIVE) {
|
||
2ac: 80 91 62 00 lds r24, 0x0062
|
||
2b0: 90 91 63 00 lds r25, 0x0063
|
||
2b4: 03 97 sbiw r24, 0x03 ; 3
|
||
2b6: 79 f4 brne .+30 ; 0x2d6 <__vector_11+0x6a>
|
||
if(pwm_led > 5) {
|
||
2b8: 80 91 64 00 lds r24, 0x0064
|
||
2bc: 90 91 65 00 lds r25, 0x0065
|
||
2c0: 06 97 sbiw r24, 0x06 ; 6
|
||
2c2: ec f0 brlt .+58 ; 0x2fe <__vector_11+0x92>
|
||
PORTB ^= (1<<PINB1);
|
||
2c4: 98 b3 in r25, 0x18 ; 24
|
||
2c6: 82 e0 ldi r24, 0x02 ; 2
|
||
2c8: 89 27 eor r24, r25
|
||
2ca: 88 bb out 0x18, r24 ; 24
|
||
pwm_led = 0;
|
||
2cc: 10 92 65 00 sts 0x0065, r1
|
||
2d0: 10 92 64 00 sts 0x0064, r1
|
||
2d4: 14 c0 rjmp .+40 ; 0x2fe <__vector_11+0x92>
|
||
}
|
||
} else if(status == RUN) {
|
||
2d6: 80 91 62 00 lds r24, 0x0062
|
||
2da: 90 91 63 00 lds r25, 0x0063
|
||
2de: 06 97 sbiw r24, 0x06 ; 6
|
||
2e0: 71 f4 brne .+28 ; 0x2fe <__vector_11+0x92>
|
||
if(pwm_led > 1) {
|
||
2e2: 80 91 64 00 lds r24, 0x0064
|
||
2e6: 90 91 65 00 lds r25, 0x0065
|
||
2ea: 02 97 sbiw r24, 0x02 ; 2
|
||
2ec: 44 f0 brlt .+16 ; 0x2fe <__vector_11+0x92>
|
||
PORTB ^= (1<<PINB1);
|
||
2ee: 98 b3 in r25, 0x18 ; 24
|
||
2f0: 82 e0 ldi r24, 0x02 ; 2
|
||
2f2: 89 27 eor r24, r25
|
||
2f4: 88 bb out 0x18, r24 ; 24
|
||
pwm_led = 0;
|
||
2f6: 10 92 65 00 sts 0x0065, r1
|
||
2fa: 10 92 64 00 sts 0x0064, r1
|
||
}
|
||
}
|
||
pwm_led++;
|
||
2fe: 80 91 64 00 lds r24, 0x0064
|
||
302: 90 91 65 00 lds r25, 0x0065
|
||
306: 01 96 adiw r24, 0x01 ; 1
|
||
308: 90 93 65 00 sts 0x0065, r25
|
||
30c: 80 93 64 00 sts 0x0064, r24
|
||
|
||
DDRB |= (1<<PINB0);
|
||
310: b8 9a sbi 0x17, 0 ; 23
|
||
PORTB |= (1<<PINB0);
|
||
312: c0 9a sbi 0x18, 0 ; 24
|
||
314: 8f ea ldi r24, 0xAF ; 175
|
||
316: 94 e0 ldi r25, 0x04 ; 4
|
||
318: 01 97 sbiw r24, 0x01 ; 1
|
||
31a: f1 f7 brne .-4 ; 0x318 <__vector_11+0xac>
|
||
31c: 00 c0 rjmp .+0 ; 0x31e <__vector_11+0xb2>
|
||
31e: 00 00 nop
|
||
_delay_us(LEFT);
|
||
for(int i=0;i<servopos;i++) {
|
||
320: 80 91 60 00 lds r24, 0x0060
|
||
324: 90 91 61 00 lds r25, 0x0061
|
||
328: 18 16 cp r1, r24
|
||
32a: 19 06 cpc r1, r25
|
||
32c: 74 f4 brge .+28 ; 0x34a <__vector_11+0xde>
|
||
32e: 80 e0 ldi r24, 0x00 ; 0
|
||
330: 90 e0 ldi r25, 0x00 ; 0
|
||
332: 25 e1 ldi r18, 0x15 ; 21
|
||
334: 2a 95 dec r18
|
||
336: f1 f7 brne .-4 ; 0x334 <__vector_11+0xc8>
|
||
338: 00 00 nop
|
||
33a: 01 96 adiw r24, 0x01 ; 1
|
||
33c: 20 91 60 00 lds r18, 0x0060
|
||
340: 30 91 61 00 lds r19, 0x0061
|
||
344: 82 17 cp r24, r18
|
||
346: 93 07 cpc r25, r19
|
||
348: a4 f3 brlt .-24 ; 0x332 <__vector_11+0xc6>
|
||
_delay_us(STEP);
|
||
}
|
||
PORTB &= ~(1<<PINB0);
|
||
34a: c0 98 cbi 0x18, 0 ; 24
|
||
}
|
||
34c: 9f 91 pop r25
|
||
34e: 8f 91 pop r24
|
||
350: 3f 91 pop r19
|
||
352: 2f 91 pop r18
|
||
354: 0f 90 pop r0
|
||
356: 0f be out 0x3f, r0 ; 63
|
||
358: 0f 90 pop r0
|
||
35a: 1f 90 pop r1
|
||
35c: 18 95 reti
|
||
|
||
0000035e <main>:
|
||
|
||
int main(void)
|
||
{
|
||
|
||
rf12_init(); // ein paar Register setzen (z.B. CLK auf 10MHz)
|
||
35e: 2f d0 rcall .+94 ; 0x3be <rf12_init>
|
||
rf12_setfreq(RF12FREQ(433.92)); // Sende/Empfangsfrequenz auf 433,92MHz einstellen
|
||
360: 80 e2 ldi r24, 0x20 ; 32
|
||
362: 96 e0 ldi r25, 0x06 ; 6
|
||
364: 6b d0 rcall .+214 ; 0x43c <rf12_setfreq>
|
||
rf12_setbandwidth(1, 0, 7); // 400kHz Bandbreite, 0dB Verst<73>rkung, DRSSI threshold: -61dBm
|
||
366: 47 e0 ldi r20, 0x07 ; 7
|
||
368: 60 e0 ldi r22, 0x00 ; 0
|
||
36a: 81 e0 ldi r24, 0x01 ; 1
|
||
36c: 4b d0 rcall .+150 ; 0x404 <rf12_setbandwidth>
|
||
rf12_setbaud(9600); // 19200 baud
|
||
36e: 80 e8 ldi r24, 0x80 ; 128
|
||
370: 95 e2 ldi r25, 0x25 ; 37
|
||
372: 73 d0 rcall .+230 ; 0x45a <rf12_setbaud>
|
||
rf12_setpower(0, 6); // 1mW Ausgangsleistung, 120kHz Frequenzshift
|
||
374: 66 e0 ldi r22, 0x06 ; 6
|
||
376: 80 e0 ldi r24, 0x00 ; 0
|
||
378: 93 d0 rcall .+294 ; 0x4a0 <rf12_setpower>
|
||
|
||
init_timer();
|
||
37a: 52 df rcall .-348 ; 0x220 <init_timer>
|
||
DDRB |= (1<<PINB1); //Led Auf Ausgang
|
||
37c: b9 9a sbi 0x17, 1 ; 23
|
||
DDRA &= ~(1<<PINA4); //SCK Eingang
|
||
37e: d4 98 cbi 0x1a, 4 ; 26
|
||
PORTA |= (1<<PINA4); //SCK Pullup
|
||
380: dc 9a sbi 0x1b, 4 ; 27
|
||
DDRA |= (1<<PINA6); //MOSI Ausgang
|
||
382: d6 9a sbi 0x1a, 6 ; 26
|
||
PORTA &= ~(1<<PINA6); //MOSI 0
|
||
384: de 98 cbi 0x1b, 6 ; 27
|
||
sei();
|
||
386: 78 94 sei
|
||
|
||
//DDRB |= (1<<PINB1);
|
||
while(1)
|
||
{
|
||
recive();
|
||
388: fb de rcall .-522 ; 0x180 <recive>
|
||
38a: fe cf rjmp .-4 ; 0x388 <main+0x2a>
|
||
|
||
0000038c <rf12_trans>:
|
||
unsigned short rf12_trans(unsigned short wert)
|
||
{
|
||
unsigned short werti = 0;
|
||
unsigned char i;
|
||
|
||
RF_PORT &= ~(1<<CS);
|
||
38c: d9 98 cbi 0x1b, 1 ; 27
|
||
38e: 40 e1 ldi r20, 0x10 ; 16
|
||
#include "rf12.h"
|
||
#include <util/delay.h>
|
||
|
||
unsigned short rf12_trans(unsigned short wert)
|
||
{
|
||
unsigned short werti = 0;
|
||
390: 20 e0 ldi r18, 0x00 ; 0
|
||
392: 30 e0 ldi r19, 0x00 ; 0
|
||
unsigned char i;
|
||
|
||
RF_PORT &= ~(1<<CS);
|
||
for (i=0; i<16; i++)
|
||
{
|
||
if (wert&32768) {
|
||
394: 99 23 and r25, r25
|
||
396: 14 f4 brge .+4 ; 0x39c <rf12_trans+0x10>
|
||
RF_PORT |= (1<<SDI);
|
||
398: db 9a sbi 0x1b, 3 ; 27
|
||
39a: 01 c0 rjmp .+2 ; 0x39e <rf12_trans+0x12>
|
||
}
|
||
else {
|
||
RF_PORT &= ~(1<<SDI);
|
||
39c: db 98 cbi 0x1b, 3 ; 27
|
||
}
|
||
werti<<=1;
|
||
39e: 22 0f add r18, r18
|
||
3a0: 33 1f adc r19, r19
|
||
if (RF_PIN & (1<<SDO)) {
|
||
3a2: c8 99 sbic 0x19, 0 ; 25
|
||
werti|=1;
|
||
3a4: 21 60 ori r18, 0x01 ; 1
|
||
}
|
||
RF_PORT |= (1<<SCK);
|
||
3a6: da 9a sbi 0x1b, 2 ; 27
|
||
wert<<=1;
|
||
3a8: 88 0f add r24, r24
|
||
3aa: 99 1f adc r25, r25
|
||
3ac: 00 c0 rjmp .+0 ; 0x3ae <rf12_trans+0x22>
|
||
3ae: 00 00 nop
|
||
_delay_us(0.3);
|
||
RF_PORT &= ~(1<<SCK);
|
||
3b0: da 98 cbi 0x1b, 2 ; 27
|
||
3b2: 41 50 subi r20, 0x01 ; 1
|
||
{
|
||
unsigned short werti = 0;
|
||
unsigned char i;
|
||
|
||
RF_PORT &= ~(1<<CS);
|
||
for (i=0; i<16; i++)
|
||
3b4: 79 f7 brne .-34 ; 0x394 <rf12_trans+0x8>
|
||
RF_PORT |= (1<<SCK);
|
||
wert<<=1;
|
||
_delay_us(0.3);
|
||
RF_PORT &= ~(1<<SCK);
|
||
}
|
||
RF_PORT |= (1<<CS);
|
||
3b6: d9 9a sbi 0x1b, 1 ; 27
|
||
return werti;
|
||
}
|
||
3b8: 82 2f mov r24, r18
|
||
3ba: 93 2f mov r25, r19
|
||
3bc: 08 95 ret
|
||
|
||
000003be <rf12_init>:
|
||
|
||
void rf12_init(void)
|
||
{
|
||
RF_DDR |= (1<<SDI) | (1<<SCK) | (1<<CS);
|
||
3be: 8a b3 in r24, 0x1a ; 26
|
||
3c0: 8e 60 ori r24, 0x0E ; 14
|
||
3c2: 8a bb out 0x1a, r24 ; 26
|
||
RF_PORT |= (1<<CS);
|
||
3c4: d9 9a sbi 0x1b, 1 ; 27
|
||
#else
|
||
//round up by default
|
||
__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
|
||
#endif
|
||
|
||
__builtin_avr_delay_cycles(__ticks_dc);
|
||
3c6: 2f ef ldi r18, 0xFF ; 255
|
||
3c8: 80 e7 ldi r24, 0x70 ; 112
|
||
3ca: 92 e0 ldi r25, 0x02 ; 2
|
||
3cc: 21 50 subi r18, 0x01 ; 1
|
||
3ce: 80 40 sbci r24, 0x00 ; 0
|
||
3d0: 90 40 sbci r25, 0x00 ; 0
|
||
3d2: e1 f7 brne .-8 ; 0x3cc <rf12_init+0xe>
|
||
3d4: 00 c0 rjmp .+0 ; 0x3d6 <rf12_init+0x18>
|
||
3d6: 00 00 nop
|
||
|
||
_delay_ms(100);
|
||
|
||
rf12_trans(0xC0E0); // AVR CLK: 10MHz
|
||
3d8: 80 ee ldi r24, 0xE0 ; 224
|
||
3da: 90 ec ldi r25, 0xC0 ; 192
|
||
3dc: d7 df rcall .-82 ; 0x38c <rf12_trans>
|
||
rf12_trans(0x80D7); // Enable FIFO
|
||
3de: 87 ed ldi r24, 0xD7 ; 215
|
||
3e0: 90 e8 ldi r25, 0x80 ; 128
|
||
3e2: d4 df rcall .-88 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xC2AB); // Data Filter: internal
|
||
3e4: 8b ea ldi r24, 0xAB ; 171
|
||
3e6: 92 ec ldi r25, 0xC2 ; 194
|
||
3e8: d1 df rcall .-94 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xCA81); // Set FIFO mode
|
||
3ea: 81 e8 ldi r24, 0x81 ; 129
|
||
3ec: 9a ec ldi r25, 0xCA ; 202
|
||
3ee: ce df rcall .-100 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xE000); // disable wakeuptimer
|
||
3f0: 80 e0 ldi r24, 0x00 ; 0
|
||
3f2: 90 ee ldi r25, 0xE0 ; 224
|
||
3f4: cb df rcall .-106 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xC800); // disable low duty cycle
|
||
3f6: 80 e0 ldi r24, 0x00 ; 0
|
||
3f8: 98 ec ldi r25, 0xC8 ; 200
|
||
3fa: c8 df rcall .-112 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xC4F7); // AFC settings: autotuning: -10kHz...+7,5kHz
|
||
3fc: 87 ef ldi r24, 0xF7 ; 247
|
||
3fe: 94 ec ldi r25, 0xC4 ; 196
|
||
400: c5 df rcall .-118 ; 0x38c <rf12_trans>
|
||
402: 08 95 ret
|
||
|
||
00000404 <rf12_setbandwidth>:
|
||
}
|
||
|
||
void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
|
||
{
|
||
rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
|
||
404: 47 70 andi r20, 0x07 ; 7
|
||
406: 50 e0 ldi r21, 0x00 ; 0
|
||
408: 54 69 ori r21, 0x94 ; 148
|
||
40a: 63 70 andi r22, 0x03 ; 3
|
||
40c: 26 2f mov r18, r22
|
||
40e: 30 e0 ldi r19, 0x00 ; 0
|
||
410: 22 0f add r18, r18
|
||
412: 33 1f adc r19, r19
|
||
414: 22 0f add r18, r18
|
||
416: 33 1f adc r19, r19
|
||
418: 22 0f add r18, r18
|
||
41a: 33 1f adc r19, r19
|
||
41c: 90 e0 ldi r25, 0x00 ; 0
|
||
41e: 88 0f add r24, r24
|
||
420: 99 1f adc r25, r25
|
||
422: 82 95 swap r24
|
||
424: 92 95 swap r25
|
||
426: 90 7f andi r25, 0xF0 ; 240
|
||
428: 98 27 eor r25, r24
|
||
42a: 80 7f andi r24, 0xF0 ; 240
|
||
42c: 98 27 eor r25, r24
|
||
42e: 99 27 eor r25, r25
|
||
430: 82 2b or r24, r18
|
||
432: 93 2b or r25, r19
|
||
434: 84 2b or r24, r20
|
||
436: 95 2b or r25, r21
|
||
438: a9 df rcall .-174 ; 0x38c <rf12_trans>
|
||
43a: 08 95 ret
|
||
|
||
0000043c <rf12_setfreq>:
|
||
}
|
||
|
||
void rf12_setfreq(unsigned short freq)
|
||
{
|
||
if (freq<96) { // 430,2400MHz
|
||
43c: 80 36 cpi r24, 0x60 ; 96
|
||
43e: 91 05 cpc r25, r1
|
||
440: 38 f0 brcs .+14 ; 0x450 <rf12_setfreq+0x14>
|
||
442: 80 34 cpi r24, 0x40 ; 64
|
||
444: 2f e0 ldi r18, 0x0F ; 15
|
||
446: 92 07 cpc r25, r18
|
||
448: 28 f0 brcs .+10 ; 0x454 <rf12_setfreq+0x18>
|
||
44a: 8f e3 ldi r24, 0x3F ; 63
|
||
44c: 9f e0 ldi r25, 0x0F ; 15
|
||
44e: 02 c0 rjmp .+4 ; 0x454 <rf12_setfreq+0x18>
|
||
freq=96;
|
||
450: 80 e6 ldi r24, 0x60 ; 96
|
||
452: 90 e0 ldi r25, 0x00 ; 0
|
||
} else if (freq>3903) { // 439,7575MHz
|
||
freq=3903;
|
||
}
|
||
rf12_trans(0xA000|freq);
|
||
454: 90 6a ori r25, 0xA0 ; 160
|
||
456: 9a df rcall .-204 ; 0x38c <rf12_trans>
|
||
458: 08 95 ret
|
||
|
||
0000045a <rf12_setbaud>:
|
||
}
|
||
|
||
void rf12_setbaud(unsigned short baud)
|
||
{
|
||
if (baud<663) {
|
||
45a: 87 39 cpi r24, 0x97 ; 151
|
||
45c: 22 e0 ldi r18, 0x02 ; 2
|
||
45e: 92 07 cpc r25, r18
|
||
460: f0 f0 brcs .+60 ; 0x49e <rf12_setbaud+0x44>
|
||
return;
|
||
}
|
||
if (baud<5400) { // Baudrate= 344827,58621/(R+1)/(1+CS*7)
|
||
462: 88 31 cpi r24, 0x18 ; 24
|
||
464: 25 e1 ldi r18, 0x15 ; 21
|
||
466: 92 07 cpc r25, r18
|
||
468: 70 f4 brcc .+28 ; 0x486 <rf12_setbaud+0x2c>
|
||
rf12_trans(0xC680|((43104/baud)-1));
|
||
46a: 9c 01 movw r18, r24
|
||
46c: 40 e0 ldi r20, 0x00 ; 0
|
||
46e: 50 e0 ldi r21, 0x00 ; 0
|
||
470: 60 e6 ldi r22, 0x60 ; 96
|
||
472: 78 ea ldi r23, 0xA8 ; 168
|
||
474: 80 e0 ldi r24, 0x00 ; 0
|
||
476: 90 e0 ldi r25, 0x00 ; 0
|
||
478: a0 d0 rcall .+320 ; 0x5ba <__divmodsi4>
|
||
47a: c9 01 movw r24, r18
|
||
47c: 01 97 sbiw r24, 0x01 ; 1
|
||
47e: 80 68 ori r24, 0x80 ; 128
|
||
480: 96 6c ori r25, 0xC6 ; 198
|
||
482: 84 df rcall .-248 ; 0x38c <rf12_trans>
|
||
484: 08 95 ret
|
||
} else {
|
||
rf12_trans(0xC600|((344828UL/baud)-1));
|
||
486: 9c 01 movw r18, r24
|
||
488: 40 e0 ldi r20, 0x00 ; 0
|
||
48a: 50 e0 ldi r21, 0x00 ; 0
|
||
48c: 6c ef ldi r22, 0xFC ; 252
|
||
48e: 72 e4 ldi r23, 0x42 ; 66
|
||
490: 85 e0 ldi r24, 0x05 ; 5
|
||
492: 90 e0 ldi r25, 0x00 ; 0
|
||
494: 70 d0 rcall .+224 ; 0x576 <__udivmodsi4>
|
||
496: c9 01 movw r24, r18
|
||
498: 01 97 sbiw r24, 0x01 ; 1
|
||
49a: 96 6c ori r25, 0xC6 ; 198
|
||
49c: 77 df rcall .-274 ; 0x38c <rf12_trans>
|
||
49e: 08 95 ret
|
||
|
||
000004a0 <rf12_setpower>:
|
||
}
|
||
}
|
||
|
||
void rf12_setpower(unsigned char power, unsigned char mod)
|
||
{
|
||
rf12_trans(0x9800|(power&7)|((mod&15)<<4));
|
||
4a0: 87 70 andi r24, 0x07 ; 7
|
||
4a2: 90 e0 ldi r25, 0x00 ; 0
|
||
4a4: 98 69 ori r25, 0x98 ; 152
|
||
4a6: 70 e0 ldi r23, 0x00 ; 0
|
||
4a8: 62 95 swap r22
|
||
4aa: 72 95 swap r23
|
||
4ac: 70 7f andi r23, 0xF0 ; 240
|
||
4ae: 76 27 eor r23, r22
|
||
4b0: 60 7f andi r22, 0xF0 ; 240
|
||
4b2: 76 27 eor r23, r22
|
||
4b4: 77 27 eor r23, r23
|
||
4b6: 86 2b or r24, r22
|
||
4b8: 97 2b or r25, r23
|
||
4ba: 68 df rcall .-304 ; 0x38c <rf12_trans>
|
||
4bc: 08 95 ret
|
||
|
||
000004be <rf12_ready>:
|
||
}
|
||
|
||
void rf12_ready(void)
|
||
{
|
||
RF_PORT &= ~(1<<CS);
|
||
4be: d9 98 cbi 0x1b, 1 ; 27
|
||
while (!(RF_PIN & (1<<SDO))); // wait until FIFO ready
|
||
4c0: c8 9b sbis 0x19, 0 ; 25
|
||
4c2: fe cf rjmp .-4 ; 0x4c0 <rf12_ready+0x2>
|
||
}
|
||
4c4: 08 95 ret
|
||
|
||
000004c6 <rf12_beginasyncrx>:
|
||
|
||
void rf12_beginasyncrx() {
|
||
rf12_trans(0x82C8); // RX on
|
||
4c6: 88 ec ldi r24, 0xC8 ; 200
|
||
4c8: 92 e8 ldi r25, 0x82 ; 130
|
||
4ca: 60 df rcall .-320 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xCA81); // set FIFO mode
|
||
4cc: 81 e8 ldi r24, 0x81 ; 129
|
||
4ce: 9a ec ldi r25, 0xCA ; 202
|
||
4d0: 5d df rcall .-326 ; 0x38c <rf12_trans>
|
||
rf12_trans(0xCA83); // enable FIFO
|
||
4d2: 83 e8 ldi r24, 0x83 ; 131
|
||
4d4: 9a ec ldi r25, 0xCA ; 202
|
||
4d6: 5a df rcall .-332 ; 0x38c <rf12_trans>
|
||
4d8: 08 95 ret
|
||
|
||
000004da <rf12_hasdata>:
|
||
}
|
||
uint8_t rf12_hasdata() {
|
||
RF_PORT &= ~(1<<CS);
|
||
4da: d9 98 cbi 0x1b, 1 ; 27
|
||
return !(RF_PIN & (1<<SDO));
|
||
4dc: 89 b3 in r24, 0x19 ; 25
|
||
4de: 80 95 com r24
|
||
}
|
||
4e0: 81 70 andi r24, 0x01 ; 1
|
||
4e2: 08 95 ret
|
||
|
||
000004e4 <rf12_rxbyte>:
|
||
uint8_t rf12_rxbyte() {
|
||
return rf12_trans(0xB000);
|
||
4e4: 80 e0 ldi r24, 0x00 ; 0
|
||
4e6: 90 eb ldi r25, 0xB0 ; 176
|
||
4e8: 51 df rcall .-350 ; 0x38c <rf12_trans>
|
||
}
|
||
4ea: 08 95 ret
|
||
|
||
000004ec <rf12_endasyncrx>:
|
||
void rf12_endasyncrx() {
|
||
rf12_trans(0x8208); // RX off
|
||
4ec: 88 e0 ldi r24, 0x08 ; 8
|
||
4ee: 92 e8 ldi r25, 0x82 ; 130
|
||
4f0: 4d df rcall .-358 ; 0x38c <rf12_trans>
|
||
4f2: 08 95 ret
|
||
|
||
000004f4 <rf12_txpacket>:
|
||
*data++=rf12_trans(0xB000);
|
||
}
|
||
rf12_trans(0x8208); // RX off
|
||
}
|
||
|
||
void rf12_txpacket(uint8_t addr, uint8_t from, uint8_t data) {
|
||
4f4: 1f 93 push r17
|
||
4f6: cf 93 push r28
|
||
4f8: df 93 push r29
|
||
4fa: 18 2f mov r17, r24
|
||
4fc: d6 2f mov r29, r22
|
||
4fe: c4 2f mov r28, r20
|
||
rf12_trans(0x8238); // TX on
|
||
500: 88 e3 ldi r24, 0x38 ; 56
|
||
502: 92 e8 ldi r25, 0x82 ; 130
|
||
504: 43 df rcall .-378 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
506: db df rcall .-74 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB8AA);
|
||
508: 8a ea ldi r24, 0xAA ; 170
|
||
50a: 98 eb ldi r25, 0xB8 ; 184
|
||
50c: 3f df rcall .-386 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
50e: d7 df rcall .-82 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB8AA);
|
||
510: 8a ea ldi r24, 0xAA ; 170
|
||
512: 98 eb ldi r25, 0xB8 ; 184
|
||
514: 3b df rcall .-394 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
516: d3 df rcall .-90 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB8AA);
|
||
518: 8a ea ldi r24, 0xAA ; 170
|
||
51a: 98 eb ldi r25, 0xB8 ; 184
|
||
51c: 37 df rcall .-402 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
51e: cf df rcall .-98 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB82D);
|
||
520: 8d e2 ldi r24, 0x2D ; 45
|
||
522: 98 eb ldi r25, 0xB8 ; 184
|
||
524: 33 df rcall .-410 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
526: cb df rcall .-106 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB8D4);
|
||
528: 84 ed ldi r24, 0xD4 ; 212
|
||
52a: 98 eb ldi r25, 0xB8 ; 184
|
||
52c: 2f df rcall .-418 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
52e: c7 df rcall .-114 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB800|addr);
|
||
530: 81 2f mov r24, r17
|
||
532: 90 e0 ldi r25, 0x00 ; 0
|
||
534: 98 6b ori r25, 0xB8 ; 184
|
||
536: 2a df rcall .-428 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
538: c2 df rcall .-124 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB800|from);
|
||
53a: 8d 2f mov r24, r29
|
||
53c: 90 e0 ldi r25, 0x00 ; 0
|
||
53e: 98 6b ori r25, 0xB8 ; 184
|
||
540: 25 df rcall .-438 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
542: bd df rcall .-134 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB800|data);
|
||
544: 8c 2f mov r24, r28
|
||
546: 90 e0 ldi r25, 0x00 ; 0
|
||
548: 98 6b ori r25, 0xB8 ; 184
|
||
54a: 20 df rcall .-448 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
54c: b8 df rcall .-144 ; 0x4be <rf12_ready>
|
||
rf12_trans(0xB800);
|
||
54e: 80 e0 ldi r24, 0x00 ; 0
|
||
550: 98 eb ldi r25, 0xB8 ; 184
|
||
552: 1c df rcall .-456 ; 0x38c <rf12_trans>
|
||
rf12_ready();
|
||
554: b4 df rcall .-152 ; 0x4be <rf12_ready>
|
||
rf12_trans(0x8208); // TX off
|
||
556: 88 e0 ldi r24, 0x08 ; 8
|
||
558: 92 e8 ldi r25, 0x82 ; 130
|
||
55a: 18 df rcall .-464 ; 0x38c <rf12_trans>
|
||
55c: 2f ef ldi r18, 0xFF ; 255
|
||
55e: 80 e7 ldi r24, 0x70 ; 112
|
||
560: 92 e0 ldi r25, 0x02 ; 2
|
||
562: 21 50 subi r18, 0x01 ; 1
|
||
564: 80 40 sbci r24, 0x00 ; 0
|
||
566: 90 40 sbci r25, 0x00 ; 0
|
||
568: e1 f7 brne .-8 ; 0x562 <rf12_txpacket+0x6e>
|
||
56a: 00 c0 rjmp .+0 ; 0x56c <rf12_txpacket+0x78>
|
||
56c: 00 00 nop
|
||
_delay_ms(100);
|
||
56e: df 91 pop r29
|
||
570: cf 91 pop r28
|
||
572: 1f 91 pop r17
|
||
574: 08 95 ret
|
||
|
||
00000576 <__udivmodsi4>:
|
||
576: a1 e2 ldi r26, 0x21 ; 33
|
||
578: 1a 2e mov r1, r26
|
||
57a: aa 1b sub r26, r26
|
||
57c: bb 1b sub r27, r27
|
||
57e: fd 01 movw r30, r26
|
||
580: 0d c0 rjmp .+26 ; 0x59c <__udivmodsi4_ep>
|
||
|
||
00000582 <__udivmodsi4_loop>:
|
||
582: aa 1f adc r26, r26
|
||
584: bb 1f adc r27, r27
|
||
586: ee 1f adc r30, r30
|
||
588: ff 1f adc r31, r31
|
||
58a: a2 17 cp r26, r18
|
||
58c: b3 07 cpc r27, r19
|
||
58e: e4 07 cpc r30, r20
|
||
590: f5 07 cpc r31, r21
|
||
592: 20 f0 brcs .+8 ; 0x59c <__udivmodsi4_ep>
|
||
594: a2 1b sub r26, r18
|
||
596: b3 0b sbc r27, r19
|
||
598: e4 0b sbc r30, r20
|
||
59a: f5 0b sbc r31, r21
|
||
|
||
0000059c <__udivmodsi4_ep>:
|
||
59c: 66 1f adc r22, r22
|
||
59e: 77 1f adc r23, r23
|
||
5a0: 88 1f adc r24, r24
|
||
5a2: 99 1f adc r25, r25
|
||
5a4: 1a 94 dec r1
|
||
5a6: 69 f7 brne .-38 ; 0x582 <__udivmodsi4_loop>
|
||
5a8: 60 95 com r22
|
||
5aa: 70 95 com r23
|
||
5ac: 80 95 com r24
|
||
5ae: 90 95 com r25
|
||
5b0: 9b 01 movw r18, r22
|
||
5b2: ac 01 movw r20, r24
|
||
5b4: bd 01 movw r22, r26
|
||
5b6: cf 01 movw r24, r30
|
||
5b8: 08 95 ret
|
||
|
||
000005ba <__divmodsi4>:
|
||
5ba: 05 2e mov r0, r21
|
||
5bc: 97 fb bst r25, 7
|
||
5be: 16 f4 brtc .+4 ; 0x5c4 <__divmodsi4+0xa>
|
||
5c0: 00 94 com r0
|
||
5c2: 06 d0 rcall .+12 ; 0x5d0 <__divmodsi4_neg1>
|
||
5c4: 57 fd sbrc r21, 7
|
||
5c6: 0c d0 rcall .+24 ; 0x5e0 <__divmodsi4_neg2>
|
||
5c8: d6 df rcall .-84 ; 0x576 <__udivmodsi4>
|
||
5ca: 07 fc sbrc r0, 7
|
||
5cc: 09 d0 rcall .+18 ; 0x5e0 <__divmodsi4_neg2>
|
||
5ce: 7e f4 brtc .+30 ; 0x5ee <__divmodsi4_exit>
|
||
|
||
000005d0 <__divmodsi4_neg1>:
|
||
5d0: 90 95 com r25
|
||
5d2: 80 95 com r24
|
||
5d4: 70 95 com r23
|
||
5d6: 61 95 neg r22
|
||
5d8: 7f 4f sbci r23, 0xFF ; 255
|
||
5da: 8f 4f sbci r24, 0xFF ; 255
|
||
5dc: 9f 4f sbci r25, 0xFF ; 255
|
||
5de: 08 95 ret
|
||
|
||
000005e0 <__divmodsi4_neg2>:
|
||
5e0: 50 95 com r21
|
||
5e2: 40 95 com r20
|
||
5e4: 30 95 com r19
|
||
5e6: 21 95 neg r18
|
||
5e8: 3f 4f sbci r19, 0xFF ; 255
|
||
5ea: 4f 4f sbci r20, 0xFF ; 255
|
||
5ec: 5f 4f sbci r21, 0xFF ; 255
|
||
|
||
000005ee <__divmodsi4_exit>:
|
||
5ee: 08 95 ret
|
||
|
||
000005f0 <_exit>:
|
||
5f0: f8 94 cli
|
||
|
||
000005f2 <__stop_program>:
|
||
5f2: ff cf rjmp .-2 ; 0x5f2 <__stop_program>
|