453 lines
19 KiB
Plaintext
453 lines
19 KiB
Plaintext
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1 # 1 "lib/lib1funcs.S"
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1 /*
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0
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0
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2 * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
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3 *
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4 * Author: Nicolas Pitre <nico@cam.org>
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5 * - contributed to gcc-3.4 on Sep 30, 2003
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6 * - adapted for the Linux kernel on Oct 2, 2003
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7 */
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8
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9 /* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
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10
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11 This file is free software; you can redistribute it and/or modify it
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12 under the terms of the GNU General Public License as published by the
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13 Free Software Foundation; either version 2, or (at your option) any
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14 later version.
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15
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16 In addition to the permissions in the GNU General Public License, the
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17 Free Software Foundation gives you unlimited permission to link the
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18 compiled version of this file into combinations with other programs,
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19 and to distribute those combinations without any restriction coming
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20 from the use of this file. (The General Public License restrictions
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21 do apply in other respects; for example, they cover modification of
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22 the file, and distribution when not linked into a combine
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23 executable.)
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24
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25 This file is distributed in the hope that it will be useful, but
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26 WITHOUT ANY WARRANTY; without even the implied warranty of
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27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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28 General Public License for more details.
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29
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30 You should have received a copy of the GNU General Public License
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31 along with this program; see the file COPYING. If not, write to
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32 the Free Software Foundation, 59 Temple Place - Suite 330,
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33 Boston, MA 02111-1307, USA. */
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34
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35
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36 #include <asm/linkage.h>
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1 #ifndef __ASM_LINKAGE_H
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37 #include <asm/assembler.h>
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1 /*
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2 * linux/include/asm-arm/assembler.h
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3 *
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4 * Copyright (C) 1996-2000 Russell King
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5 *
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License version 2 as
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8 * published by the Free Software Foundation.
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9 *
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10 * This file contains arm architecture specific defines
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11 * for the different processors.
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12 *
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13 * Do not include any C declarations in this file - it is included by
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14 * assembler source.
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15 */
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16 #ifndef __ASSEMBLY__
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17 #error "Only include this from assembly code"
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18 #endif
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19
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20 #include <asm/ptrace.h>
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1 /*
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21
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22 #define pull lsl
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23 #define push lsr
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24 #define get_byte_0 lsr #24
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25 #define get_byte_1 lsr #16
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26 #define get_byte_2 lsr #8
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27 #define get_byte_3 lsl #0
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28 #define put_byte_0 lsl #24
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29 #define put_byte_1 lsl #16
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30 #define put_byte_2 lsl #8
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31 #define put_byte_3 lsl #0
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32
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33 #define PLD(code...)
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34
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35 #define MODE_USR USR_MODE
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36 #define MODE_FIQ FIQ_MODE
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37 #define MODE_IRQ IRQ_MODE
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38 #define MODE_SVC SVC_MODE
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39
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40 #define DEFAULT_FIQ MODE_FIQ
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41
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42 /*
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43 * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
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44 */
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45 #ifdef __STDC__
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46 #define LOADREGS(cond, base, reglist...)\
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47 ldm##cond base,reglist
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48 #else
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49 #define LOADREGS(cond, base, reglist...)\
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50 ldm/**/cond base,reglist
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51 #endif
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52
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53 /*
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54 * Build a return instruction for this processor type.
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55 */
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56 #define RETINSTR(instr, regs...)\
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57 instr regs
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58
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59 /*
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60 * Enable and disable interrupts
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61 */
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62 .macro disable_irq
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63 msr cpsr_c, #PSR_I_BIT | SVC_MODE
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64 .endm
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65
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66 .macro enable_irq
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67 msr cpsr_c, #SVC_MODE
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68 .endm
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69
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70 /*
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71 * Save the current IRQ state and disable IRQs. Note that this macro
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72 * assumes FIQs are enabled, and that the processor is in SVC mode.
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73 */
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74 .macro save_and_disable_irqs, oldcpsr
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75 mrs \oldcpsr, cpsr
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76 disable_irq
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77 .endm
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78
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79 /*
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80 * Restore interrupt state previously stored in a register. We don't
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81 * guarantee that this will preserve the flags.
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82 */
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83 .macro restore_irqs, oldcpsr
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84 msr cpsr_c, \oldcpsr
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85 .endm
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86
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87 /*
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88 * These two are used to save LR/restore PC over a user-based access.
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89 * The old 26-bit architecture requires that we do. On 32-bit
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90 * architecture, we can safely ignore this requirement.
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91 */
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92 .macro save_lr
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93 .endm
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94
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95 .macro restore_pc
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96 mov pc, lr
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97 .endm
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98 ...
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38
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39
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40 .macro ARM_DIV_BODY dividend, divisor, result, curbit
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41
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42 #if __LINUX_ARM_ARCH__ >= 5
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43
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44 clz \curbit, \divisor
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45 clz \result, \dividend
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46 sub \result, \curbit, \result
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47 mov \curbit, #1
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48 mov \divisor, \divisor, lsl \result
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49 mov \curbit, \curbit, lsl \result
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50 mov \result, #0
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51
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52 #else
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53
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54 @ Initially shift the divisor left 3 bits if possible,
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55 @ set curbit accordingly. This allows for curbit to be located
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56 @ at the left end of each 4 bit nibbles in the division loop
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57 @ to save one loop in most cases.
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58 tst \divisor, #0xe0000000
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59 moveq \divisor, \divisor, lsl #3
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60 moveq \curbit, #8
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61 movne \curbit, #1
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62
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63 @ Unless the divisor is very big, shift it up in multiples of
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64 @ four bits, since this is the amount of unwinding in the main
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65 @ division loop. Continue shifting until the divisor is
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66 @ larger than the dividend.
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67 1: cmp \divisor, #0x10000000
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68 cmplo \divisor, \dividend
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69 movlo \divisor, \divisor, lsl #4
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70 movlo \curbit, \curbit, lsl #4
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71 blo 1b
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72
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73 @ For very big divisors, we must shift it a bit at a time, or
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74 @ we will be in danger of overflowing.
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75 1: cmp \divisor, #0x80000000
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76 cmplo \divisor, \dividend
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77 movlo \divisor, \divisor, lsl #1
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78 movlo \curbit, \curbit, lsl #1
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79 blo 1b
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80
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81 mov \result, #0
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82
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83 #endif
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84
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85 @ Division loop
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86 1: cmp \dividend, \divisor
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87 subhs \dividend, \dividend, \divisor
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88 orrhs \result, \result, \curbit
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89 cmp \dividend, \divisor, lsr #1
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90 subhs \dividend, \dividend, \divisor, lsr #1
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91 orrhs \result, \result, \curbit, lsr #1
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92 cmp \dividend, \divisor, lsr #2
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93 subhs \dividend, \dividend, \divisor, lsr #2
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94 orrhs \result, \result, \curbit, lsr #2
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95 cmp \dividend, \divisor, lsr #3
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96 subhs \dividend, \dividend, \divisor, lsr #3
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97 orrhs \result, \result, \curbit, lsr #3
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98 cmp \dividend, #0 @ Early termination?
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99 movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
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100 movne \divisor, \divisor, lsr #4
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101 bne 1b
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102
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103 .endm
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104
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105
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106 .macro ARM_DIV2_ORDER divisor, order
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107
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108 #if __LINUX_ARM_ARCH__ >= 5
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109
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110 clz \order, \divisor
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111 rsb \order, \order, #31
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112
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113 #else
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114
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115 cmp \divisor, #(1 << 16)
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116 movhs \divisor, \divisor, lsr #16
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117 movhs \order, #16
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118 movlo \order, #0
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119
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120 cmp \divisor, #(1 << 8)
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121 movhs \divisor, \divisor, lsr #8
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122 addhs \order, \order, #8
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123
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124 cmp \divisor, #(1 << 4)
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125 movhs \divisor, \divisor, lsr #4
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126 addhs \order, \order, #4
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127
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128 cmp \divisor, #(1 << 2)
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129 addhi \order, \order, #3
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130 addls \order, \order, \divisor, lsr #1
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131
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132 #endif
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133
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134 .endm
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135
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136
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137 .macro ARM_MOD_BODY dividend, divisor, order, spare
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138
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139 #if __LINUX_ARM_ARCH__ >= 5
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140
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141 clz \order, \divisor
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142 clz \spare, \dividend
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143 sub \order, \order, \spare
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144 mov \divisor, \divisor, lsl \order
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145
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146 #else
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147
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148 mov \order, #0
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149
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150 @ Unless the divisor is very big, shift it up in multiples of
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151 @ four bits, since this is the amount of unwinding in the main
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152 @ division loop. Continue shifting until the divisor is
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153 @ larger than the dividend.
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154 1: cmp \divisor, #0x10000000
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155 cmplo \divisor, \dividend
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156 movlo \divisor, \divisor, lsl #4
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157 addlo \order, \order, #4
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158 blo 1b
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159
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160 @ For very big divisors, we must shift it a bit at a time, or
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161 @ we will be in danger of overflowing.
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162 1: cmp \divisor, #0x80000000
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163 cmplo \divisor, \dividend
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164 movlo \divisor, \divisor, lsl #1
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165 addlo \order, \order, #1
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166 blo 1b
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167
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168 #endif
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169
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170 @ Perform all needed substractions to keep only the reminder.
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171 @ Do comparisons in batch of 4 first.
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172 subs \order, \order, #3 @ yes, 3 is intended here
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173 blt 2f
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174
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175 1: cmp \dividend, \divisor
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176 subhs \dividend, \dividend, \divisor
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177 cmp \dividend, \divisor, lsr #1
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178 subhs \dividend, \dividend, \divisor, lsr #1
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179 cmp \dividend, \divisor, lsr #2
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180 subhs \dividend, \dividend, \divisor, lsr #2
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181 cmp \dividend, \divisor, lsr #3
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182 subhs \dividend, \dividend, \divisor, lsr #3
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183 cmp \dividend, #1
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184 mov \divisor, \divisor, lsr #4
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185 subges \order, \order, #4
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186 bge 1b
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187
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188 tst \order, #3
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189 teqne \dividend, #0
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190 beq 5f
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191
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192 @ Either 1, 2 or 3 comparison/substractions are left.
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193 2: cmn \order, #2
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194 blt 4f
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195 beq 3f
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196 cmp \dividend, \divisor
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197 subhs \dividend, \dividend, \divisor
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198 mov \divisor, \divisor, lsr #1
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199 3: cmp \dividend, \divisor
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200 subhs \dividend, \dividend, \divisor
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201 mov \divisor, \divisor, lsr #1
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202 4: cmp \dividend, \divisor
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203 subhs \dividend, \dividend, \divisor
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204 5:
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205 .endm
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206
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207
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208 /*ENTRY(__udivsi3)
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209 ENTRY(__aeabi_uidiv)
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210
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211 subs r2, r1, #1
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212 moveq pc, lr
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213 bcc Ldiv0
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214 cmp r0, r1
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215 bls 11f
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216 tst r1, r2
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217 beq 12f
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218
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219 ARM_DIV_BODY r0, r1, r2, r3
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220
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221 mov r0, r2
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222 mov pc, lr
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223
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224 11: moveq r0, #1
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225 movne r0, #0
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226 mov pc, lr
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227
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228 12: ARM_DIV2_ORDER r1, r2
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229
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230 mov r0, r0, lsr r2
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231 mov pc, lr
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232 */
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233
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234 ENTRY(__umodsi3)
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235
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236 0000 012051E2 subs r2, r1, #1 @ compare divisor with 1
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237 0004 A700003A bcc Ldiv0
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238 0008 01005011 cmpne r0, r1 @ compare dividend with divisor
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239 000c 0000A003 moveq r0, #0
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240 0010 02001181 tsthi r1, r2 @ see if divisor is power of 2
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241 0014 02000000 andeq r0, r0, r2
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242 0018 0EF0A091 movls pc, lr
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243
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244 ARM_MOD_BODY r0, r1, r2, r3
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245
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246 00b8 0EF0A0E1 mov pc, lr
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247
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248
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249 ENTRY(__divsi3)
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250 ENTRY(__aeabi_idiv)
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251
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252 00bc 000051E3 cmp r1, #0
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253 00c0 01C020E0 eor ip, r0, r1 @ save the sign of the result.
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254 00c4 7700000A beq Ldiv0
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255 00c8 00106142 rsbmi r1, r1, #0 @ loops below use unsigned.
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256 00cc 012051E2 subs r2, r1, #1 @ division by 1 or -1 ?
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257 00d0 2700000A beq 10f
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258 00d4 0030B0E1 movs r3, r0
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259 00d8 00306042 rsbmi r3, r0, #0 @ positive dividend value
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260 00dc 010053E1 cmp r3, r1
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||
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261 00e0 2600009A bls 11f
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262 00e4 020011E1 tst r1, r2 @ divisor is power of 2 ?
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||
|
|
263 00e8 2800000A beq 12f
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||
|
|
264
|
||
|
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265 ARM_DIV_BODY r3, r1, r0, r2
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||
|
|
266
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||
|
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267 0168 00005CE3 cmp ip, #0
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||
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268 016c 00006042 rsbmi r0, r0, #0
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||
|
|
269 0170 0EF0A0E1 mov pc, lr
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||
|
|
270
|
||
|
|
271 0174 00003CE1 10: teq ip, r0 @ same sign ?
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||
|
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272 0178 00006042 rsbmi r0, r0, #0
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||
|
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273 017c 0EF0A0E1 mov pc, lr
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||
|
|
274
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||
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|
275 0180 0000A033 11: movlo r0, #0
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||
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276 0184 CC0FA001 moveq r0, ip, asr #31
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||
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|
277 0188 01008003 orreq r0, r0, #1
|
||
|
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278 018c 0EF0A0E1 mov pc, lr
|
||
|
|
279
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||
|
|
280 12: ARM_DIV2_ORDER r1, r2
|
||
|
|
281
|
||
|
|
282 01c4 00005CE3 cmp ip, #0
|
||
|
|
283 01c8 3302A0E1 mov r0, r3, lsr r2
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||
|
|
284 01cc 00006042 rsbmi r0, r0, #0
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||
|
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285 01d0 0EF0A0E1 mov pc, lr
|
||
|
|
286
|
||
|
|
287
|
||
|
|
288 ENTRY(__modsi3)
|
||
|
|
289
|
||
|
|
290 01d4 000051E3 cmp r1, #0
|
||
|
|
291 01d8 3200000A beq Ldiv0
|
||
|
|
292 01dc 00106142 rsbmi r1, r1, #0 @ loops below use unsigned.
|
||
|
|
293 01e0 00C0B0E1 movs ip, r0 @ preserve sign of dividend
|
||
|
|
294 01e4 00006042 rsbmi r0, r0, #0 @ if negative make positive
|
||
|
|
295 01e8 012051E2 subs r2, r1, #1 @ compare divisor with 1
|
||
|
|
296 01ec 01005011 cmpne r0, r1 @ compare dividend with divisor
|
||
|
|
297 01f0 0000A003 moveq r0, #0
|
||
|
|
298 01f4 02001181 tsthi r1, r2 @ see if divisor is power of 2
|
||
|
|
299 01f8 02000000 andeq r0, r0, r2
|
||
|
|
300 01fc 2600009A bls 10f
|
||
|
|
301
|
||
|
|
302 ARM_MOD_BODY r0, r1, r2, r3
|
||
|
|
303
|
||
|
|
304 029c 00005CE3 10: cmp ip, #0
|
||
|
|
305 02a0 00006042 rsbmi r0, r0, #0
|
||
|
|
306 02a4 0EF0A0E1 mov pc, lr
|
||
|
|
307
|
||
|
|
308 #ifdef CONFIG_AEABI
|
||
|
|
309
|
||
|
|
310 ENTRY(__aeabi_uidivmod)
|
||
|
|
311
|
||
|
|
312 stmfd sp!, {r0, r1, ip, lr}
|
||
|
|
313 bl __aeabi_uidiv
|
||
|
|
314 ldmfd sp!, {r1, r2, ip, lr}
|
||
|
|
315 mul r3, r0, r2
|
||
|
|
316 sub r1, r1, r3
|
||
|
|
317 mov pc, lr
|
||
|
|
318
|
||
|
|
319 ENTRY(__aeabi_idivmod)
|
||
|
|
320
|
||
|
|
321 stmfd sp!, {r0, r1, ip, lr}
|
||
|
|
322 bl __aeabi_idiv
|
||
|
|
323 ldmfd sp!, {r1, r2, ip, lr}
|
||
|
|
324 mul r3, r0, r2
|
||
|
|
325 sub r1, r1, r3
|
||
|
|
326 mov pc, lr
|
||
|
|
327
|
||
|
|
328 #endif
|
||
|
|
329
|
||
|
|
330 Ldiv0:
|
||
|
|
331
|
||
|
|
332 02a8 08E02DE5 str lr, [sp, #-8]!
|
||
|
|
333 02ac FEFFFFEB bl __div0
|
||
|
|
334 02b0 0000A0E3 mov r0, #0 @ About as wrong as it could be.
|
||
|
|
335 02b4 08F09DE4 ldr pc, [sp], #8
|
||
|
|
336
|
||
|
|
337 ENTRY(__div0)
|
||
|
|
338 02b8 0EF0A0E1 mov pc, lr
|
||
|
|
DEFINED SYMBOLS
|
||
|
|
lib/lib1funcs.S:234 .text:00000000 __umodsi3
|
||
|
|
lib/lib1funcs.S:234 .text:00000000 $a
|
||
|
|
lib/lib1funcs.S:330 .text:000002a8 Ldiv0
|
||
|
|
lib/lib1funcs.S:249 .text:000000bc __divsi3
|
||
|
|
lib/lib1funcs.S:250 .text:000000bc __aeabi_idiv
|
||
|
|
lib/lib1funcs.S:288 .text:000001d4 __modsi3
|
||
|
|
lib/lib1funcs.S:337 .text:000002b8 __div0
|
||
|
|
.debug_aranges:0000000c $d
|
||
|
|
|
||
|
|
NO UNDEFINED SYMBOLS
|