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- data that is needed from both app and dfu mode
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- code that is needed from both app and dfu mode
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- function pointers
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- copy code to RAM in case of DFU switch
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- data that is only needed in DFU mode
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- can be overwritten in case of reset-to-application
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- data that is only needed in app mode
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- can be overwritten with DFU data in case of DFU switch
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- code that is only needed in DFU mode
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- has to be copied to ram in case of DFU switch
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- code that is only needed in app mode
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- can be read from flash, no action required
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=> abandoned that complicated idea.
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now all DFU functions are __ramfunc's and thus always present.
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interaction between app and dfu code:
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- dfu_switch(void)
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- dfu_status (can be put in accessor function, if required)
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- dfu_cfg_descriptor
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- dfu_dev_descriptor
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- dfu_ep0_handler()
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order of events at boot;
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- start at reset vector in flash
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- AT91F_LowLevelInit()
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- setup stack for each mode
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- relocate 'data' of bootloader, including ramfunc/vectram
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- clear 'bss' of bootloader
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- call remap command
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- call usb initialization (irq, clock)
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- if keypress,
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- call dfu_main()
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- wait for ep0 / busreset interrupt
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- else call main()
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memory layout:
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0: lowlevel startup code
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Cstartup.o 0x00bc
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Cstartup_SAM7.o 0x0100
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dfufunc 0x1dcc
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dfustruct 0x0038
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text text 0x0070
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data data 0x0000
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bss bss 0x000c
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flash = text + data (= 8k)
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ram/rel = data + bss (12 bytes)
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If we drop the DFU-can-flash-DFU requirement, we can leave all DFU related code
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in flash. no need for any function to be permanently in RAM. However, not
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preventing this feature in some future version, we shouldn't do that.
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Function DFU runtime
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udp_init x x RAM
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udp_ep0_send_data x x RAM
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udp_ep0_send_zlp x x RAM
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udp_sp0_send_stall x x RAM
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handle_dnload x - flash/relocated
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handle_upload x - flash/relocated
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handle_getstatus x - flash/relocated
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handle_getstate x - flash/relocated
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dfu_ep0_handler x x RAM
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dfu_dev_descriptor x - flash/relocated
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dfu_cfg_descriptor x - flash/relocated
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dfu_udp_ep0_handler x - flash/relocated
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dfu_udp_irq x - flash/relocated
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dfu_switch - x RAM
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dfu_main x - flash/relocated
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vectram x x flash/relocated/switched
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IRQ_Handler_EntryR x x flash/relocated/switched
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_remap x - flash/reloaded
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dfu_api x x flash (const anyway)
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dfu_state x x RAM
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preconditions:
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- dfu code assumes to be loaded to address zero to make it work from both ram and rom
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startup:
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- exception vectors (in flash)
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- call lowlevel_init
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- setup user/supervisor/FIQ/IRQ stack
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- relocate dfu_state
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- if DFU switch is pressed
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- jump to dfu_main in flash
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- relocate all of DFU .text/.data into ram (including exception vectors)
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- initialize DFU .bss
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- remap RAM to address zero
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- if DFU switch is not pressed jump to entry address of app
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- Cstartup_app.S
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- relocate application .data
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- initialize application .bss
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- jump to appliction main
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- application uses dfu_api in flash, pointing to in-flash data
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- application calls dfu_switch()
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- disable all interupts but USB
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- relocate all of DFU .text/.data into ram (including exception vectors)
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- remap RAM to address zero
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- check whether app has already remapped RAM before !?!
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memory map:
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load_addr run_Addr
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0x00100000 0x00000000 exception vectors (DFU Cstartup)
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Cstartup_SAM7
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0x00200000
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DFU constants:
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_etext:
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_data: 0x200000
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_edata:
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APP contants:
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_data: _edata_dfu
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@@ -0,0 +1,34 @@
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- code to control digital potentiometers via SPI [MM]
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- chip select not SPI CS
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- idea: use comparator to determine voltage range, then reconfigure amplifier
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- later
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- problem: capacitance of digital poti
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- idea 1:
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- idea 2: logarithmic amplifier using transistor
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- ADC driver
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- core [MM]
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- trigger function (we want to read all values ASAP)
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- callback function (once new values are available)
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- init function (initialize ADC)
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- USB integration [HW]
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- simple READ_ADC command
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- one reply packet with all ADC channels
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- OS timer
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- how often?
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- 'load modulation' driver
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x set PA2/PA3 to binary 0..3
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x add IO definitions for
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- PLL INHIBIT low
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- SPI_SS1_GAIN
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- SPI_SS2_DATA_THRESHOLD
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- BOOTLDR
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- sampled data continuous output into file / stdout
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- trigger sampling by raising/falling edge (configurable)
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- sample only one buffer
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@@ -0,0 +1,42 @@
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PICCSIM design
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ISO14443 anticollision:
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- Configure TC
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- to reset TC2 on every falling edge
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- to use FORCE_FAST for TC IRQ
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- to enable TC2 ETRGS
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- CARRIER_DIV is switched to 212kHz / 424kHz
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- this results in SSC Rx is 4x (2x?) oversampling
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- Set SSC Rx start condition to 4x/2x SOF pattern
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- upon reception of first falling edge, we
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- end up in TC FIQ
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- read out TC0 current value
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- reconfigure TC0 RA/RB to be in-phase with previously-read TC0
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value (subtracting some fixed offset depending on FIQ latency)
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- reconfigure TC2
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- to use external event on every rising edge
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- to reset(trigger) on every external event
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- to clear TIOA2 on RC compare (RC is high)
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- to set TIOA2 on RA compare (RA set later)
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- disable TC2 IRQ (and FIQ FAST_FORCE)
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- Wait for SSC Rx Interrupt (DMA complete, or PIO)
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- Read and decode single 32bit word
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- determine whether it is REQA or WUPA
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- abort if not, start over
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- depending on last bit 0/1, configure TC2 RA (FDT)
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- recconfig TC0 to produce 1.6MHz CARRIER_DIV clock for SSC Tx
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- make sure this is done synchronously
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-
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- set up SSC Tx
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- DMA with pre-encoded (and user-configured) ATQA
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- start Tx at a rising edge of TF (asserted by TC2 RA)
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- Send Interrupt once TX DMA is done
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- Once TC2 RA compare happens, the rising edge of TIOA2 will trigger SSC
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- Wait for SSC Tx DMA to finish
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- Repeat similar steps for ANTICOL/SELECT command, differences:
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- single-byte compare after frame Rx is not sufficient
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- evaluate number of valid bits ASAP
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- we might receive and transmit split frame at non-byte-boundaries
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- just shift a prepared ANTICOL/Select response
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- make sure parity is handled correctly!
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- Once we've completed the select, we go on with normal
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