: .date = COMPILE_DATE, .by = COMPILE_BY, }; int main(void) { 1080dc: e92d4008 push {r3, lr} /* initialize LED and debug unit */ led_init(); 1080e0: ebffff90 bl 107f28 sysirq_init(); 1080e4: eb00048a bl 109314 AT91F_DBGU_Init(); 1080e8: ebffff03 bl 107cfc //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 1080ec: e3e01c03 mvn r1, #768 ; 0x300 1080f0: e3a00004 mov r0, #4 1080f4: e50100ef str r0, [r1, #-239] ; 0xffffff11 AT91F_PIOA_CfgPMC(); wdt_init(); 1080f8: eb00035c bl 108e70 pit_init(); 1080fc: eb0001b8 bl 1087e4 blinkcode_init(); 108100: eb0003de bl 109080 /* initialize USB */ req_ctx_init(); 108104: ebffffa7 bl 107fa8 usbcmd_gen_init(); 108108: eb00033c bl 108e00 udp_open(); 10810c: ebfffd25 bl 1075a8 /* call application specific init function */ _init_func(); 108110: eb000783 bl 109f24 <_init_func> // Enable User Reset and set its minimal assertion to 960 us AT91C_BASE_RSTC->RSTC_RMR = 108114: e59f2030 ldr r2, [pc, #48] ; 10814c 108118: e3e03c02 mvn r3, #512 ; 0x200 AT91F_PMC_EnablePCK(AT91C_BASE_PMC, 0, AT91C_PMC_CSS_PLL_CLK); AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA6_PCK0); #endif /* switch on first led */ led_switch(2, 1); 10811c: e3a00002 mov r0, #2 108120: e3a01001 mov r1, #1 /* call application specific init function */ _init_func(); // Enable User Reset and set its minimal assertion to 960 us AT91C_BASE_RSTC->RSTC_RMR = 108124: e50320f7 str r2, [r3, #-247] ; 0xffffff09 AT91F_PMC_EnablePCK(AT91C_BASE_PMC, 0, AT91C_PMC_CSS_PLL_CLK); AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA6_PCK0); #endif /* switch on first led */ led_switch(2, 1); 108128: ebffff54 bl 107e80 DEBUGPCRF("entering main (idle) loop"); 10812c: e59f001c ldr r0, [pc, #28] ; 108150 108130: e59f101c ldr r1, [pc, #28] ; 108154 108134: e3a0204c mov r2, #76 ; 0x4c 108138: ebffff37 bl 107e1c while (1) { /* Call application specific main idle function */ _main_func(); 10813c: eb0007e1 bl 10a0c8 <_main_func> dbgu_rb_flush(); 108140: ebffff18 bl 107da8 /* restart watchdog timer */ wdt_restart(); 108144: eb000344 bl 108e5c 108148: eafffffb b 10813c 10814c: a5000401 .word 0xa5000401 108150: 0010ab3c .word 0x0010ab3c 108154: 0010ab04 .word 0x0010ab04 00108158 <_read_r>: unsigned int i; unsigned char *p; p = (unsigned char*)ptr; for (i = 0; i < len; i++) { 108158: e3530000 cmp r3, #0 10815c: 01a00003 moveq r0, r3 108160: 0a00000c beq 108198 <_read_r+0x40> 108164: e3a00000 mov r0, #0 //* \brief Return 1 if a character can be read in US_RHR //*---------------------------------------------------------------------------- static inline unsigned int AT91F_US_RxReady ( AT91PS_USART pUSART ) // \arg pointer to a USART controller { return (pUSART->US_CSR & AT91C_US_RXRDY); 108168: e3e0cc0d mvn ip, #3328 ; 0xd00 10816c: e51c10eb ldr r1, [ip, #-235] ; 0xffffff15 AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, c); } static int my_kbhit( void ) { if ((AT91F_US_RxReady((AT91PS_USART)AT91C_BASE_DBGU)) == 0) return 0; 108170: e3110001 tst r1, #1 108174: 0afffffc beq 10816c <_read_r+0x14> //* \brief Receive a character,does not check if a character is available //*---------------------------------------------------------------------------- static inline int AT91F_US_GetChar ( const AT91PS_USART pUSART) { return((pUSART->US_RHR) & 0x1FF); 108178: e51c10e7 ldr r1, [ip, #-231] ; 0xffffff19 else return 1; } static char my_getc( void ) { return AT91F_US_GetChar((AT91PS_USART)AT91C_BASE_DBGU); 10817c: e20110ff and r1, r1, #255 ; 0xff for (i = 0; i < len; i++) { // c = uart0Getch(); // c = uart0GetchW(); while ( !my_kbhit() ) ; c = (char) my_getc(); if (c == 0x0D) { 108180: e351000d cmp r1, #13 108184: 0a000005 beq 1081a0 <_read_r+0x48> unsigned int i; unsigned char *p; p = (unsigned char*)ptr; for (i = 0; i < len; i++) { 108188: e2800001 add r0, r0, #1 10818c: e1500003 cmp r0, r3 c = (char) my_getc(); if (c == 0x0D) { *p='\0'; break; } *p++ = c; 108190: e4c21001 strb r1, [r2], #1 unsigned int i; unsigned char *p; p = (unsigned char*)ptr; for (i = 0; i < len; i++) { 108194: 1afffff4 bne 10816c <_read_r+0x14> } *p++ = c; ////// uart0_putc(c); } return len - i; } 108198: e0600003 rsb r0, r0, r3 10819c: e12fff1e bx lr // c = uart0Getch(); // c = uart0GetchW(); while ( !my_kbhit() ) ; c = (char) my_getc(); if (c == 0x0D) { *p='\0'; 1081a0: e3a0c000 mov ip, #0 1081a4: e5c2c000 strb ip, [r2] } *p++ = c; ////// uart0_putc(c); } return len - i; } 1081a8: e0600003 rsb r0, r0, r3 1081ac: e12fff1e bx lr 001081b0 <_write_r>: int i; const unsigned char *p; p = (const unsigned char*) ptr; for (i = 0; i < len; i++) { 1081b0: e2530000 subs r0, r3, #0 _ssize_t _write_r ( struct _reent *r, int file, const void *ptr, size_t len) { 1081b4: e92d0070 push {r4, r5, r6} int i; const unsigned char *p; p = (const unsigned char*) ptr; for (i = 0; i < len; i++) { 1081b8: 0a00000c beq 1081f0 <_write_r+0x40> //* \brief Return 1 if a character can be written in US_THR //*---------------------------------------------------------------------------- static inline unsigned int AT91F_US_TxReady ( AT91PS_USART pUSART ) // \arg pointer to a USART controller { return (pUSART->US_CSR & AT91C_US_TXRDY); 1081bc: e3e01c0d mvn r1, #3328 ; 0xd00 extern void *_sbrk_r _PARAMS ((struct _reent *, ptrdiff_t)); extern int _stat_r _PARAMS ((struct _reent *, const char *, struct stat *)); extern _CLOCK_T_ _times_r _PARAMS ((struct _reent *, struct tms *)); extern int _unlink_r _PARAMS ((struct _reent *, const char *)); extern int _wait_r _PARAMS ((struct _reent *, int *)); extern _ssize_t _write_r _PARAMS ((struct _reent *, int, const void *, size_t)); 1081c0: e0825000 add r5, r2, r0 1081c4: e1a04001 mov r4, r1 //*---------------------------------------------------------------------------- static inline void AT91F_US_PutChar ( AT91PS_USART pUSART, int character ) { pUSART->US_THR = (character & 0x1FF); 1081c8: e3a0600d mov r6, #13 if (*p == '\n' ) my_putc('\r'); 1081cc: e4d2c001 ldrb ip, [r2], #1 1081d0: e35c000a cmp ip, #10 1081d4: 0a000007 beq 1081f8 <_write_r+0x48> //* \brief Return 1 if a character can be written in US_THR //*---------------------------------------------------------------------------- static inline unsigned int AT91F_US_TxReady ( AT91PS_USART pUSART ) // \arg pointer to a USART controller { return (pUSART->US_CSR & AT91C_US_TXRDY); 1081d8: e51130eb ldr r3, [r1, #-235] ; 0xffffff15 #include static void my_putc(char c) { while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)); 1081dc: e3130002 tst r3, #2 1081e0: 0afffffc beq 1081d8 <_write_r+0x28> int i; const unsigned char *p; p = (const unsigned char*) ptr; for (i = 0; i < len; i++) { 1081e4: e1520005 cmp r2, r5 //*---------------------------------------------------------------------------- static inline void AT91F_US_PutChar ( AT91PS_USART pUSART, int character ) { pUSART->US_THR = (character & 0x1FF); 1081e8: e504c0e3 str ip, [r4, #-227] ; 0xffffff1d 1081ec: 1afffff6 bne 1081cc <_write_r+0x1c> if (*p == '\n' ) my_putc('\r'); my_putc(*p++); } return len; } 1081f0: e8bd0070 pop {r4, r5, r6} 1081f4: e12fff1e bx lr //* \brief Return 1 if a character can be written in US_THR //*---------------------------------------------------------------------------- static inline unsigned int AT91F_US_TxReady ( AT91PS_USART pUSART ) // \arg pointer to a USART controller { return (pUSART->US_CSR & AT91C_US_TXRDY); 1081f8: e51130eb ldr r3, [r1, #-235] ; 0xffffff15 #include static void my_putc(char c) { while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)); 1081fc: e3130002 tst r3, #2 108200: 0afffffc beq 1081f8 <_write_r+0x48> //*---------------------------------------------------------------------------- static inline void AT91F_US_PutChar ( AT91PS_USART pUSART, int character ) { pUSART->US_THR = (character & 0x1FF); 108204: e50460e3 str r6, [r4, #-227] ; 0xffffff1d 108208: e552c001 ldrb ip, [r2, #-1] 10820c: eafffff1 b 1081d8 <_write_r+0x28> 00108210 <_close_r>: int _close_r( struct _reent *r, int file) { return 0; } 108210: e3a00000 mov r0, #0 108214: e12fff1e bx lr 00108218 <_lseek_r>: int file, _off_t ptr, int dir) { return (_off_t)0; /* Always indicate we are at file beginning. */ } 108218: e3a00000 mov r0, #0 10821c: e12fff1e bx lr 00108220 <_fstat_r>: struct _reent *r, int file, struct stat *st) { /* Always set as character device. */ st->st_mode = S_IFCHR; 108220: e3a03a02 mov r3, #8192 ; 0x2000 108224: e5823008 str r3, [r2, #8] /* assigned to strong type with implicit */ /* signed/unsigned conversion. Required by */ /* newlib. */ return 0; } 108228: e3a00000 mov r0, #0 10822c: e12fff1e bx lr 00108230 : int isatty(int file); /* avoid warning */ int isatty(int file) { return 1; } 108230: e3a00001 mov r0, #1 108234: e12fff1e bx lr 00108238 <_sbrk_r>: struct _reent *_s_r, ptrdiff_t nbytes) { char *base; /* errno should be set to ENOMEM on error */ if (!heap_ptr) { /* Initialize if first time through. */ 108238: e59f3018 ldr r3, [pc, #24] ; 108258 <_sbrk_r+0x20> 10823c: e5930000 ldr r0, [r3] 108240: e59f2014 ldr r2, [pc, #20] ; 10825c <_sbrk_r+0x24> 108244: e3500000 cmp r0, #0 108248: 01a00002 moveq r0, r2 heap_ptr = end; } base = heap_ptr; /* Point to end of heap. */ heap_ptr += nbytes; /* Increase heap. */ 10824c: e0801001 add r1, r0, r1 108250: e5831000 str r1, [r3] return base; /* Return pointer to start of new heap area. */ } 108254: e12fff1e bx lr 108258: 002037e4 .word 0x002037e4 10825c: 00203b4c .word 0x00203b4c 00108260 : static usb_cmd_fn *cmd_hdlrs[16]; int usb_hdlr_register(usb_cmd_fn *hdlr, u_int8_t class) { cmd_hdlrs[class] = hdlr; 108260: e59f3008 ldr r3, [pc, #8] ; 108270 108264: e7830101 str r0, [r3, r1, lsl #2] return 0; } 108268: e3a00000 mov r0, #0 10826c: e12fff1e bx lr 108270: 002037e8 .word 0x002037e8 00108274 : void usb_hdlr_unregister(u_int8_t class) { cmd_hdlrs[class] = NULL; 108274: e59f3008 ldr r3, [pc, #8] ; 108284 108278: e3a02000 mov r2, #0 10827c: e7832100 str r2, [r3, r0, lsl #2] } 108280: e12fff1e bx lr 108284: 002037e8 .word 0x002037e8 00108288 : } /* Process all pending request contexts that want to Tx on either * IN or INTERRUPT endpoint */ void usb_out_process(void) { 108288: e92d4008 push {r3, lr} /* interrupts are likely to be more urgent than bulk */ udp_refill_ep(3); 10828c: e3a00003 mov r0, #3 108290: ebfffcb0 bl 107558 udp_refill_ep(2); 108294: e3a00002 mov r0, #2 108298: ebfffcae bl 107558 } 10829c: e8bd4008 pop {r3, lr} 1082a0: e12fff1e bx lr 001082a4 : /* process incoming USB packets (OUT pipe) that have already been * put into request contexts by the UDP IRQ handler */ void usb_in_process(void) { 1082a4: e92d41f0 push {r4, r5, r6, r7, r8, lr} 1082a8: e59f40c0 ldr r4, [pc, #192] ; 108370 /* DEBUGP("usb_in(cls=%d) ", OPENPCD_CMD_CLS(poh->cmd));*/ if (rctx->tot_len < sizeof(*poh)) return -EINVAL; hdlr = cmd_hdlrs[OPENPCD_CMD_CLS(poh->cmd)]; 1082ac: e59f50c0 ldr r5, [pc, #192] ; 108374 } else ret = (hdlr)(rctx); if (ret & USB_RET_ERR) { poh->val = ret & 0xff; poh->flags = OPENPCD_FLAG_ERROR; 1082b0: e3e0607f mvn r6, #127 ; 0x7f * put into request contexts by the UDP IRQ handler */ void usb_in_process(void) { struct req_ctx *rctx; while (rctx = req_ctx_find_get(0, RCTX_STATE_UDP_RCV_DONE, 1082b4: e3a02003 mov r2, #3 1082b8: e3a01002 mov r1, #2 1082bc: e3a00000 mov r0, #0 1082c0: e1a0e00f mov lr, pc 1082c4: e12fff14 bx r4 1082c8: e2507000 subs r7, r0, #0 1082cc: 0a00001b beq 108340 usb_cmd_fn *hdlr; int ret; /* DEBUGP("usb_in(cls=%d) ", OPENPCD_CMD_CLS(poh->cmd));*/ if (rctx->tot_len < sizeof(*poh)) 1082d0: e1d730b6 ldrh r3, [r7, #6] 1082d4: e3530003 cmp r3, #3 cmd_hdlrs[class] = NULL; } static int usb_in(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; 1082d8: e5978008 ldr r8, [r7, #8] usb_cmd_fn *hdlr; int ret; /* DEBUGP("usb_in(cls=%d) ", OPENPCD_CMD_CLS(poh->cmd));*/ if (rctx->tot_len < sizeof(*poh)) 1082dc: 9afffff4 bls 1082b4 return -EINVAL; hdlr = cmd_hdlrs[OPENPCD_CMD_CLS(poh->cmd)]; 1082e0: e5d82000 ldrb r2, [r8] 1082e4: e1a01222 lsr r1, r2, #4 1082e8: e7953101 ldr r3, [r5, r1, lsl #2] if (!hdlr) { 1082ec: e3530000 cmp r3, #0 1082f0: 0a000019 beq 10835c DEBUGPCR("no handler for this class "); ret = USB_ERR(USB_ERR_CMD_UNKNOWN); } else ret = (hdlr)(rctx); 1082f4: e1a0e00f mov lr, pc 1082f8: e12fff13 bx r3 if (ret & USB_RET_ERR) { 1082fc: e3100c02 tst r0, #512 ; 0x200 108300: 02003c01 andeq r3, r0, #256 ; 0x100 108304: 1a000010 bne 10834c poh->val = ret & 0xff; poh->flags = OPENPCD_FLAG_ERROR; } if (ret & USB_RET_RESPOND) { 108308: e3530000 cmp r3, #0 10830c: 0affffe8 beq 1082b4 req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING); 108310: e1a00007 mov r0, r7 108314: e3a01010 mov r1, #16 108318: ebffff15 bl 107f74 udp_refill_ep(2); 10831c: e3a00002 mov r0, #2 108320: ebfffc8c bl 107558 * put into request contexts by the UDP IRQ handler */ void usb_in_process(void) { struct req_ctx *rctx; while (rctx = req_ctx_find_get(0, RCTX_STATE_UDP_RCV_DONE, 108324: e3a02003 mov r2, #3 108328: e3a01002 mov r1, #2 10832c: e3a00000 mov r0, #0 108330: e1a0e00f mov lr, pc 108334: e12fff14 bx r4 108338: e2507000 subs r7, r0, #0 10833c: 1affffe3 bne 1082d0 RCTX_STATE_MAIN_PROCESSING)) { /* DEBUGPCRF("found used ctx %u: len=%u", req_ctx_num(rctx), rctx->tot_len);*/ usb_in(rctx); } udp_unthrottle(); 108340: ebfffc7e bl 107540 } 108344: e8bd41f0 pop {r4, r5, r6, r7, r8, lr} 108348: e12fff1e bx lr DEBUGPCR("no handler for this class "); ret = USB_ERR(USB_ERR_CMD_UNKNOWN); } else ret = (hdlr)(rctx); if (ret & USB_RET_ERR) { 10834c: e2003c01 and r3, r0, #256 ; 0x100 poh->val = ret & 0xff; 108350: e5c80003 strb r0, [r8, #3] poh->flags = OPENPCD_FLAG_ERROR; 108354: e5c86001 strb r6, [r8, #1] 108358: eaffffea b 108308 if (rctx->tot_len < sizeof(*poh)) return -EINVAL; hdlr = cmd_hdlrs[OPENPCD_CMD_CLS(poh->cmd)]; if (!hdlr) { DEBUGPCR("no handler for this class "); 10835c: e59f0014 ldr r0, [pc, #20] ; 108378 108360: ebfffead bl 107e1c 108364: e3a03c01 mov r3, #256 ; 0x100 108368: e3a00001 mov r0, #1 10836c: eafffff7 b 108350 108370: 00200080 .word 0x00200080 108374: 002037e8 .word 0x002037e8 108378: 0010ab60 .word 0x0010ab60 0010837c : static struct req_ctx dummy_rctx; static struct req_ctx empty_rctx; static int usbtest_rx(struct req_ctx *rctx) { 10837c: e92d4038 push {r3, r4, r5, lr} struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; 108380: e5904008 ldr r4, [r0, #8] struct req_ctx *rctx_new; int i; switch (poh->cmd) { 108384: e5d43000 ldrb r3, [r4] 108388: e35300f1 cmp r3, #241 ; 0xf1 static struct req_ctx dummy_rctx; static struct req_ctx empty_rctx; static int usbtest_rx(struct req_ctx *rctx) { 10838c: e1a05000 mov r5, r0 struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; struct req_ctx *rctx_new; int i; switch (poh->cmd) { 108390: 0a000006 beq 1083b0 108394: e35300f2 cmp r3, #242 ; 0xf2 108398: 0a00001a beq 108408 /* test bulk out pipe */ return USB_ERR(USB_ERR_CMD_NOT_IMPL); break; } req_ctx_put(rctx); 10839c: e1a00005 mov r0, r5 1083a0: ebfffef9 bl 107f8c return 1; 1083a4: e3a00001 mov r0, #1 } 1083a8: e8bd4038 pop {r3, r4, r5, lr} 1083ac: e12fff1e bx lr struct req_ctx *rctx_new; int i; switch (poh->cmd) { case OPENPCD_CMD_USBTEST_IN: DEBUGP("USBTEST_IN "); 1083b0: e59f0070 ldr r0, [pc, #112] ; 108428 1083b4: ebfffe98 bl 107e1c /* test bulk in pipe */ if (poh->val > RCTX_SIZE_LARGE/AT91C_EP_OUT_SIZE) 1083b8: e5d40003 ldrb r0, [r4, #3] 1083bc: e3500020 cmp r0, #32 poh->val = RCTX_SIZE_LARGE/AT91C_EP_OUT_SIZE; 1083c0: 83a00020 movhi r0, #32 1083c4: 85c40003 strbhi r0, [r4, #3] rctx_new = req_ctx_find_get(1, RCTX_STATE_FREE, 1083c8: e59f305c ldr r3, [pc, #92] ; 10842c 1083cc: e3a00001 mov r0, #1 1083d0: e3a010fe mov r1, #254 ; 0xfe 1083d4: e3a02003 mov r2, #3 1083d8: e1a0e00f mov lr, pc 1083dc: e12fff13 bx r3 RCTX_STATE_MAIN_PROCESSING); if (!rctx_new) { 1083e0: e2503000 subs r3, r0, #0 1083e4: 0a00000b beq 108418 DEBUGP("NO RCTX "); return USB_ERR(0); } rctx_new->tot_len = poh->val * AT91C_EP_OUT_SIZE; 1083e8: e5d41003 ldrb r1, [r4, #3] 1083ec: e1a02301 lsl r2, r1, #6 1083f0: e1c320b6 strh r2, [r3, #6] req_ctx_set_state(rctx_new, RCTX_STATE_UDP_EP2_PENDING); 1083f4: e3a01010 mov r1, #16 1083f8: ebfffedd bl 107f74 led_toggle(2); 1083fc: e3a00002 mov r0, #2 108400: ebfffeb7 bl 107ee4 break; 108404: eaffffe4 b 10839c case OPENPCD_CMD_USBTEST_OUT: DEBUGP("USBTEST_IN "); 108408: e59f0018 ldr r0, [pc, #24] ; 108428 10840c: ebfffe82 bl 107e1c /* test bulk out pipe */ return USB_ERR(USB_ERR_CMD_NOT_IMPL); 108410: e59f0018 ldr r0, [pc, #24] ; 108430 108414: eaffffe3 b 1083a8 if (poh->val > RCTX_SIZE_LARGE/AT91C_EP_OUT_SIZE) poh->val = RCTX_SIZE_LARGE/AT91C_EP_OUT_SIZE; rctx_new = req_ctx_find_get(1, RCTX_STATE_FREE, RCTX_STATE_MAIN_PROCESSING); if (!rctx_new) { DEBUGP("NO RCTX "); 108418: e59f0014 ldr r0, [pc, #20] ; 108434 10841c: ebfffe7e bl 107e1c return USB_ERR(0); 108420: e3a00c03 mov r0, #768 ; 0x300 108424: eaffffdf b 1083a8 108428: 0010ab80 .word 0x0010ab80 10842c: 00200080 .word 0x00200080 108430: 00000302 .word 0x00000302 108434: 0010ab8c .word 0x0010ab8c 00108438 : req_ctx_put(rctx); return 1; } void usbtest_init(void) { 108438: e92d4010 push {r4, lr} dummy_rctx.tot_len = 64; 10843c: e59f4030 ldr r4, [pc, #48] ; 108474 108440: e3a0c040 mov ip, #64 ; 0x40 memset(dummy_rctx.data, 0x23, 64); 108444: e3a01023 mov r1, #35 ; 0x23 108448: e5940008 ldr r0, [r4, #8] 10844c: e1a0200c mov r2, ip return 1; } void usbtest_init(void) { dummy_rctx.tot_len = 64; 108450: e1c4c0b6 strh ip, [r4, #6] memset(dummy_rctx.data, 0x23, 64); 108454: eb00079c bl 10a2cc empty_rctx.tot_len = 0; 108458: e3a03000 mov r3, #0 usb_hdlr_register(&usbtest_rx, OPENPCD_CMD_CLS_USBTEST); 10845c: e3a0100f mov r1, #15 108460: e59f0010 ldr r0, [pc, #16] ; 108478 void usbtest_init(void) { dummy_rctx.tot_len = 64; memset(dummy_rctx.data, 0x23, 64); empty_rctx.tot_len = 0; 108464: e1c431b2 strh r3, [r4, #18] usb_hdlr_register(&usbtest_rx, OPENPCD_CMD_CLS_USBTEST); 108468: ebffff7c bl 108260 } 10846c: e8bd4010 pop {r4, lr} 108470: e12fff1e bx lr 108474: 00203828 .word 0x00203828 108478: 0010837c .word 0x0010837c 0010847c : static AT91PS_TCB tcb = AT91C_BASE_TCB; /* set carrier divider to a specific */ void tc_cdiv_set_divider(u_int16_t div) { tcb->TCB_TC0.TC_RC = div; 10847c: e59f3018 ldr r3, [pc, #24] ; 10849c /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; tcb->TCB_TC0.TC_RB = 1 + (div >> 1); 108480: e1a0c0a0 lsr ip, r0, #1 108484: e28c2001 add r2, ip, #1 void tc_cdiv_set_divider(u_int16_t div) { tcb->TCB_TC0.TC_RC = div; /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; 108488: e3a01001 mov r1, #1 static AT91PS_TCB tcb = AT91C_BASE_TCB; /* set carrier divider to a specific */ void tc_cdiv_set_divider(u_int16_t div) { tcb->TCB_TC0.TC_RC = div; 10848c: e50300e3 str r0, [r3, #-227] ; 0xffffff1d /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; 108490: e50310eb str r1, [r3, #-235] ; 0xffffff15 tcb->TCB_TC0.TC_RB = 1 + (div >> 1); 108494: e50320e7 str r2, [r3, #-231] ; 0xffffff19 } 108498: e12fff1e bx lr 10849c: fffa00ff .word 0xfffa00ff 001084a0 : void tc_cdiv_phase_add(int16_t inc) { 1084a0: e92d4038 push {r3, r4, r5, lr} tcb->TCB_TC0.TC_RA = (tcb->TCB_TC0.TC_RA + inc) % tcb->TCB_TC0.TC_RC; 1084a4: e59f4054 ldr r4, [pc, #84] ; 108500 1084a8: e51420eb ldr r2, [r4, #-235] ; 0xffffff15 tcb->TCB_TC0.TC_RA = 1; tcb->TCB_TC0.TC_RB = 1 + (div >> 1); } void tc_cdiv_phase_add(int16_t inc) { 1084ac: e1a05000 mov r5, r0 tcb->TCB_TC0.TC_RA = (tcb->TCB_TC0.TC_RA + inc) % tcb->TCB_TC0.TC_RC; 1084b0: e51410e3 ldr r1, [r4, #-227] ; 0xffffff1d 1084b4: e0800002 add r0, r0, r2 1084b8: eb000818 bl 10a520 <__aeabi_uidivmod> 1084bc: e50410eb str r1, [r4, #-235] ; 0xffffff15 tcb->TCB_TC0.TC_RB = (tcb->TCB_TC0.TC_RB + inc) % tcb->TCB_TC0.TC_RC; 1084c0: e51400e7 ldr r0, [r4, #-231] ; 0xffffff19 1084c4: e51410e3 ldr r1, [r4, #-227] ; 0xffffff1d 1084c8: e0850000 add r0, r5, r0 1084cc: eb000813 bl 10a520 <__aeabi_uidivmod> 1084d0: e50410e7 str r1, [r4, #-231] ; 0xffffff19 /* FIXME: can this be done more elegantly? */ if (tcb->TCB_TC0.TC_RA == 0) { 1084d4: e51430eb ldr r3, [r4, #-235] ; 0xffffff15 1084d8: e3530000 cmp r3, #0 1084dc: 1a000005 bne 1084f8 tcb->TCB_TC0.TC_RA += 1; 1084e0: e51430eb ldr r3, [r4, #-235] ; 0xffffff15 1084e4: e283e001 add lr, r3, #1 1084e8: e504e0eb str lr, [r4, #-235] ; 0xffffff15 tcb->TCB_TC0.TC_RB += 1; 1084ec: e514c0e7 ldr ip, [r4, #-231] ; 0xffffff19 1084f0: e28c1001 add r1, ip, #1 1084f4: e50410e7 str r1, [r4, #-231] ; 0xffffff19 } } 1084f8: e8bd4038 pop {r3, r4, r5, lr} 1084fc: e12fff1e bx lr 108500: fffa00ff .word 0xfffa00ff 00108504 : AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_TC0)); /* Enable Clock for TC0 */ tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN; 108504: e59f3060 ldr r3, [pc, #96] ; 10856c AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; 108508: e3e01c0b mvn r1, #2816 ; 0xb00 pPio->PIO_BSR = periphBEnable; 10850c: e3a00233 mov r0, #805306371 ; 0x30000003 AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; 108510: e3a0c000 mov ip, #0 108514: e501c08f str ip, [r1, #-143] ; 0xffffff71 108518: e3a02001 mov r2, #1 pPio->PIO_BSR = periphBEnable; 10851c: e501008b str r0, [r1, #-139] ; 0xffffff75 pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode 108520: e50100fb str r0, [r1, #-251] ; 0xffffff05 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 108524: e3a00a01 mov r0, #4096 ; 0x1000 108528: e3e01c03 mvn r1, #768 ; 0x300 10852c: e50100ef str r0, [r1, #-239] ; 0xffffff11 108530: e50320ff str r2, [r3, #-255] ; 0xffffff01 /* Connect TCLK1 to XC1, TCLK2 to XC2 */ tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S); 108534: e513c03b ldr ip, [r3, #-59] ; 0xffffffc5 108538: e3cc003c bic r0, ip, #60 ; 0x3c 10853c: e503003b str r0, [r3, #-59] ; 0xffffffc5 tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2); 108540: e513103b ldr r1, [r3, #-59] ; 0xffffffc5 /* Clock XC1, Wave mode, Reset on RC comp * TIOA0 on RA comp = set, * TIOA0 on RC comp = clear, * TIOB0 on EEVT = set, TIOB0 on RB comp = clear, * EEVT = XC2 (TIOA0) */ tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE | 108544: e59fc024 ldr ip, [pc, #36] ; 108570 /* Enable Clock for TC0 */ tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN; /* Connect TCLK1 to XC1, TCLK2 to XC2 */ tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S); tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2); 108548: e503103b str r1, [r3, #-59] ; 0xffffffc5 static AT91PS_TCB tcb = AT91C_BASE_TCB; /* set carrier divider to a specific */ void tc_cdiv_set_divider(u_int16_t div) { tcb->TCB_TC0.TC_RC = div; 10854c: e3a00080 mov r0, #128 ; 0x80 /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; tcb->TCB_TC0.TC_RB = 1 + (div >> 1); 108550: e3a01041 mov r1, #65 ; 0x41 /* Clock XC1, Wave mode, Reset on RC comp * TIOA0 on RA comp = set, * TIOA0 on RC comp = clear, * TIOB0 on EEVT = set, TIOB0 on RB comp = clear, * EEVT = XC2 (TIOA0) */ tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE | 108554: e503c0fb str ip, [r3, #-251] ; 0xffffff05 static AT91PS_TCB tcb = AT91C_BASE_TCB; /* set carrier divider to a specific */ void tc_cdiv_set_divider(u_int16_t div) { tcb->TCB_TC0.TC_RC = div; 108558: e50300e3 str r0, [r3, #-227] ; 0xffffff1d /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; 10855c: e50320eb str r2, [r3, #-235] ; 0xffffff15 tcb->TCB_TC0.TC_RB = 1 + (div >> 1); 108560: e50310e7 str r1, [r3, #-231] ; 0xffffff19 AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR; tc_cdiv_set_divider(128); /* Reset to start timers */ tcb->TCB_BCR = 1; 108564: e503203f str r2, [r3, #-63] ; 0xffffffc1 } 108568: e12fff1e bx lr 10856c: fffa00ff .word 0xfffa00ff 108570: 9289cd06 .word 0x9289cd06 00108574 : void tc_cdiv_print(void) { 108574: e92d4010 push {r4, lr} DEBUGP("TCB_BMR=0x%08x ", tcb->TCB_BMR); 108578: e59f4048 ldr r4, [pc, #72] ; 1085c8 10857c: e59f0048 ldr r0, [pc, #72] ; 1085cc 108580: e514103b ldr r1, [r4, #-59] ; 0xffffffc5 108584: ebfffe24 bl 107e1c DEBUGP("TC0_CV=0x%08x ", tcb->TCB_TC0.TC_CV); 108588: e51410ef ldr r1, [r4, #-239] ; 0xffffff11 10858c: e59f003c ldr r0, [pc, #60] ; 1085d0 108590: ebfffe21 bl 107e1c DEBUGP("TC0_CMR=0x%08x ", tcb->TCB_TC0.TC_CMR); 108594: e51410fb ldr r1, [r4, #-251] ; 0xffffff05 108598: e59f0034 ldr r0, [pc, #52] ; 1085d4 10859c: ebfffe1e bl 107e1c DEBUGPCR("TC0_SR=0x%08x", tcb->TCB_TC0.TC_SR); 1085a0: e51410df ldr r1, [r4, #-223] ; 0xffffff21 1085a4: e59f002c ldr r0, [pc, #44] ; 1085d8 1085a8: ebfffe1b bl 107e1c DEBUGPCR("TC0_RA=0x%04x, TC0_RB=0x%04x, TC0_RC=0x%04x", 1085ac: e51410eb ldr r1, [r4, #-235] ; 0xffffff15 1085b0: e59f0024 ldr r0, [pc, #36] ; 1085dc 1085b4: e51420e7 ldr r2, [r4, #-231] ; 0xffffff19 1085b8: e51430e3 ldr r3, [r4, #-227] ; 0xffffff1d 1085bc: ebfffe16 bl 107e1c tcb->TCB_TC0.TC_RA, tcb->TCB_TC0.TC_RB, tcb->TCB_TC0.TC_RC); } 1085c0: e8bd4010 pop {r4, lr} 1085c4: e12fff1e bx lr 1085c8: fffa00ff .word 0xfffa00ff 1085cc: 0010ab98 .word 0x0010ab98 1085d0: 0010aba8 .word 0x0010aba8 1085d4: 0010abb8 .word 0x0010abb8 1085d8: 0010abc8 .word 0x0010abc8 1085dc: 0010abd8 .word 0x0010abd8 001085e0 : void tc_cdiv_fini(void) { tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS; 1085e0: e59f1014 ldr r1, [pc, #20] ; 1085fc 1085e4: e3a00002 mov r0, #2 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_DisablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCDR = periphIds; 1085e8: e3a02a01 mov r2, #4096 ; 0x1000 1085ec: e3e03c03 mvn r3, #768 ; 0x300 1085f0: e50100ff str r0, [r1, #-255] ; 0xffffff01 1085f4: e50320eb str r2, [r3, #-235] ; 0xffffff15 AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_TC0)); } 1085f8: e12fff1e bx lr 1085fc: fffa00ff .word 0xfffa00ff 00108600 : int timer_del(struct timer_list *tl) { unsigned long flags; int ret; local_irq_save(flags); 108600: e10fc000 mrs ip, CPSR 108604: e38c3080 orr r3, ip, #128 ; 0x80 108608: e121f003 msr CPSR_c, r3 static int __timer_remove(struct timer_list *old) { struct timer_list *tl, *tl_prev = NULL; for (tl = timers; tl != NULL; tl = tl->next) { 10860c: e59f1060 ldr r1, [pc, #96] ; 108674 108610: e5912000 ldr r2, [r1] 108614: e3520000 cmp r2, #0 return 1; } tl_prev = tl; } return 0; 108618: 01a00002 moveq r0, r2 static int __timer_remove(struct timer_list *old) { struct timer_list *tl, *tl_prev = NULL; for (tl = timers; tl != NULL; tl = tl->next) { 10861c: 0a000009 beq 108648 if (tl == old) { 108620: e1500002 cmp r0, r2 108624: 1a000003 bne 108638 108628: ea00000d b 108664 10862c: e1500003 cmp r0, r3 108630: 0a000006 beq 108650 108634: e1a02003 mov r2, r3 static int __timer_remove(struct timer_list *old) { struct timer_list *tl, *tl_prev = NULL; for (tl = timers; tl != NULL; tl = tl->next) { 108638: e5923000 ldr r3, [r2] 10863c: e3530000 cmp r3, #0 108640: 1afffff9 bne 10862c return 1; } tl_prev = tl; } return 0; 108644: e1a00003 mov r0, r3 unsigned long flags; int ret; local_irq_save(flags); ret = __timer_remove(tl); local_irq_restore(flags); 108648: e121f00c msr CPSR_c, ip return ret; } 10864c: e12fff1e bx lr for (tl = timers; tl != NULL; tl = tl->next) { if (tl == old) { if (tl == timers) timers = tl->next; else tl_prev->next = tl->next; 108650: e5903000 ldr r3, [r0] return 1; 108654: e3a00001 mov r0, #1 for (tl = timers; tl != NULL; tl = tl->next) { if (tl == old) { if (tl == timers) timers = tl->next; else tl_prev->next = tl->next; 108658: e5823000 str r3, [r2] unsigned long flags; int ret; local_irq_save(flags); ret = __timer_remove(tl); local_irq_restore(flags); 10865c: e121f00c msr CPSR_c, ip return ret; } 108660: e12fff1e bx lr struct timer_list *tl, *tl_prev = NULL; for (tl = timers; tl != NULL; tl = tl->next) { if (tl == old) { if (tl == timers) timers = tl->next; 108664: e5902000 ldr r2, [r0] else tl_prev->next = tl->next; return 1; 108668: e3a00001 mov r0, #1 struct timer_list *tl, *tl_prev = NULL; for (tl = timers; tl != NULL; tl = tl->next) { if (tl == old) { if (tl == timers) timers = tl->next; 10866c: e5812000 str r2, [r1] 108670: eafffff4 b 108648 108674: 00203840 .word 0x00203840 00108678 : static void pit_irq(u_int32_t sr) { struct timer_list *tl, *next; if (!(sr & 0x1)) 108678: e3100001 tst r0, #1 __timer_insert(tl); local_irq_restore(flags); } static void pit_irq(u_int32_t sr) { 10867c: e92d4070 push {r4, r5, r6, lr} struct timer_list *tl, *next; if (!(sr & 0x1)) 108680: 0a00001a beq 1086f0 return; jiffies += *AT91C_PITC_PIVR >> 20; 108684: e59f606c ldr r6, [pc, #108] ; 1086f8 /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { 108688: e59f106c ldr r1, [pc, #108] ; 1086fc struct timer_list *tl, *next; if (!(sr & 0x1)) return; jiffies += *AT91C_PITC_PIVR >> 20; 10868c: e3e04000 mvn r4, #0 108690: e51422c7 ldr r2, [r4, #-711] ; 0xfffffd39 108694: e5960000 ldr r0, [r6] /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { 108698: e5914000 ldr r4, [r1] struct timer_list *tl, *next; if (!(sr & 0x1)) return; jiffies += *AT91C_PITC_PIVR >> 20; 10869c: e0803a22 add r3, r0, r2, lsr #20 /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { 1086a0: e3540000 cmp r4, #0 struct timer_list *tl, *next; if (!(sr & 0x1)) return; jiffies += *AT91C_PITC_PIVR >> 20; 1086a4: e5863000 str r3, [r6] /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { 1086a8: 1a000003 bne 1086bc 1086ac: ea00000f b 1086f0 1086b0: e3550000 cmp r5, #0 1086b4: 0a00000d beq 1086f0 1086b8: e1a04005 mov r4, r5 next = tl->next; if (tl->expires <= jiffies) { 1086bc: e5945004 ldr r5, [r4, #4] 1086c0: e596c000 ldr ip, [r6] 1086c4: e155000c cmp r5, ip /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { next = tl->next; 1086c8: e5945000 ldr r5, [r4] if (tl->expires <= jiffies) { 1086cc: 8afffff7 bhi 1086b0 /* delete timer from list */ timer_del(tl); 1086d0: e1a00004 mov r0, r4 1086d4: ebffffc9 bl 108600 tl->function(tl->data); 1086d8: e594000c ldr r0, [r4, #12] 1086dc: e594c008 ldr ip, [r4, #8] 1086e0: e1a0e00f mov lr, pc 1086e4: e12fff1c bx ip jiffies += *AT91C_PITC_PIVR >> 20; /* this is the most simple/stupid algorithm one can come up with, but * hey, we're on a small embedded platform with only a hand ful * of timers, at all */ for (tl = timers; tl != NULL; tl = next) { 1086e8: e3550000 cmp r5, #0 1086ec: 1afffff1 bne 1086b8 /* delete timer from list */ timer_del(tl); tl->function(tl->data); } } } 1086f0: e8bd4070 pop {r4, r5, r6, lr} 1086f4: e12fff1e bx lr 1086f8: 00203a14 .word 0x00203a14 1086fc: 00203840 .word 0x00203840 00108700 : return ret; } void timer_add(struct timer_list *tl) { 108700: e92d0070 push {r4, r5, r6} unsigned long flags; local_irq_save(flags); 108704: e10f6000 mrs r6, CPSR 108708: e3863080 orr r3, r6, #128 ; 0x80 10870c: e121f003 msr CPSR_c, r3 static void __timer_insert(struct timer_list *new) { struct timer_list *tl, *tl_prev = NULL; if (!timers) { 108710: e59f505c ldr r5, [pc, #92] ; 108774 108714: e5954000 ldr r4, [r5] 108718: e3540000 cmp r4, #0 /* optimize for the common, fast case */ new->next = NULL; 10871c: 05804000 streq r4, [r0] timers = new; 108720: 05850000 streq r0, [r5] static void __timer_insert(struct timer_list *new) { struct timer_list *tl, *tl_prev = NULL; if (!timers) { 108724: 0a00000f beq 108768 timers = new; return; } for (tl = timers; tl != NULL; tl = tl->next) { if (tl->expires < new->expires) { 108728: e590c004 ldr ip, [r0, #4] 10872c: e1a03004 mov r3, r4 108730: e3a02000 mov r2, #0 108734: e5931004 ldr r1, [r3, #4] 108738: e151000c cmp r1, ip 10873c: 2a000004 bcs 108754 /* we need ot add just before this one */ if (!tl_prev) { 108740: e3520000 cmp r2, #0 new->next = timers; timers = new; } else { new->next = tl; 108744: 15803000 strne r3, [r0] tl_prev->next = new; 108748: 15820000 strne r0, [r2] for (tl = timers; tl != NULL; tl = tl->next) { if (tl->expires < new->expires) { /* we need ot add just before this one */ if (!tl_prev) { new->next = timers; 10874c: 05804000 streq r4, [r0] timers = new; 108750: 01a04000 moveq r4, r0 new->next = NULL; timers = new; return; } for (tl = timers; tl != NULL; tl = tl->next) { 108754: e1a02003 mov r2, r3 108758: e5933000 ldr r3, [r3] 10875c: e3530000 cmp r3, #0 108760: 1afffff3 bne 108734 108764: e5854000 str r4, [r5] { unsigned long flags; local_irq_save(flags); __timer_insert(tl); local_irq_restore(flags); 108768: e121f006 msr CPSR_c, r6 } 10876c: e8bd0070 pop {r4, r5, r6} 108770: e12fff1e bx lr 108774: 00203840 .word 0x00203840 00108778 : //* \brief Read PIT CPIV and PICNT without ressetting the counters //*---------------------------------------------------------------------------- static inline unsigned int AT91F_PITGetPIIR( AT91PS_PITC pPITC) { return(pPITC->PITC_PIIR); 108778: e3e03c02 mvn r3, #512 ; 0x200 10877c: e51320c3 ldr r2, [r3, #-195] ; 0xffffff3d void pit_mdelay(u_int32_t ms) { u_int32_t end; end = (AT91F_PITGetPIIR(AT91C_BASE_PITC) + ms) % 20; 108780: e59fc020 ldr ip, [pc, #32] ; 1087a8 108784: e0800002 add r0, r0, r2 108788: e08c1c90 umull r1, ip, r0, ip 10878c: e1a0122c lsr r1, ip, #4 108790: e0812101 add r2, r1, r1, lsl #2 108794: e0402102 sub r2, r0, r2, lsl #2 108798: e51300c3 ldr r0, [r3, #-195] ; 0xffffff3d while (end < AT91F_PITGetPIIR(AT91C_BASE_PITC)) { } 10879c: e1520000 cmp r2, r0 1087a0: 3afffffc bcc 108798 } 1087a4: e12fff1e bx lr 1087a8: cccccccd .word 0xcccccccd 001087ac : 1087ac: e3e03c02 mvn r3, #512 ; 0x200 1087b0: e51320c3 ldr r2, [r3, #-195] ; 0xffffff3d void pit_mdelay(u_int32_t ms) { u_int32_t end; end = (AT91F_PITGetPIIR(AT91C_BASE_PITC) + ms) % 20; 1087b4: e59fc020 ldr ip, [pc, #32] ; 1087dc 1087b8: e0800002 add r0, r0, r2 1087bc: e08c1c90 umull r1, ip, r0, ip 1087c0: e1a0122c lsr r1, ip, #4 1087c4: e0812101 add r2, r1, r1, lsl #2 1087c8: e0402102 sub r2, r0, r2, lsl #2 1087cc: e51300c3 ldr r0, [r3, #-195] ; 0xffffff3d while (end < AT91F_PITGetPIIR(AT91C_BASE_PITC)) { } 1087d0: e1520000 cmp r2, r0 1087d4: 3afffffc bcc 1087cc } void mdelay(u_int32_t ms) { return pit_mdelay(ms); } 1087d8: e12fff1e bx lr 1087dc: cccccccd .word 0xcccccccd 001087e0 : void usleep(u_int32_t us) { return; return pit_mdelay(us/1000); } 1087e0: e12fff1e bx lr 001087e4 : static inline void AT91F_PITInit( AT91PS_PITC pPITC, unsigned int period, unsigned int pit_frequency) { pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 1087e4: e59fc040 ldr ip, [pc, #64] ; 10882c void pit_init(void) { 1087e8: e92d4010 push {r4, lr} //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 1087ec: e3e03c03 mvn r3, #768 ; 0x300 static inline void AT91F_PITInit( AT91PS_PITC pPITC, unsigned int period, unsigned int pit_frequency) { pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 1087f0: e3e04c02 mvn r4, #512 ; 0x200 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 1087f4: e3a0e002 mov lr, #2 1087f8: e503e0ef str lr, [r3, #-239] ; 0xffffff11 static inline void AT91F_PITInit( AT91PS_PITC pPITC, unsigned int period, unsigned int pit_frequency) { pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 1087fc: e504c0cf str ip, [r4, #-207] ; 0xffffff31 pPITC->PITC_PIMR |= AT91C_PITC_PITEN; 108800: e51410cf ldr r1, [r4, #-207] ; 0xffffff31 108804: e3812401 orr r2, r1, #16777216 ; 0x1000000 AT91F_PITC_CfgPMC(); AT91F_PITInit(AT91C_BASE_PITC, 1000000/HZ /* uS */, 48 /* MHz */); sysirq_register(AT91SAM7_SYSIRQ_PIT, &pit_irq); 108808: e3a00000 mov r0, #0 10880c: e59f101c ldr r1, [pc, #28] ; 108830 108810: e50420cf str r2, [r4, #-207] ; 0xffffff31 108814: eb0002b9 bl 109300 //* \brief Enable PIT periodic interrupt //*---------------------------------------------------------------------------- static inline void AT91F_PITEnableInt( AT91PS_PITC pPITC) { pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; 108818: e51400cf ldr r0, [r4, #-207] ; 0xffffff31 10881c: e3803402 orr r3, r0, #33554432 ; 0x2000000 108820: e50430cf str r3, [r4, #-207] ; 0xffffff31 AT91F_PITEnableInt(AT91C_BASE_PITC); } 108824: e8bd4010 pop {r4, lr} 108828: e12fff1e bx lr 10882c: 00007530 .word 0x00007530 108830: 00108678 .word 0x00108678 00108834 : return 0; } /* set frequency of PWM signal to freq */ int pwm_freq_set(int channel, u_int32_t freq) { 108834: e92d40f0 push {r4, r5, r6, r7, lr} u_int32_t overall_div; u_int32_t presc_total; u_int8_t cpre = 0; u_int16_t cprd; if (freq > MCLK) 108838: e59f7100 ldr r7, [pc, #256] ; 108940 10883c: e1510007 cmp r1, r7 return 0; } /* set frequency of PWM signal to freq */ int pwm_freq_set(int channel, u_int32_t freq) { 108840: e1a05000 mov r5, r0 108844: e24dd00c sub sp, sp, #12 108848: e1a04001 mov r4, r1 u_int32_t presc_total; u_int8_t cpre = 0; u_int16_t cprd; if (freq > MCLK) return -ERANGE; 10884c: 83e00021 mvnhi r0, #33 ; 0x21 u_int32_t overall_div; u_int32_t presc_total; u_int8_t cpre = 0; u_int16_t cprd; if (freq > MCLK) 108850: 9a000002 bls 108860 DEBUGPCRF("cpre=%u, cprd=%u", cpre, cprd); AT91F_PWMC_CfgChannel(AT91C_BASE_PWMC, channel, cpre|AT91C_PWMC_CPOL, cprd, 1); return 0; } 108854: e28dd00c add sp, sp, #12 108858: e8bd40f0 pop {r4, r5, r6, r7, lr} 10885c: e12fff1e bx lr u_int16_t cprd; if (freq > MCLK) return -ERANGE; overall_div = MCLK / freq; 108860: e1a00007 mov r0, r7 108864: eb0006f0 bl 10a42c <__aeabi_uidiv> DEBUGPCRF("mclk=%u, freq=%u, overall_div=%u", MCLK, freq, overall_div); 108868: e59f10d4 ldr r1, [pc, #212] ; 108944 u_int16_t cprd; if (freq > MCLK) return -ERANGE; overall_div = MCLK / freq; 10886c: e1a06000 mov r6, r0 DEBUGPCRF("mclk=%u, freq=%u, overall_div=%u", MCLK, freq, overall_div); 108870: e3a02049 mov r2, #73 ; 0x49 108874: e59f00cc ldr r0, [pc, #204] ; 108948 108878: e1a03007 mov r3, r7 10887c: e88d0050 stm sp, {r4, r6} 108880: ebfffd65 bl 107e1c if (overall_div > 0x7fff) { 108884: e3560902 cmp r6, #32768 ; 0x8000 /* divisor is larger than half the maximum CPRD register, we * have to configure prescalers */ presc_total = overall_div >> 15; 108888: 21a007a6 lsrcs r0, r6, #15 static int fhs(u_int32_t val) { int i; for (i = 32; i > 0; i--) { if (val & (1 << (i-1))) 10888c: 23a01001 movcs r1, #1 /* find highest bit set. returns bit (32..1) or 0 in case no bit set */ static int fhs(u_int32_t val) { int i; for (i = 32; i > 0; i--) { 108890: 23a0401f movcs r4, #31 return -ERANGE; overall_div = MCLK / freq; DEBUGPCRF("mclk=%u, freq=%u, overall_div=%u", MCLK, freq, overall_div); if (overall_div > 0x7fff) { 108894: 2a00001d bcs 108910 /* subtract one, because of fhs semantics */ cpre--; } cprd = overall_div / (1 << cpre); } else cprd = overall_div; 108898: e1a01806 lsl r1, r6, #16 10889c: e1a06821 lsr r6, r1, #16 1088a0: e3a04c02 mov r4, #512 ; 0x200 1088a4: e3a03000 mov r3, #0 DEBUGPCRF("cpre=%u, cprd=%u", cpre, cprd); 1088a8: e59f009c ldr r0, [pc, #156] ; 10894c 1088ac: e59f1090 ldr r1, [pc, #144] ; 108944 1088b0: e3a0205a mov r2, #90 ; 0x5a 1088b4: e58d6000 str r6, [sp] 1088b8: ebfffd57 bl 107e1c unsigned int channelId, // \arg PWM channel ID unsigned int mode, // \arg PWM mode unsigned int period, // \arg PWM period unsigned int duty) // \arg PWM duty cycle { pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 1088bc: e59fc08c ldr ip, [pc, #140] ; 108950 1088c0: e2852010 add r2, r5, #16 1088c4: e1a01282 lsl r1, r2, #5 pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; 1088c8: e1a0300c mov r3, ip 1088cc: e1a05285 lsl r5, r5, #5 unsigned int channelId, // \arg PWM channel ID unsigned int mode, // \arg PWM mode unsigned int period, // \arg PWM period unsigned int duty) // \arg PWM duty cycle { pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 1088d0: e081000c add r0, r1, ip pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; 1088d4: e0853003 add r3, r5, r3 unsigned int channelId, // \arg PWM channel ID unsigned int mode, // \arg PWM mode unsigned int period, // \arg PWM period unsigned int duty) // \arg PWM duty cycle { pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 1088d8: e241c90d sub ip, r1, #212992 ; 0x34000 pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; 1088dc: e3a02001 mov r2, #1 unsigned int channelId, // \arg PWM channel ID unsigned int mode, // \arg PWM mode unsigned int period, // \arg PWM period unsigned int duty) // \arg PWM duty cycle { pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 1088e0: e50040ff str r4, [r0, #-255] ; 0xffffff01 pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; 1088e4: e58c2004 str r2, [ip, #4] AT91F_PWMC_CfgChannel(AT91C_BASE_PWMC, channel, cpre|AT91C_PWMC_CPOL, cprd, 1); return 0; 1088e8: e3a00000 mov r0, #0 pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; 1088ec: e5836109 str r6, [r3, #265] ; 0x109 1088f0: eaffffd7 b 108854 /* find highest bit set. returns bit (32..1) or 0 in case no bit set */ static int fhs(u_int32_t val) { int i; for (i = 32; i > 0; i--) { 1088f4: e3530000 cmp r3, #0 1088f8: e1a04003 mov r4, r3 if (val & (1 << (i-1))) 1088fc: e2432001 sub r2, r3, #1 /* find highest bit set. returns bit (32..1) or 0 in case no bit set */ static int fhs(u_int32_t val) { int i; for (i = 32; i > 0; i--) { 108900: 0a000009 beq 10892c if (val & (1 << (i-1))) 108904: e0103211 ands r3, r0, r1, lsl r2 108908: 1a000003 bne 10891c /* find highest bit set. returns bit (32..1) or 0 in case no bit set */ static int fhs(u_int32_t val) { int i; for (i = 32; i > 0; i--) { 10890c: e1a04002 mov r4, r2 if (val & (1 << (i-1))) 108910: e2443001 sub r3, r4, #1 108914: e0102311 ands r2, r0, r1, lsl r3 108918: 0afffff5 beq 1088f4 * have to configure prescalers */ presc_total = overall_div >> 15; /* find highest 2^n fitting in prescaler (highest bit set) */ cpre = fhs(presc_total); if (cpre > 0) { 10891c: e21440ff ands r4, r4, #255 ; 0xff /* subtract one, because of fhs semantics */ cpre--; 108920: 12444001 subne r4, r4, #1 108924: 120440ff andne r4, r4, #255 ; 0xff * have to configure prescalers */ presc_total = overall_div >> 15; /* find highest 2^n fitting in prescaler (highest bit set) */ cpre = fhs(presc_total); if (cpre > 0) { 108928: e1a03004 mov r3, r4 /* subtract one, because of fhs semantics */ cpre--; } cprd = overall_div / (1 << cpre); 10892c: e1a00336 lsr r0, r6, r3 108930: e1a06800 lsl r6, r0, #16 108934: e1a06826 lsr r6, r6, #16 108938: e3844c02 orr r4, r4, #512 ; 0x200 10893c: eaffffd9 b 1088a8 108940: 02dc6c00 .word 0x02dc6c00 108944: 0010ac08 .word 0x0010ac08 108948: 0010ac30 .word 0x0010ac30 10894c: 0010ac5c .word 0x0010ac5c 108950: fffcc0ff .word 0xfffcc0ff 00108954 : return 0; } void pwm_start(int channel) { AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, (1 << channel)); 108954: e3a01001 mov r1, #1 108958: e1a03011 lsl r3, r1, r0 //*---------------------------------------------------------------------------- static inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller unsigned int flag) // \arg Channels IDs to be enabled { pPWM->PWMC_ENA = flag; 10895c: e59f2004 ldr r2, [pc, #4] ; 108968 108960: e50230fb str r3, [r2, #-251] ; 0xffffff05 } 108964: e12fff1e bx lr 108968: fffcc0ff .word 0xfffcc0ff 0010896c : void pwm_stop(int channel) { AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, (1 << channel)); 10896c: e3a01001 mov r1, #1 108970: e1a03011 lsl r3, r1, r0 //*---------------------------------------------------------------------------- static inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller unsigned int flag) // \arg Channels IDs to be enabled { pPWM->PWMC_DIS = flag; 108974: e59f2004 ldr r2, [pc, #4] ; 108980 108978: e50230f7 str r3, [r2, #-247] ; 0xffffff09 } 10897c: e12fff1e bx lr 108980: fffcc0ff .word 0xfffcc0ff 00108984 : void pwm_duty_set_percent(int channel, u_int16_t duty) { 108984: e92d4038 push {r3, r4, r5, lr} u_int32_t tmp = pwm->PWMC_CH[channel].PWMC_CPRDR & 0xffff; 108988: e59f4040 ldr r4, [pc, #64] ; 1089d0 10898c: e1a0c280 lsl ip, r0, #5 108990: e08c4004 add r4, ip, r4 108994: e5942109 ldr r2, [r4, #265] ; 0x109 tmp = tmp << 16; /* extend value by 2^16 */ tmp = tmp / 100; /* tmp = 1 % of extended cprd */ 108998: e59f3034 ldr r3, [pc, #52] ; 1089d4 void pwm_duty_set_percent(int channel, u_int16_t duty) { u_int32_t tmp = pwm->PWMC_CH[channel].PWMC_CPRDR & 0xffff; tmp = tmp << 16; /* extend value by 2^16 */ 10899c: e1a00802 lsl r0, r2, #16 tmp = tmp / 100; /* tmp = 1 % of extended cprd */ 1089a0: e0802093 umull r2, r0, r3, r0 1089a4: e1a052a0 lsr r5, r0, #5 tmp = duty * tmp; /* tmp = 'duty' % of extended cprd */ 1089a8: e0050591 mul r5, r1, r5 tmp = tmp >> 16; /* un-extend tmp (divide by 2^16) */ 1089ac: e1a05825 lsr r5, r5, #16 DEBUGPWM("Writing %u to Update register\n", tmp); 1089b0: e59f0020 ldr r0, [pc, #32] ; 1089d8 1089b4: e59f1020 ldr r1, [pc, #32] ; 1089dc 1089b8: e3a02074 mov r2, #116 ; 0x74 1089bc: e1a03005 mov r3, r5 1089c0: ebfffd15 bl 107e1c static inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller unsigned int channelId, // \arg PWM channel ID unsigned int update) // \arg Channels IDs to be enabled { pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; 1089c4: e5845111 str r5, [r4, #273] ; 0x111 AT91F_PWMC_UpdateChannel(AT91C_BASE_PWMC, channel, tmp); } 1089c8: e8bd4038 pop {r3, r4, r5, lr} 1089cc: e12fff1e bx lr 1089d0: fffcc0ff .word 0xfffcc0ff 1089d4: 51eb851f .word 0x51eb851f 1089d8: 0010ac78 .word 0x0010ac78 1089dc: 0010ac18 .word 0x0010ac18 001089e0 : static int pwm_usb_in(struct req_ctx *rctx) { 1089e0: e92d4010 push {r4, lr} struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; 1089e4: e5903008 ldr r3, [r0, #8] u_int32_t *freq; switch (poh->cmd) { 1089e8: e5d31000 ldrb r1, [r3] 1089ec: e2412041 sub r2, r1, #65 ; 0x41 DEBUGPWM("Writing %u to Update register\n", tmp); AT91F_PWMC_UpdateChannel(AT91C_BASE_PWMC, channel, tmp); } static int pwm_usb_in(struct req_ctx *rctx) { 1089f0: e1a04000 mov r4, r0 struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int32_t *freq; switch (poh->cmd) { 1089f4: e3520004 cmp r2, #4 1089f8: 979ff102 ldrls pc, [pc, r2, lsl #2] 1089fc: ea000007 b 108a20 108a00: 00108a68 .word 0x00108a68 108a04: 00108a14 .word 0x00108a14 108a08: 00108a50 .word 0x00108a50 108a0c: 00108a34 .word 0x00108a34 108a10: 00108a50 .word 0x00108a50 pwm_start(0); else pwm_stop(0); break; case OPENPCD_CMD_PWM_DUTY_SET: pwm_duty_set_percent(0, poh->val); 108a14: e3a00000 mov r0, #0 108a18: e5d31003 ldrb r1, [r3, #3] 108a1c: ebffffd8 bl 108984 break; default: break; } req_ctx_put(rctx); 108a20: e1a00004 mov r0, r4 108a24: ebfffd58 bl 107f8c return 0; 108a28: e3a00000 mov r0, #0 respond: req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING); udp_refill_ep(2); return 1; } 108a2c: e8bd4010 pop {r4, lr} 108a30: e12fff1e bx lr break; case OPENPCD_CMD_PWM_DUTY_GET: goto respond; break; case OPENPCD_CMD_PWM_FREQ_SET: if (rctx->tot_len < sizeof(*poh)+4) 108a34: e1d0e0b6 ldrh lr, [r0, #6] 108a38: e35e0007 cmp lr, #7 108a3c: 9afffff7 bls 108a20 break; freq = (u_int32_t *) ((unsigned char *) poh) + sizeof(*poh); pwm_freq_set(0, *freq); 108a40: e5931010 ldr r1, [r3, #16] 108a44: e3a00000 mov r0, #0 108a48: ebffff79 bl 108834 break; 108a4c: eafffff3 b 108a20 } req_ctx_put(rctx); return 0; respond: req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING); 108a50: e3a01010 mov r1, #16 108a54: ebfffd46 bl 107f74 udp_refill_ep(2); 108a58: e3a00002 mov r0, #2 108a5c: ebfffabd bl 107558 return 1; 108a60: e3a00001 mov r0, #1 108a64: eafffff0 b 108a2c struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int32_t *freq; switch (poh->cmd) { case OPENPCD_CMD_PWM_ENABLE: if (poh->val) 108a68: e5d3c003 ldrb ip, [r3, #3] //*---------------------------------------------------------------------------- static inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller unsigned int flag) // \arg Channels IDs to be enabled { pPWM->PWMC_ENA = flag; 108a6c: e59f3010 ldr r3, [pc, #16] ; 108a84 108a70: e35c0000 cmp ip, #0 108a74: e3a00001 mov r0, #1 108a78: 150300fb strne r0, [r3, #-251] ; 0xffffff05 //*---------------------------------------------------------------------------- static inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller unsigned int flag) // \arg Channels IDs to be enabled { pPWM->PWMC_DIS = flag; 108a7c: 050300f7 streq r0, [r3, #-247] ; 0xffffff09 108a80: eaffffe6 b 108a20 108a84: fffcc0ff .word 0xfffcc0ff 00108a88 : udp_refill_ep(2); return 1; } void pwm_init(void) { 108a88: e92d4008 push {r3, lr} static inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int inputEnable) // \arg PIO to be enabled { // Disable output pPio->PIO_ODR = inputEnable; 108a8c: e3e02c0b mvn r2, #2816 ; 0xb00 108a90: e3a03802 mov r3, #131072 ; 0x20000 unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; pPio->PIO_BSR = periphBEnable; 108a94: e3a0e502 mov lr, #8388608 ; 0x800000 AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; 108a98: e3a0c000 mov ip, #0 static inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int inputEnable) // \arg PIO to be enabled { // Disable output pPio->PIO_ODR = inputEnable; 108a9c: e50230eb str r3, [r2, #-235] ; 0xffffff15 pPio->PIO_PER = inputEnable; 108aa0: e50230ff str r3, [r2, #-255] ; 0xffffff01 AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; 108aa4: e502c08f str ip, [r2, #-143] ; 0xffffff71 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 108aa8: e3e03c03 mvn r3, #768 ; 0x300 unsigned int periphAEnable, // \arg PERIPH A to enable unsigned int periphBEnable) // \arg PERIPH B to enable { pPio->PIO_ASR = periphAEnable; pPio->PIO_BSR = periphBEnable; 108aac: e502e08b str lr, [r2, #-139] ; 0xffffff75 pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode 108ab0: e502e0fb str lr, [r2, #-251] ; 0xffffff05 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 108ab4: e3a02b01 mov r2, #1024 ; 0x400 AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, OPENPCD_PIO_MFIN_PWM); /* Enable Clock for PWM controller */ AT91F_PWMC_CfgPMC(); usb_hdlr_register(&pwm_usb_in, OPENPCD_CMD_CLS_PWM); 108ab8: e3a01004 mov r1, #4 108abc: e50320ef str r2, [r3, #-239] ; 0xffffff11 108ac0: e59f0008 ldr r0, [pc, #8] ; 108ad0 108ac4: ebfffde5 bl 108260 } 108ac8: e8bd4008 pop {r3, lr} 108acc: e12fff1e bx lr 108ad0: 001089e0 .word 0x001089e0 00108ad4 : void pwm_fini(void) { 108ad4: e92d4008 push {r3, lr} usb_hdlr_unregister(OPENPCD_CMD_CLS_PWM); 108ad8: e3a00004 mov r0, #4 108adc: ebfffde4 bl 108274 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_DisablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCDR = periphIds; 108ae0: e3a02b01 mov r2, #1024 ; 0x400 108ae4: e3e03c03 mvn r3, #768 ; 0x300 108ae8: e50320eb str r2, [r3, #-235] ; 0xffffff15 AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC, (1 << AT91C_ID_PWMC)); } 108aec: e8bd4008 pop {r3, lr} 108af0: e12fff1e bx lr 00108af4 : //* \brief Return PIO Interrupt Status //*---------------------------------------------------------------------------- static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status AT91PS_PIO pPio) // \arg pointer to a PIO controller { return pPio->PIO_ISR; 108af4: e3e00c0b mvn r0, #2816 ; 0xb00 AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_PIOA); } /* regular interrupt handler, in case fast forcing for PIOA disabled */ static void pio_irq_demux(void) { 108af8: e92d4008 push {r3, lr} 108afc: e51000b3 ldr r0, [r0, #-179] ; 0xffffff4d u_int32_t pio = AT91F_PIO_GetInterruptStatus(AT91C_BASE_PIOA); __pio_irq_demux(pio); 108b00: e59f300c ldr r3, [pc, #12] ; 108b14 108b04: e1a0e00f mov lr, pc 108b08: e12fff13 bx r3 } 108b0c: e8bd4008 pop {r3, lr} 108b10: e12fff1e bx lr 108b14: 002000e8 .word 0x002000e8 00108b18 : //*---------------------------------------------------------------------------- static inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int flag) // \arg pio interrupt to be enabled { pPio->PIO_IER = flag; 108b18: e3e03c0b mvn r3, #2816 ; 0xb00 108b1c: e50300bf str r0, [r3, #-191] ; 0xffffff41 void pio_irq_enable(u_int32_t pio) { AT91F_PIO_InterruptEnable(AT91C_BASE_PIOA, pio); } 108b20: e12fff1e bx lr 00108b24 : //*---------------------------------------------------------------------------- static inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int flag) // \arg pio interrupt to be disabled { pPio->PIO_IDR = flag; 108b24: e3e03c0b mvn r3, #2816 ; 0xb00 108b28: e50300bb str r0, [r3, #-187] ; 0xffffff45 void pio_irq_disable(u_int32_t pio) { AT91F_PIO_InterruptDisable(AT91C_BASE_PIOA, pio); } 108b2c: e12fff1e bx lr 00108b30 : int pio_irq_register(u_int32_t pio, irq_handler_t *handler) { 108b30: e92d40f0 push {r4, r5, r6, r7, lr} 108b34: e24dd00c sub sp, sp, #12 108b38: e1a04000 mov r4, r0 108b3c: e1a05001 mov r5, r1 u_int8_t num = ffs(pio); 108b40: eb00067f bl 10a544 <__ffssi2> if (num == 0) 108b44: e21000ff ands r0, r0, #255 ; 0xff return -EINVAL; 108b48: 03e00015 mvneq r0, #21 int pio_irq_register(u_int32_t pio, irq_handler_t *handler) { u_int8_t num = ffs(pio); if (num == 0) 108b4c: 1a000002 bne 108b5c AT91F_PIO_CfgInput(AT91C_BASE_PIOA, pio); pirqs.handlers[num] = handler; DEBUGPCRF("registering handler %p for PIOA %u", handler, num); return 0; } 108b50: e28dd00c add sp, sp, #12 108b54: e8bd40f0 pop {r4, r5, r6, r7, lr} 108b58: e12fff1e bx lr { u_int8_t num = ffs(pio); if (num == 0) return -EINVAL; num--; 108b5c: e2400001 sub r0, r0, #1 if (pirqs.handlers[num]) 108b60: e59f6044 ldr r6, [pc, #68] ; 108bac 108b64: e200c0ff and ip, r0, #255 ; 0xff 108b68: e796710c ldr r7, [r6, ip, lsl #2] 108b6c: e3570000 cmp r7, #0 return -EBUSY; 108b70: 13e0000f mvnne r0, #15 if (num == 0) return -EINVAL; num--; if (pirqs.handlers[num]) 108b74: 1afffff5 bne 108b50 108b78: e3e0ec0b mvn lr, #2816 ; 0xb00 108b7c: e50e40bb str r4, [lr, #-187] ; 0xffffff45 return -EBUSY; pio_irq_disable(pio); AT91F_PIO_CfgInput(AT91C_BASE_PIOA, pio); pirqs.handlers[num] = handler; DEBUGPCRF("registering handler %p for PIOA %u", handler, num); 108b80: e59f0028 ldr r0, [pc, #40] ; 108bb0 static inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int inputEnable) // \arg PIO to be enabled { // Disable output pPio->PIO_ODR = inputEnable; 108b84: e50e40eb str r4, [lr, #-235] ; 0xffffff15 108b88: e59f1024 ldr r1, [pc, #36] ; 108bb4 pPio->PIO_PER = inputEnable; 108b8c: e50e40ff str r4, [lr, #-255] ; 0xffffff01 108b90: e3a0206d mov r2, #109 ; 0x6d 108b94: e1a03005 mov r3, r5 if (pirqs.handlers[num]) return -EBUSY; pio_irq_disable(pio); AT91F_PIO_CfgInput(AT91C_BASE_PIOA, pio); pirqs.handlers[num] = handler; 108b98: e786510c str r5, [r6, ip, lsl #2] DEBUGPCRF("registering handler %p for PIOA %u", handler, num); 108b9c: e58dc000 str ip, [sp] 108ba0: ebfffc9d bl 107e1c return 0; 108ba4: e1a00007 mov r0, r7 108ba8: eaffffe8 b 108b50 108bac: 00203844 .word 0x00203844 108bb0: 0010acec .word 0x0010acec 108bb4: 0010acb4 .word 0x0010acb4 00108bb8 : } void pio_irq_unregister(u_int32_t pio) { 108bb8: e92d4010 push {r4, lr} 108bbc: e1a04000 mov r4, r0 u_int8_t num = ffs(pio); 108bc0: eb00065f bl 10a544 <__ffssi2> if (num == 0) 108bc4: e21000ff ands r0, r0, #255 ; 0xff 108bc8: 0a000006 beq 108be8 return; num--; 108bcc: e240c001 sub ip, r0, #1 pio_irq_disable(pio); pirqs.handlers[num] = NULL; 108bd0: e59f3018 ldr r3, [pc, #24] ; 108bf0 108bd4: e20c00ff and r0, ip, #255 ; 0xff //*---------------------------------------------------------------------------- static inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller unsigned int flag) // \arg pio interrupt to be disabled { pPio->PIO_IDR = flag; 108bd8: e3e01c0b mvn r1, #2816 ; 0xb00 108bdc: e3a02000 mov r2, #0 108be0: e50140bb str r4, [r1, #-187] ; 0xffffff45 108be4: e7832100 str r2, [r3, r0, lsl #2] } 108be8: e8bd4010 pop {r4, lr} 108bec: e12fff1e bx lr 108bf0: 00203844 .word 0x00203844 00108bf4 : return 0; } void pio_irq_init(void) { 108bf4: e92d4010 push {r4, lr} AT91F_PIOA_CfgPMC(); AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_PIOA, 108bf8: e3a02000 mov r2, #0 //*---------------------------------------------------------------------------- static inline void AT91F_PMC_EnablePeriphClock ( AT91PS_PMC pPMC, // \arg pointer to PMC controller unsigned int periphIds) // \arg IDs of peripherals to enable { pPMC->PMC_PCER = periphIds; 108bfc: e3a04004 mov r4, #4 108c00: e3e0ec03 mvn lr, #768 ; 0x300 108c04: e59fc02c ldr ip, [pc, #44] ; 108c38 return 0; } void pio_irq_init(void) { 108c08: e24dd008 sub sp, sp, #8 AT91F_PIOA_CfgPMC(); AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_PIOA, 108c0c: e1a03002 mov r3, r2 108c10: e50e40ef str r4, [lr, #-239] ; 0xffffff11 108c14: e59f0020 ldr r0, [pc, #32] ; 108c3c 108c18: e3a01002 mov r1, #2 108c1c: e58dc000 str ip, [sp] 108c20: ebffee59 bl 10458c static inline void AT91F_AIC_EnableIt ( AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { //* Enable the interrupt on the interrupt controller pAic->AIC_IECR = 0x1 << irq_id ; 108c24: e3e03c0f mvn r3, #3840 ; 0xf00 108c28: e5834021 str r4, [r3, #33] ; 0x21 AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &pio_irq_demux); AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_PIOA); } 108c2c: e28dd008 add sp, sp, #8 108c30: e8bd4010 pop {r4, lr} 108c34: e12fff1e bx lr 108c38: 00108af4 .word 0x00108af4 108c3c: fffff000 .word 0xfffff000 00108c40 : return len; } static int gen_usb_rx(struct req_ctx *rctx) { 108c40: e92d4070 push {r4, r5, r6, lr} struct openpcd_compile_version *ver = (struct openpcd_compile_version *)poh->data; u_int32_t len = rctx->tot_len-sizeof(*poh); /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); 108c44: e3a0c004 mov ip, #4 return len; } static int gen_usb_rx(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; 108c48: e5904008 ldr r4, [r0, #8] struct openpcd_compile_version *ver = (struct openpcd_compile_version *)poh->data; u_int32_t len = rctx->tot_len-sizeof(*poh); 108c4c: e1d020b6 ldrh r2, [r0, #6] /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); 108c50: e1c0c0b6 strh ip, [r0, #6] switch (poh->cmd) { 108c54: e5d41000 ldrb r1, [r4] 108c58: e2413001 sub r3, r1, #1 return len; } static int gen_usb_rx(struct req_ctx *rctx) { 108c5c: e24dd008 sub sp, sp, #8 108c60: e1a05000 mov r5, r0 struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; struct openpcd_compile_version *ver = (struct openpcd_compile_version *)poh->data; 108c64: e2841004 add r1, r4, #4 u_int32_t len = rctx->tot_len-sizeof(*poh); /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); switch (poh->cmd) { 108c68: e3530006 cmp r3, #6 108c6c: 979ff103 ldrls pc, [pc, r3, lsl #2] 108c70: ea00000f b 108cb4 108c74: 00108cbc .word 0x00108cbc 108c78: 00108cec .word 0x00108cec 108c7c: 00108d00 .word 0x00108d00 108c80: 00108d34 .word 0x00108d34 108c84: 00108d4c .word 0x00108d4c 108c88: 00108d84 .word 0x00108d84 108c8c: 00108c90 .word 0x00108c90 //*---------------------------------------------------------------------------- static inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, unsigned int reset) { pRSTC->RSTC_RCR = (0xA5000000 | reset); 108c90: e59f1150 ldr r1, [pc, #336] ; 108de8 108c94: e3e03c02 mvn r3, #512 ; 0x200 108c98: e50310ff str r1, [r3, #-255] ; 0xffffff01 108c9c: e5d40001 ldrb r0, [r4, #1] DEBUGP("UNKNOWN\n"); return USB_ERR(USB_ERR_CMD_UNKNOWN); break; } if (poh->flags & OPENPCD_FLAG_RESPOND) 108ca0: e2100001 ands r0, r0, #1 return USB_RET_RESPOND; 108ca4: 13a00c01 movne r0, #256 ; 0x100 return 0; } 108ca8: e28dd008 add sp, sp, #8 108cac: e8bd4070 pop {r4, r5, r6, lr} 108cb0: e12fff1e bx lr #endif break; default: DEBUGP("UNKNOWN\n"); return USB_ERR(USB_ERR_CMD_UNKNOWN); 108cb4: e59f0130 ldr r0, [pc, #304] ; 108dec 108cb8: eafffffa b 108ca8 AT91C_RSTC_PERRST|AT91C_RSTC_EXTRST); break; case OPENPCD_CMD_GET_VERSION: DEBUGP("GET_VERSION\n"); poh->flags |= OPENPCD_FLAG_RESPOND; 108cbc: e5d40001 ldrb r0, [r4, #1] 108cc0: e380e001 orr lr, r0, #1 memcpy(ver, &opcd_version, sizeof(*ver)); 108cc4: e3a02030 mov r2, #48 ; 0x30 108cc8: e1a00001 mov r0, r1 AT91C_RSTC_PERRST|AT91C_RSTC_EXTRST); break; case OPENPCD_CMD_GET_VERSION: DEBUGP("GET_VERSION\n"); poh->flags |= OPENPCD_FLAG_RESPOND; 108ccc: e5c4e001 strb lr, [r4, #1] memcpy(ver, &opcd_version, sizeof(*ver)); 108cd0: e59f1118 ldr r1, [pc, #280] ; 108df0 108cd4: eb00050c bl 10a10c rctx->tot_len += sizeof(*ver); 108cd8: e1d520b6 ldrh r2, [r5, #6] 108cdc: e282c030 add ip, r2, #48 ; 0x30 108ce0: e1c5c0b6 strh ip, [r5, #6] 108ce4: e5d40001 ldrb r0, [r4, #1] break; 108ce8: eaffffec b 108ca0 case OPENPCD_CMD_SET_LED: DEBUGP("SET LED(%u,%u)\n", poh->reg, poh->val); led_switch(poh->reg, poh->val); 108cec: e5d40002 ldrb r0, [r4, #2] 108cf0: e5d41003 ldrb r1, [r4, #3] 108cf4: ebfffc61 bl 107e80 108cf8: e5d40001 ldrb r0, [r4, #1] break; 108cfc: eaffffe7 b 108ca0 case OPENPCD_CMD_GET_SERIAL: DEBUGP("GET SERIAL("); poh->flags |= OPENPCD_FLAG_RESPOND; 108d00: e5d4e001 ldrb lr, [r4, #1] 108d04: e38e2001 orr r2, lr, #1 108d08: e5c42001 strb r2, [r4, #1] #ifdef PCD rctx->tot_len += 4; 108d0c: e1d0c0b6 ldrh ip, [r0, #6] 108d10: e28c3004 add r3, ip, #4 108d14: e1c030b6 strh r3, [r0, #6] if (rc632_get_serial(NULL, (u_int32_t *)poh->data) < 0) { 108d18: e3a00000 mov r0, #0 108d1c: eb00047c bl 109f14 108d20: e3500000 cmp r0, #0 DEBUGP("ERROR) "); return USB_ERR(USB_ERR_CMD_NOT_IMPL); 108d24: b59f00c8 ldrlt r0, [pc, #200] ; 108df4 case OPENPCD_CMD_GET_SERIAL: DEBUGP("GET SERIAL("); poh->flags |= OPENPCD_FLAG_RESPOND; #ifdef PCD rctx->tot_len += 4; if (rc632_get_serial(NULL, (u_int32_t *)poh->data) < 0) { 108d28: baffffde blt 108ca8 108d2c: e5d40001 ldrb r0, [r4, #1] 108d30: eaffffda b 108ca0 switch (poh->cmd) { case OPENPCD_CMD_GET_API_VERSION: DEBUGP("CMD_GET_API_VERSION\n"); poh->flags &= OPENPCD_FLAG_RESPOND; 108d34: e5d40001 ldrb r0, [r4, #1] poh->val = OPENPCD_API_VERSION; 108d38: e3a02001 mov r2, #1 switch (poh->cmd) { case OPENPCD_CMD_GET_API_VERSION: DEBUGP("CMD_GET_API_VERSION\n"); poh->flags &= OPENPCD_FLAG_RESPOND; 108d3c: e2000001 and r0, r0, #1 108d40: e5c40001 strb r0, [r4, #1] poh->val = OPENPCD_API_VERSION; 108d44: e5c42003 strb r2, [r4, #3] break; 108d48: eaffffd4 b 108ca0 case OPENPCD_CMD_GET_ENVIRONMENT: poh->flags &= OPENPCD_FLAG_RESPOND; 108d4c: e5d4c001 ldrb ip, [r4, #1] poh->val = gen_getenv(&poh->data,poh->val); 108d50: e5d46003 ldrb r6, [r4, #3] poh->flags &= OPENPCD_FLAG_RESPOND; poh->val = OPENPCD_API_VERSION; break; case OPENPCD_CMD_GET_ENVIRONMENT: poh->flags &= OPENPCD_FLAG_RESPOND; 108d54: e20ce001 and lr, ip, #1 static int gen_getenv(void* buffer,int len) { if( len >= sizeof(config_stack) ) len=sizeof(config_stack); memcpy(buffer,&config_stack,len); 108d58: e1a00001 mov r0, r1 108d5c: e1a02006 mov r2, r6 poh->flags &= OPENPCD_FLAG_RESPOND; poh->val = OPENPCD_API_VERSION; break; case OPENPCD_CMD_GET_ENVIRONMENT: poh->flags &= OPENPCD_FLAG_RESPOND; 108d60: e5c4e001 strb lr, [r4, #1] static int gen_getenv(void* buffer,int len) { if( len >= sizeof(config_stack) ) len=sizeof(config_stack); memcpy(buffer,&config_stack,len); 108d64: e59f108c ldr r1, [pc, #140] ; 108df8 108d68: eb0004e7 bl 10a10c poh->val = OPENPCD_API_VERSION; break; case OPENPCD_CMD_GET_ENVIRONMENT: poh->flags &= OPENPCD_FLAG_RESPOND; poh->val = gen_getenv(&poh->data,poh->val); 108d6c: e5c46003 strb r6, [r4, #3] rctx->tot_len += poh->val; 108d70: e1d530b6 ldrh r3, [r5, #6] 108d74: e0866003 add r6, r6, r3 108d78: e1c560b6 strh r6, [r5, #6] 108d7c: e5d40001 ldrb r0, [r4, #1] DEBUGP("CMD_GET_ENVIRONMENT(res_len=%u)\n", poh->val); break; 108d80: eaffffc6 b 108ca0 static int gen_usb_rx(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; struct openpcd_compile_version *ver = (struct openpcd_compile_version *)poh->data; u_int32_t len = rctx->tot_len-sizeof(*poh); 108d84: e2422004 sub r2, r2, #4 u_int32_t *dst; if( len >= sizeof(config_stack) ) len=sizeof(config_stack); memcpy(&config_stack,buffer,len); 108d88: e35200ff cmp r2, #255 ; 0xff 108d8c: 83a02c01 movhi r2, #256 ; 0x100 108d90: e59f0060 ldr r0, [pc, #96] ; 108df8 108d94: eb0004dc bl 10a10c /* retrieve current content to allow partial flashing */ /* flash changes */ dst=(u_int32_t*)CONFIG_AREA_ADDR; for(i=0;i 108dac: e59f3048 ldr r3, [pc, #72] ; 108dfc 108db0: e59f1040 ldr r1, [pc, #64] ; 108df8 *dst++=config_stack[i]; 108db4: e59d0004 ldr r0, [sp, #4] 108db8: e7912100 ldr r2, [r1, r0, lsl #2] 108dbc: e4832004 str r2, [r3], #4 /* retrieve current content to allow partial flashing */ /* flash changes */ dst=(u_int32_t*)CONFIG_AREA_ADDR; for(i=0;i *dst++=config_stack[i]; flash_page(CONFIG_AREA_ADDR); 108dd8: e59f001c ldr r0, [pc, #28] ; 108dfc 108ddc: eb00015d bl 109358 108de0: e5d40001 ldrb r0, [r4, #1] break; case OPENPCD_CMD_SET_ENVIRONMENT: DEBUGP("CMD_SET_ENVIRONMENT (in_len=%u)\n", len); gen_setenv(&poh->data,len); break; 108de4: eaffffad b 108ca0 108de8: a500000d .word 0xa500000d 108dec: 00000301 .word 0x00000301 108df0: 0010ab0c .word 0x0010ab0c 108df4: 00000302 .word 0x00000302 108df8: 00203a18 .word 0x00203a18 108dfc: 0011ff00 .word 0x0011ff00 00108e00 : return USB_RET_RESPOND; return 0; } void usbcmd_gen_init(void) { 108e00: e92d4008 push {r3, lr} DEBUGP("Inititalizing usbcmd_gen_init\n"); /* setup FLASH write support for environment storage */ flash_init(); 108e04: eb00017b bl 1093f8 /* retrieve default data from flash */ memcpy(&config_stack,CONFIG_AREA_ADDR,sizeof(config_stack)); 108e08: e59f101c ldr r1, [pc, #28] ; 108e2c 108e0c: e3a02c01 mov r2, #256 ; 0x100 108e10: e59f0018 ldr r0, [pc, #24] ; 108e30 108e14: eb0004bc bl 10a10c usb_hdlr_register(&gen_usb_rx, OPENPCD_CMD_CLS_GENERIC); 108e18: e3a01000 mov r1, #0 108e1c: e59f0010 ldr r0, [pc, #16] ; 108e34 108e20: ebfffd0e bl 108260 } 108e24: e8bd4008 pop {r3, lr} 108e28: e12fff1e bx lr 108e2c: 0011ff00 .word 0x0011ff00 108e30: 00203a18 .word 0x00203a18 108e34: 00108c40 .word 0x00108c40 00108e38 : #ifdef WDT_DEBUG #undef WDT_DEBUG #endif/*WDT_DEBUG*/ static void wdt_irq(u_int32_t sr) { 108e38: e92d4008 push {r3, lr} DEBUGPCRF("================> WATCHDOG EXPIRED !!!!!"); 108e3c: e59f0010 ldr r0, [pc, #16] ; 108e54 108e40: e59f1010 ldr r1, [pc, #16] ; 108e58 108e44: e3a02020 mov r2, #32 108e48: ebfffbf3 bl 107e1c } 108e4c: e8bd4008 pop {r3, lr} 108e50: e12fff1e bx lr 108e54: 0010ad24 .word 0x0010ad24 108e58: 0010ad1c .word 0x0010ad1c 00108e5c : //* \brief Restart Watchdog //*---------------------------------------------------------------------------- static inline void AT91F_WDTRestart( AT91PS_WDTC pWDTC) { pWDTC->WDTC_WDCR = 0xA5000001; 108e5c: e59f2008 ldr r2, [pc, #8] ; 108e6c 108e60: e3e03c02 mvn r3, #512 ; 0x200 108e64: e50320bf str r2, [r3, #-191] ; 0xffffff41 void wdt_restart(void) { AT91F_WDTRestart(AT91C_BASE_WDTC); } 108e68: e12fff1e bx lr 108e6c: a5000001 .word 0xa5000001 00108e70 : void wdt_init(void) { 108e70: e92d4008 push {r3, lr} sysirq_register(AT91SAM7_SYSIRQ_WDT, &wdt_irq); 108e74: e3a00003 mov r0, #3 108e78: e59f1014 ldr r1, [pc, #20] ; 108e94 108e7c: eb00011f bl 109300 //*---------------------------------------------------------------------------- static inline void AT91F_WDTSetMode( AT91PS_WDTC pWDTC, unsigned int Mode) { pWDTC->WDTC_WDMR = Mode; 108e80: e59f2010 ldr r2, [pc, #16] ; 108e98 108e84: e3e03c02 mvn r3, #512 ; 0x200 108e88: e50320bb str r2, [r3, #-187] ; 0xffffff45 AT91C_WDTC_WDFIEN); #else AT91F_WDTSetMode(AT91C_BASE_WDTC, (0x80 << 16) | AT91C_WDTC_WDRSTEN | 0x80); #endif } 108e8c: e8bd4008 pop {r3, lr} 108e90: e12fff1e bx lr 108e94: 00108e38 .word 0x00108e38 108e98: 00802080 .word 0x00802080 00108e9c : }; static struct blinker blink_state[NUM_LEDS]; static void blinkcode_cb(void *data) { 108e9c: e92d4030 push {r4, r5, lr} /* we got called back by the timer */ struct blinker *bl = data; DEBUGPCRF("(jiffies=%lu, data=%p, state=%u)", 108ea0: e59f513c ldr r5, [pc, #316] ; 108fe4 108ea4: e5d0c010 ldrb ip, [r0, #16] }; static struct blinker blink_state[NUM_LEDS]; static void blinkcode_cb(void *data) { 108ea8: e24dd00c sub sp, sp, #12 108eac: e1a04000 mov r4, r0 /* we got called back by the timer */ struct blinker *bl = data; DEBUGPCRF("(jiffies=%lu, data=%p, state=%u)", 108eb0: e5953000 ldr r3, [r5] 108eb4: e59f012c ldr r0, [pc, #300] ; 108fe8 108eb8: e59f112c ldr r1, [pc, #300] ; 108fec 108ebc: e3a0202a mov r2, #42 ; 0x2a 108ec0: e88d1010 stm sp, {r4, ip} 108ec4: ebfffbd4 bl 107e1c jiffies, data, bl->state); switch (bl->state) { 108ec8: e5d43010 ldrb r3, [r4, #16] 108ecc: e3530005 cmp r3, #5 108ed0: 979ff103 ldrls pc, [pc, r3, lsl #2] 108ed4: ea00000d b 108f10 108ed8: 00108f34 .word 0x00108f34 108edc: 00108f60 .word 0x00108f60 108ee0: 00108f84 .word 0x00108f84 108ee4: 00108fa8 .word 0x00108fa8 108ee8: 00108ef0 .word 0x00108ef0 108eec: 00108f24 .word 0x00108f24 if (bl->cur <= 0) bl->state = BLINKCODE_STATE_DONE; break; case BLINKCODE_STATE_BLINK_ON: /* we've been on, turn off */ led_switch(bl->led, 0); 108ef0: e5d4001c ldrb r0, [r4, #28] 108ef4: e3a01000 mov r1, #0 108ef8: ebfffbe0 bl 107e80 bl->state = BLINKCODE_STATE_BLINK_OFF; bl->timer.expires = jiffies + TIME_BLINK; 108efc: e5951000 ldr r1, [r5] bl->state = BLINKCODE_STATE_DONE; break; case BLINKCODE_STATE_BLINK_ON: /* we've been on, turn off */ led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_BLINK_OFF; 108f00: e3a02003 mov r2, #3 bl->timer.expires = jiffies + TIME_BLINK; 108f04: e2810019 add r0, r1, #25 bl->state = BLINKCODE_STATE_DONE; break; case BLINKCODE_STATE_BLINK_ON: /* we've been on, turn off */ led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_BLINK_OFF; 108f08: e5c42010 strb r2, [r4, #16] bl->timer.expires = jiffies + TIME_BLINK; 108f0c: e5840004 str r0, [r4, #4] led_switch(bl->led, 0); return; break; } /* default case: re-add the timer */ timer_add(&bl->timer); 108f10: e1a00004 mov r0, r4 108f14: ebfffdf9 bl 108700 } 108f18: e28dd00c add sp, sp, #12 108f1c: e8bd4030 pop {r4, r5, lr} 108f20: e12fff1e bx lr bl->state = BLINKCODE_STATE_BLINK_OFF; bl->timer.expires = jiffies + TIME_BLINK; break; case BLINKCODE_STATE_DONE: /* we've been on, turn off */ led_switch(bl->led, 0); 108f24: e5d4001c ldrb r0, [r4, #28] 108f28: e3a01000 mov r1, #0 108f2c: ebfffbd3 bl 107e80 return; 108f30: eafffff8 b 108f18 DEBUGPCRF("(jiffies=%lu, data=%p, state=%u)", jiffies, data, bl->state); switch (bl->state) { case BLINKCODE_STATE_NONE: led_switch(bl->led, 0); 108f34: e5d4001c ldrb r0, [r4, #28] 108f38: e3a01000 mov r1, #0 108f3c: ebfffbcf bl 107e80 bl->state = BLINKCODE_STATE_SILENT; bl->timer.expires = jiffies + TIME_SILENT; 108f40: e5953000 ldr r3, [r5] bl->cur = bl->num; 108f44: e5940014 ldr r0, [r4, #20] jiffies, data, bl->state); switch (bl->state) { case BLINKCODE_STATE_NONE: led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_SILENT; bl->timer.expires = jiffies + TIME_SILENT; 108f48: e2832064 add r2, r3, #100 ; 0x64 DEBUGPCRF("(jiffies=%lu, data=%p, state=%u)", jiffies, data, bl->state); switch (bl->state) { case BLINKCODE_STATE_NONE: led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_SILENT; 108f4c: e3a01001 mov r1, #1 108f50: e5c41010 strb r1, [r4, #16] bl->timer.expires = jiffies + TIME_SILENT; 108f54: e5842004 str r2, [r4, #4] bl->cur = bl->num; 108f58: e5840018 str r0, [r4, #24] break; 108f5c: eaffffeb b 108f10 case BLINKCODE_STATE_SILENT: /* we've finished the period of silence, turn led on */ led_switch(bl->led, 1); 108f60: e5d4001c ldrb r0, [r4, #28] 108f64: e3a01001 mov r1, #1 108f68: ebfffbc4 bl 107e80 bl->state = BLINKCODE_STATE_INIT; bl->timer.expires = jiffies + TIME_INIT; 108f6c: e5952000 ldr r2, [r5] bl->cur = bl->num; break; case BLINKCODE_STATE_SILENT: /* we've finished the period of silence, turn led on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_INIT; 108f70: e3a00002 mov r0, #2 bl->timer.expires = jiffies + TIME_INIT; 108f74: e282c064 add ip, r2, #100 ; 0x64 bl->cur = bl->num; break; case BLINKCODE_STATE_SILENT: /* we've finished the period of silence, turn led on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_INIT; 108f78: e5c40010 strb r0, [r4, #16] bl->timer.expires = jiffies + TIME_INIT; 108f7c: e584c004 str ip, [r4, #4] break; 108f80: eaffffe2 b 108f10 case BLINKCODE_STATE_INIT: /* we've finished the period of init */ led_switch(bl->led, 0); 108f84: e3a01000 mov r1, #0 108f88: e5d4001c ldrb r0, [r4, #28] 108f8c: ebfffbbb bl 107e80 bl->state = BLINKCODE_STATE_BLINK_OFF; bl->timer.expires = jiffies + TIME_INIT; 108f90: e595c000 ldr ip, [r5] bl->timer.expires = jiffies + TIME_INIT; break; case BLINKCODE_STATE_INIT: /* we've finished the period of init */ led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_BLINK_OFF; 108f94: e3a03003 mov r3, #3 bl->timer.expires = jiffies + TIME_INIT; 108f98: e28c1064 add r1, ip, #100 ; 0x64 bl->timer.expires = jiffies + TIME_INIT; break; case BLINKCODE_STATE_INIT: /* we've finished the period of init */ led_switch(bl->led, 0); bl->state = BLINKCODE_STATE_BLINK_OFF; 108f9c: e5c43010 strb r3, [r4, #16] bl->timer.expires = jiffies + TIME_INIT; 108fa0: e5841004 str r1, [r4, #4] break; 108fa4: eaffffd9 b 108f10 case BLINKCODE_STATE_BLINK_OFF: /* we've been off, turn on */ led_switch(bl->led, 1); 108fa8: e5d4001c ldrb r0, [r4, #28] 108fac: e3a01001 mov r1, #1 108fb0: ebfffbb2 bl 107e80 bl->state = BLINKCODE_STATE_BLINK_ON; bl->cur--; 108fb4: e5943018 ldr r3, [r4, #24] bl->timer.expires = jiffies + TIME_BLINK; 108fb8: e595c000 ldr ip, [r5] break; case BLINKCODE_STATE_BLINK_OFF: /* we've been off, turn on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_BLINK_ON; bl->cur--; 108fbc: e2430001 sub r0, r3, #1 bl->timer.expires = jiffies + TIME_BLINK; if (bl->cur <= 0) 108fc0: e3500000 cmp r0, #0 case BLINKCODE_STATE_BLINK_OFF: /* we've been off, turn on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_BLINK_ON; bl->cur--; bl->timer.expires = jiffies + TIME_BLINK; 108fc4: e28c2019 add r2, ip, #25 bl->timer.expires = jiffies + TIME_INIT; break; case BLINKCODE_STATE_BLINK_OFF: /* we've been off, turn on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_BLINK_ON; 108fc8: e3a01004 mov r1, #4 bl->cur--; 108fcc: e5840018 str r0, [r4, #24] bl->timer.expires = jiffies + TIME_BLINK; if (bl->cur <= 0) bl->state = BLINKCODE_STATE_DONE; 108fd0: d3a00005 movle r0, #5 bl->timer.expires = jiffies + TIME_INIT; break; case BLINKCODE_STATE_BLINK_OFF: /* we've been off, turn on */ led_switch(bl->led, 1); bl->state = BLINKCODE_STATE_BLINK_ON; 108fd4: e5c41010 strb r1, [r4, #16] bl->cur--; bl->timer.expires = jiffies + TIME_BLINK; 108fd8: e5842004 str r2, [r4, #4] if (bl->cur <= 0) bl->state = BLINKCODE_STATE_DONE; 108fdc: d5c40010 strble r0, [r4, #16] 108fe0: eaffffca b 108f10 108fe4: 00203a14 .word 0x00203a14 108fe8: 0010ad78 .word 0x0010ad78 108fec: 0010ad58 .word 0x0010ad58 00108ff0 : /* default case: re-add the timer */ timer_add(&bl->timer); } void blinkcode_set(int led, enum blinkcode_num num) { 108ff0: e92d4070 push {r4, r5, r6, lr} DEBUGPCRF("(jiffies=%lu, led=%u, num=%u)", jiffies, led, num); 108ff4: e59f6074 ldr r6, [pc, #116] ; 109070 /* default case: re-add the timer */ timer_add(&bl->timer); } void blinkcode_set(int led, enum blinkcode_num num) { 108ff8: e24dd008 sub sp, sp, #8 108ffc: e1a04000 mov r4, r0 109000: e1a05001 mov r5, r1 DEBUGPCRF("(jiffies=%lu, led=%u, num=%u)", jiffies, led, num); 109004: e58d4000 str r4, [sp] 109008: e5963000 ldr r3, [r6] 10900c: e59f0060 ldr r0, [pc, #96] ; 109074 109010: e59f1060 ldr r1, [pc, #96] ; 109078 109014: e3a02059 mov r2, #89 ; 0x59 if (--led > NUM_LEDS) 109018: e2444001 sub r4, r4, #1 timer_add(&bl->timer); } void blinkcode_set(int led, enum blinkcode_num num) { DEBUGPCRF("(jiffies=%lu, led=%u, num=%u)", jiffies, led, num); 10901c: e58d5004 str r5, [sp, #4] 109020: ebfffb7d bl 107e1c if (--led > NUM_LEDS) 109024: e3540002 cmp r4, #2 109028: da000002 ble 109038 blink_state[led].state = BLINKCODE_STATE_NONE; blink_state[led].timer.expires = jiffies; if (num != BLINKCODE_NONE) timer_add(&blink_state[led].timer); } 10902c: e28dd008 add sp, sp, #8 109030: e8bd4070 pop {r4, r5, r6, lr} 109034: e12fff1e bx lr DEBUGPCRF("(jiffies=%lu, led=%u, num=%u)", jiffies, led, num); if (--led > NUM_LEDS) return; timer_del(&blink_state[led].timer); 109038: e59f003c ldr r0, [pc, #60] ; 10907c 10903c: e0804284 add r4, r0, r4, lsl #5 109040: e1a00004 mov r0, r4 109044: ebfffd6d bl 108600 blink_state[led].num = num; blink_state[led].state = BLINKCODE_STATE_NONE; blink_state[led].timer.expires = jiffies; 109048: e5963000 ldr r3, [r6] return; timer_del(&blink_state[led].timer); blink_state[led].num = num; blink_state[led].state = BLINKCODE_STATE_NONE; 10904c: e3a02000 mov r2, #0 blink_state[led].timer.expires = jiffies; if (num != BLINKCODE_NONE) 109050: e3550000 cmp r5, #0 if (--led > NUM_LEDS) return; timer_del(&blink_state[led].timer); blink_state[led].num = num; 109054: e5845014 str r5, [r4, #20] blink_state[led].state = BLINKCODE_STATE_NONE; 109058: e5c42010 strb r2, [r4, #16] blink_state[led].timer.expires = jiffies; 10905c: e5843004 str r3, [r4, #4] if (num != BLINKCODE_NONE) 109060: 0afffff1 beq 10902c timer_add(&blink_state[led].timer); 109064: e1a00004 mov r0, r4 109068: ebfffda4 bl 108700 10906c: eaffffee b 10902c 109070: 00203a14 .word 0x00203a14 109074: 0010ada4 .word 0x0010ada4 109078: 0010ad68 .word 0x0010ad68 10907c: 002038cc .word 0x002038cc 00109080 : void blinkcode_init(void) { int i; for (i = 0; i < NUM_LEDS; i++) { blink_state[i].num = 0; 109080: e59f303c ldr r3, [pc, #60] ; 1090c4 109084: e3a02000 mov r2, #0 blink_state[i].state = BLINKCODE_STATE_NONE; blink_state[i].led = i+1; blink_state[i].timer.data = &blink_state[i]; blink_state[i].timer.function = &blinkcode_cb; 109088: e59f1038 ldr r1, [pc, #56] ; 1090c8 for (i = 0; i < NUM_LEDS; i++) { blink_state[i].num = 0; blink_state[i].state = BLINKCODE_STATE_NONE; blink_state[i].led = i+1; blink_state[i].timer.data = &blink_state[i]; 10908c: e2830020 add r0, r3, #32 void blinkcode_init(void) { int i; for (i = 0; i < NUM_LEDS; i++) { blink_state[i].num = 0; 109090: e5832014 str r2, [r3, #20] blink_state[i].state = BLINKCODE_STATE_NONE; 109094: e5c32010 strb r2, [r3, #16] blink_state[i].led = i+1; 109098: e3a0c001 mov ip, #1 void blinkcode_init(void) { int i; for (i = 0; i < NUM_LEDS; i++) { blink_state[i].num = 0; 10909c: e5832034 str r2, [r3, #52] ; 0x34 blink_state[i].state = BLINKCODE_STATE_NONE; 1090a0: e5c32030 strb r2, [r3, #48] ; 0x30 blink_state[i].led = i+1; 1090a4: e3a02002 mov r2, #2 1090a8: e5c3c01c strb ip, [r3, #28] blink_state[i].timer.data = &blink_state[i]; 1090ac: e583300c str r3, [r3, #12] blink_state[i].timer.function = &blinkcode_cb; 1090b0: e5831008 str r1, [r3, #8] int i; for (i = 0; i < NUM_LEDS; i++) { blink_state[i].num = 0; blink_state[i].state = BLINKCODE_STATE_NONE; blink_state[i].led = i+1; 1090b4: e5c3203c strb r2, [r3, #60] ; 0x3c blink_state[i].timer.data = &blink_state[i]; 1090b8: e583002c str r0, [r3, #44] ; 0x2c blink_state[i].timer.function = &blinkcode_cb; 1090bc: e5831028 str r1, [r3, #40] ; 0x28 } } 1090c0: e12fff1e bx lr 1090c4: 002038cc .word 0x002038cc 1090c8: 00108e9c .word 0x00108e9c 001090cc : /* Somehow Atmel decided to do really stupid interrupt sharing * for commonly-used interrupts such as the timer irq */ /* dbgu */ if (*AT91C_DBGU_IMR) { 1090cc: e3e02000 mvn r2, #0 #include "../openpcd.h" static sysirq_hdlr *sysirq_hdlrs[AT91SAM7_SYSIRQ_COUNT]; static void sys_irq(void) { 1090d0: e92d4008 push {r3, lr} /* Somehow Atmel decided to do really stupid interrupt sharing * for commonly-used interrupts such as the timer irq */ /* dbgu */ if (*AT91C_DBGU_IMR) { 1090d4: e5123def ldr r3, [r2, #-3567] ; 0xfffff211 1090d8: e3530000 cmp r3, #0 1090dc: 0a000003 beq 1090f0 sr = *AT91C_DBGU_CSR; 1090e0: e5120deb ldr r0, [r2, #-3563] ; 0xfffff215 if (sr & *AT91C_DBGU_IMR) { 1090e4: e5121def ldr r1, [r2, #-3567] ; 0xfffff211 1090e8: e1110000 tst r1, r0 1090ec: 1a000062 bne 10927c DEBUGP(") "); } } /* pit_irq */ if (*AT91C_PITC_PIMR & AT91C_PITC_PITIEN) { 1090f0: e3e02000 mvn r2, #0 1090f4: e51232cf ldr r3, [r2, #-719] ; 0xfffffd31 1090f8: e3130402 tst r3, #33554432 ; 0x2000000 1090fc: 0a000002 beq 10910c sr = *AT91C_PITC_PISR; 109100: e51202cb ldr r0, [r2, #-715] ; 0xfffffd35 if (sr & AT91C_PITC_PITS) { 109104: e3100001 tst r0, #1 109108: 1a000054 bne 109260 } } } /* rtt_irq */ if (*AT91C_RTTC_RTMR & (AT91C_RTTC_ALMIEN|AT91C_RTTC_RTTINCIEN)) { 10910c: e3e02000 mvn r2, #0 109110: e51232df ldr r3, [r2, #-735] ; 0xfffffd21 109114: e3130803 tst r3, #196608 ; 0x30000 109118: 0a000002 beq 109128 sr = *AT91C_RTTC_RTSR; 10911c: e51202d3 ldr r0, [r2, #-723] ; 0xfffffd2d if (sr) { 109120: e3500000 cmp r0, #0 109124: 1a000046 bne 109244 DEBUGP(") "); } } /* pmc_irq */ if (*AT91C_PMC_IMR) { 109128: e3e02000 mvn r2, #0 10912c: e5123393 ldr r3, [r2, #-915] ; 0xfffffc6d 109130: e3530000 cmp r3, #0 109134: 0a000003 beq 109148 sr = *AT91C_PMC_SR; 109138: e5120397 ldr r0, [r2, #-919] ; 0xfffffc69 if (sr & *AT91C_PMC_IMR) { 10913c: e5121393 ldr r1, [r2, #-915] ; 0xfffffc6d 109140: e1110000 tst r1, r0 109144: 1a000037 bne 109228 DEBUGP(") "); } } /* rstc_irq */ if (*AT91C_RSTC_RMR & (AT91C_RSTC_URSTIEN|AT91C_RSTC_BODIEN)) { 109148: e3e02000 mvn r2, #0 10914c: e51212f7 ldr r1, [r2, #-759] ; 0xfffffd09 109150: e59fc1a0 ldr ip, [pc, #416] ; 1092f8 109154: e001300c and r3, r1, ip 109158: e3530000 cmp r3, #0 10915c: 0a000002 beq 10916c sr = *AT91C_RSTC_RSR; 109160: e51202fb ldr r0, [r2, #-763] ; 0xfffffd05 if (sr & (AT91C_RSTC_URSTS|AT91C_RSTC_BODSTS)) { 109164: e3100003 tst r0, #3 109168: 1a000027 bne 10920c DEBUGP(") "); } } /* mc_irq */ if (*AT91C_MC_FMR & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) { 10916c: e3e03000 mvn r3, #0 109170: e513209f ldr r2, [r3, #-159] ; 0xffffff61 109174: e312000c tst r2, #12 109178: 0a00000b beq 1091ac sr = *AT91C_MC_FSR; 10917c: e5130097 ldr r0, [r3, #-151] ; 0xffffff69 if ((*AT91C_MC_FMR & AT91C_MC_LOCKE && (sr & AT91C_MC_LOCKE))|| 109180: e513309f ldr r3, [r3, #-159] ; 0xffffff61 109184: e3130004 tst r3, #4 109188: 0a000018 beq 1091f0 10918c: e3100004 tst r0, #4 109190: 0a000016 beq 1091f0 (*AT91C_MC_FMR & AT91C_MC_PROGE && (sr & AT91C_MC_PROGE))){ DEBUGP("EFC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_EFC]) { 109194: e59f2160 ldr r2, [pc, #352] ; 1092fc 109198: e5923008 ldr r3, [r2, #8] 10919c: e3530000 cmp r3, #0 1091a0: 0a00004f beq 1092e4 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_EFC](sr); 1091a4: e1a0e00f mov lr, pc 1091a8: e12fff13 bx r3 DEBUGP(") "); } } /* wdt_irq */ if (*AT91C_WDTC_WDMR & AT91C_WDTC_WDFIEN) { 1091ac: e3e03000 mvn r3, #0 1091b0: e51312bb ldr r1, [r3, #-699] ; 0xfffffd45 1091b4: e3110a01 tst r1, #4096 ; 0x1000 1091b8: 0a000007 beq 1091dc sr = *AT91C_WDTC_WDSR; 1091bc: e51302b7 ldr r0, [r3, #-695] ; 0xfffffd49 if (sr) { 1091c0: e3500000 cmp r0, #0 1091c4: 0a000004 beq 1091dc DEBUGP("WDT("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_WDT]) { 1091c8: e59f212c ldr r2, [pc, #300] ; 1092fc 1091cc: e592300c ldr r3, [r2, #12] 1091d0: e3530000 cmp r3, #0 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_WDT](sr); 1091d4: 11a0e00f movne lr, pc 1091d8: 112fff13 bxne r3 static inline void AT91F_AIC_ClearIt ( AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id) // \arg interrupt number to initialize { //* Clear the interrupt on the Interrupt Controller ( if one is pending ) pAic->AIC_ICCR = (0x1 << irq_id); 1091dc: e3a00002 mov r0, #2 1091e0: e3e03c0f mvn r3, #3840 ; 0xf00 1091e4: e5830029 str r0, [r3, #41] ; 0x29 DEBUGP(") "); } } AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_SYS); DEBUGPCR("END"); } 1091e8: e8bd4008 pop {r3, lr} 1091ec: e12fff1e bx lr /* mc_irq */ if (*AT91C_MC_FMR & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) { sr = *AT91C_MC_FSR; if ((*AT91C_MC_FMR & AT91C_MC_LOCKE && (sr & AT91C_MC_LOCKE))|| (*AT91C_MC_FMR & AT91C_MC_PROGE && (sr & AT91C_MC_PROGE))){ 1091f0: e3e01000 mvn r1, #0 1091f4: e511c09f ldr ip, [r1, #-159] ; 0xffffff61 } /* mc_irq */ if (*AT91C_MC_FMR & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) { sr = *AT91C_MC_FSR; if ((*AT91C_MC_FMR & AT91C_MC_LOCKE && (sr & AT91C_MC_LOCKE))|| 1091f8: e31c0008 tst ip, #8 1091fc: 0affffea beq 1091ac (*AT91C_MC_FMR & AT91C_MC_PROGE && (sr & AT91C_MC_PROGE))){ 109200: e3100008 tst r0, #8 109204: 0affffe8 beq 1091ac 109208: eaffffe1 b 109194 /* rstc_irq */ if (*AT91C_RSTC_RMR & (AT91C_RSTC_URSTIEN|AT91C_RSTC_BODIEN)) { sr = *AT91C_RSTC_RSR; if (sr & (AT91C_RSTC_URSTS|AT91C_RSTC_BODSTS)) { DEBUGP("RSTC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_RSTC]) { 10920c: e59f30e8 ldr r3, [pc, #232] ; 1092fc 109210: e5933014 ldr r3, [r3, #20] 109214: e3530000 cmp r3, #0 109218: 0a000025 beq 1092b4 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_RSTC](sr); 10921c: e1a0e00f mov lr, pc 109220: e12fff13 bx r3 109224: eaffffd0 b 10916c /* pmc_irq */ if (*AT91C_PMC_IMR) { sr = *AT91C_PMC_SR; if (sr & *AT91C_PMC_IMR) { DEBUGP("PMC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_PMC]) { 109228: e59fc0cc ldr ip, [pc, #204] ; 1092fc 10922c: e59c3018 ldr r3, [ip, #24] 109230: e3530000 cmp r3, #0 109234: 0a00001b beq 1092a8 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_PMC](sr); 109238: e1a0e00f mov lr, pc 10923c: e12fff13 bx r3 109240: eaffffc0 b 109148 /* rtt_irq */ if (*AT91C_RTTC_RTMR & (AT91C_RTTC_ALMIEN|AT91C_RTTC_RTTINCIEN)) { sr = *AT91C_RTTC_RTSR; if (sr) { DEBUGP("RTT("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_RTT]) { 109244: e59f10b0 ldr r1, [pc, #176] ; 1092fc 109248: e5913010 ldr r3, [r1, #16] 10924c: e3530000 cmp r3, #0 109250: 0a000010 beq 109298 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_RTT](sr); 109254: e1a0e00f mov lr, pc 109258: e12fff13 bx r3 10925c: eaffffb1 b 109128 /* pit_irq */ if (*AT91C_PITC_PIMR & AT91C_PITC_PITIEN) { sr = *AT91C_PITC_PISR; if (sr & AT91C_PITC_PITS) { if (sysirq_hdlrs[AT91SAM7_SYSIRQ_PIT]) { 109260: e59f1094 ldr r1, [pc, #148] ; 1092fc 109264: e5913000 ldr r3, [r1] 109268: e3530000 cmp r3, #0 10926c: 0a000018 beq 1092d4 sysirq_hdlrs[AT91SAM7_SYSIRQ_PIT](sr); 109270: e1a0e00f mov lr, pc 109274: e12fff13 bx r3 109278: eaffffa3 b 10910c /* dbgu */ if (*AT91C_DBGU_IMR) { sr = *AT91C_DBGU_CSR; if (sr & *AT91C_DBGU_IMR) { DEBUGP("DBGU("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_DBGU]) { 10927c: e59fc078 ldr ip, [pc, #120] ; 1092fc 109280: e59c3004 ldr r3, [ip, #4] 109284: e3530000 cmp r3, #0 109288: 0a00000e beq 1092c8 DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_DBGU](sr); 10928c: e1a0e00f mov lr, pc 109290: e12fff13 bx r3 109294: eaffff95 b 1090f0 DEBUGP("RTT("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_RTT]) { DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_RTT](sr); } else { *AT91C_RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN| 109298: e51202df ldr r0, [r2, #-735] ; 0xfffffd21 10929c: e3c0c803 bic ip, r0, #196608 ; 0x30000 1092a0: e502c2df str ip, [r2, #-735] ; 0xfffffd21 1092a4: eaffff9f b 109128 DEBUGP("PMC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_PMC]) { DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_PMC](sr); } else { *AT91C_PMC_IDR = *AT91C_PMC_IMR; 1092a8: e5120393 ldr r0, [r2, #-915] ; 0xfffffc6d 1092ac: e502039b str r0, [r2, #-923] ; 0xfffffc65 1092b0: eaffffa4 b 109148 DEBUGP("RSTC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_RSTC]) { DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_RSTC](sr); } else { *AT91C_RSTC_RMR &= ~(AT91C_RSTC_URSTIEN| 1092b4: e51212f7 ldr r1, [r2, #-759] ; 0xfffffd09 1092b8: e3c1c801 bic ip, r1, #65536 ; 0x10000 1092bc: e3cc0010 bic r0, ip, #16 1092c0: e50202f7 str r0, [r2, #-759] ; 0xfffffd09 1092c4: eaffffa8 b 10916c DEBUGP("DBGU("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_DBGU]) { DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_DBGU](sr); } else { *AT91C_DBGU_IDR = *AT91C_DBGU_IMR; 1092c8: e5120def ldr r0, [r2, #-3567] ; 0xfffff211 1092cc: e5020df3 str r0, [r2, #-3571] ; 0xfffff20d 1092d0: eaffff86 b 1090f0 if (sr & AT91C_PITC_PITS) { if (sysirq_hdlrs[AT91SAM7_SYSIRQ_PIT]) { sysirq_hdlrs[AT91SAM7_SYSIRQ_PIT](sr); } else { DEBUGP("no handler DISABLE_PIT "); *AT91C_PITC_PIMR &= ~AT91C_PITC_PITIEN; 1092d4: e51202cf ldr r0, [r2, #-719] ; 0xfffffd31 1092d8: e3c0c402 bic ip, r0, #33554432 ; 0x2000000 1092dc: e502c2cf str ip, [r2, #-719] ; 0xfffffd31 1092e0: eaffff89 b 10910c DEBUGP("EFC("); if (sysirq_hdlrs[AT91SAM7_SYSIRQ_EFC]) { DEBUGP("handler "); sysirq_hdlrs[AT91SAM7_SYSIRQ_EFC](sr); } else { *AT91C_MC_FMR &= ~(AT91C_MC_LOCKE | 1092e4: e3e03000 mvn r3, #0 1092e8: e513c09f ldr ip, [r3, #-159] ; 0xffffff61 1092ec: e3cc000c bic r0, ip, #12 1092f0: e503009f str r0, [r3, #-159] ; 0xffffff61 1092f4: eaffffac b 1091ac 1092f8: 00010010 .word 0x00010010 1092fc: 0020390c .word 0x0020390c 00109300 : DEBUGPCR("END"); } void sysirq_register(enum sysirqs irq, sysirq_hdlr *hdlr) { if (irq >= AT91SAM7_SYSIRQ_COUNT) 109300: e3500006 cmp r0, #6 return; sysirq_hdlrs[irq] = hdlr; 109304: 959f3004 ldrls r3, [pc, #4] ; 109310 109308: 97831100 strls r1, [r3, r0, lsl #2] 10930c: e12fff1e bx lr 109310: 0020390c .word 0x0020390c 00109314 : } void sysirq_init(void) { 109314: e52de004 push {lr} ; (str lr, [sp, #-4]!) AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS, 109318: e59fc030 ldr ip, [pc, #48] ; 109350 sysirq_hdlrs[irq] = hdlr; } void sysirq_init(void) { 10931c: e24dd00c sub sp, sp, #12 AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS, 109320: e3a02005 mov r2, #5 109324: e3a03000 mov r3, #0 109328: e59f0024 ldr r0, [pc, #36] ; 109354 10932c: e3a01001 mov r1, #1 109330: e58dc000 str ip, [sp] 109334: ebffec94 bl 10458c static inline void AT91F_AIC_EnableIt ( AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { //* Enable the interrupt on the interrupt controller pAic->AIC_IECR = 0x1 << irq_id ; 109338: e3a02002 mov r2, #2 10933c: e3e03c0f mvn r3, #3840 ; 0xf00 109340: e5832021 str r2, [r3, #33] ; 0x21 OPENPCD_IRQ_PRIO_SYS, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &sys_irq); AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); } 109344: e28dd00c add sp, sp, #12 109348: e49de004 pop {lr} ; (ldr lr, [sp], #4) 10934c: e12fff1e bx lr 109350: 001090cc .word 0x001090cc 109354: fffff000 .word 0xfffff000 00109358 : AT91C_MC_CORRECT_KEY | (page << 8)); } void flash_page(u_int8_t *addr) { u_int16_t page = page_from_ramaddr(addr) & 0x3ff; 109358: e1a02700 lsl r2, r0, #14 AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK | AT91C_MC_CORRECT_KEY | (page << 8)); } void flash_page(u_int8_t *addr) { 10935c: e1a01000 mov r1, r0 u_int16_t page = page_from_ramaddr(addr) & 0x3ff; 109360: e1a00b22 lsr r0, r2, #22 AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK | AT91C_MC_CORRECT_KEY | (page << 8)); } void flash_page(u_int8_t *addr) { 109364: e92d40f8 push {r3, r4, r5, r6, r7, lr} u_int16_t page = page_from_ramaddr(addr) & 0x3ff; 109368: e1a05800 lsl r5, r0, #16 10936c: e1a06825 lsr r6, r5, #16 //* \brief Return MC EFC Status //*---------------------------------------------------------------------------- static inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC) // pointer to a MC controller { return pMC->MC_FSR; 109370: e3e04000 mvn r4, #0 u_int32_t fsr = AT91F_MC_EFC_GetStatus(AT91C_BASE_MC); DEBUGP("flash_page(0x%x=%u) ", addr, page); 109374: e59f006c ldr r0, [pc, #108] ; 1093e8 109378: e1a02006 mov r2, r6 10937c: e5147097 ldr r7, [r4, #-151] ; 0xffffff69 109380: ebfffaa5 bl 107e1c static int is_page_locked(u_int16_t page) { u_int16_t lockregion = LOCKREGION_FROM_PAGE(page); return (AT91C_BASE_MC->MC_FSR & (lockregion << 16)); 109384: e5143097 ldr r3, [r4, #-151] ; 0xffffff69 109388: e1a05a25 lsr r5, r5, #20 { u_int16_t page = page_from_ramaddr(addr) & 0x3ff; u_int32_t fsr = AT91F_MC_EFC_GetStatus(AT91C_BASE_MC); DEBUGP("flash_page(0x%x=%u) ", addr, page); if (is_page_locked(page)) { 10938c: e0135805 ands r5, r3, r5, lsl #16 109390: 1a00000d bne 1093cc DEBUGP("unlocking "); unlock_page(page); } if (!(fsr & AT91C_MC_FRDY)) { 109394: e3170001 tst r7, #1 109398: 0a000008 beq 1093c0 DEBUGP("NOT_FLASHING "); return; } DEBUGP("performing start_prog "); 10939c: e59f0048 ldr r0, [pc, #72] ; 1093ec 1093a0: ebfffa9d bl 107e1c AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_START_PROG | AT91C_MC_CORRECT_KEY | (page << 8)); 1093a4: e1a02406 lsl r2, r6, #8 return; } DEBUGP("performing start_prog "); AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_START_PROG | 1093a8: e382645a orr r6, r2, #1509949440 ; 0x5a000000 1093ac: e3866001 orr r6, r6, #1 //*---------------------------------------------------------------------------- static inline void AT91F_MC_EFC_PerformCmd ( AT91PS_MC pMC, // pointer to a MC controller unsigned int transfer_cmd) { pMC->MC_FCR = transfer_cmd; 1093b0: e3e00000 mvn r0, #0 1093b4: e500609b str r6, [r0, #-155] ; 0xffffff65 AT91C_MC_CORRECT_KEY | (page << 8)); } 1093b8: e8bd40f8 pop {r3, r4, r5, r6, r7, lr} 1093bc: e12fff1e bx lr DEBUGP("unlocking "); unlock_page(page); } if (!(fsr & AT91C_MC_FRDY)) { DEBUGP("NOT_FLASHING "); 1093c0: e59f0028 ldr r0, [pc, #40] ; 1093f0 1093c4: ebfffa94 bl 107e1c return; 1093c8: eafffffa b 1093b8 u_int16_t page = page_from_ramaddr(addr) & 0x3ff; u_int32_t fsr = AT91F_MC_EFC_GetStatus(AT91C_BASE_MC); DEBUGP("flash_page(0x%x=%u) ", addr, page); if (is_page_locked(page)) { DEBUGP("unlocking "); 1093cc: e59f0020 ldr r0, [pc, #32] ; 1093f4 1093d0: ebfffa91 bl 107e1c static void unlock_page(u_int16_t page) { page &= 0x3ff; AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK | AT91C_MC_CORRECT_KEY | (page << 8)); 1093d4: e1a03406 lsl r3, r6, #8 } static void unlock_page(u_int16_t page) { page &= 0x3ff; AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK | 1093d8: e383c45a orr ip, r3, #1509949440 ; 0x5a000000 1093dc: e38c1004 orr r1, ip, #4 1093e0: e504109b str r1, [r4, #-155] ; 0xffffff65 1093e4: eaffffea b 109394 1093e8: 0010adcc .word 0x0010adcc 1093ec: 0010ae00 .word 0x0010ae00 1093f0: 0010adf0 .word 0x0010adf0 1093f4: 0010ade4 .word 0x0010ade4 001093f8 : static inline void AT91F_MC_EFC_CfgModeReg ( AT91PS_MC pMC, // pointer to a MC controller unsigned int mode) // mode register { // Write to the FMR register pMC->MC_FMR = mode; 1093f8: e59f2008 ldr r2, [pc, #8] ; 109408 1093fc: e3e03000 mvn r3, #0 109400: e503209f str r2, [r3, #-159] ; 0xffffff61 { unsigned int fmcn = AT91F_MC_EFC_ComputeFMCN(MCK); AT91F_MC_EFC_CfgModeReg(AT91C_BASE_MC, (fmcn&0xff) << 16 | AT91C_MC_FWS_3FWS); } 109404: e12fff1e bx lr 109408: 00310300 .word 0x00310300 0010940c : static const AT91PS_SPI pSPI = AT91C_BASE_SPI; /* SPI irq handler */ static void spi_irq(void) { u_int32_t status = pSPI->SPI_SR; 10940c: e59f002c ldr r0, [pc, #44] ; 109440 109410: e510c0ef ldr ip, [r0, #-239] ; 0xffffff11 if (status & AT91C_SPI_OVRES) DEBUGPSPIIRQ("Overrun "); if (status & AT91C_SPI_MODF) DEBUGPSPIIRQ("ModeFault "); if (status & AT91C_SPI_ENDRX) { 109414: e31c0010 tst ip, #16 pSPI->SPI_IDR = AT91C_SPI_ENDRX; 109418: 13a01010 movne r1, #16 10941c: 150010e7 strne r1, [r0, #-231] ; 0xffffff19 DEBUGPSPIIRQ("ENDRX "); } if (status & AT91C_SPI_ENDTX) { 109420: e31c0020 tst ip, #32 pSPI->SPI_IDR = AT91C_SPI_ENDTX; 109424: 159fc014 ldrne ip, [pc, #20] ; 109440 109428: 13a00020 movne r0, #32 static inline void AT91F_AIC_ClearIt ( AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id) // \arg interrupt number to initialize { //* Clear the interrupt on the Interrupt Controller ( if one is pending ) pAic->AIC_ICCR = (0x1 << irq_id); 10942c: e3a02020 mov r2, #32 109430: e3e03c0f mvn r3, #3840 ; 0xf00 109434: 150c00e7 strne r0, [ip, #-231] ; 0xffffff19 109438: e5832029 str r2, [r3, #41] ; 0x29 } DEBUGPSPIIRQ("\r\n"); AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_SPI); } 10943c: e12fff1e bx lr 109440: fffe00ff .word 0xfffe00ff 00109444 : #ifdef SPI_USES_DMA static int spi_transceive(const u_int8_t *tx_data, u_int16_t tx_len, 109444: e92d40f0 push {r4, r5, r6, r7, lr} u_int8_t *rx_data, u_int16_t *rx_len) { DEBUGPSPI("DMA Xfer tx=%s\r\n", hexdump(tx_data, tx_len)); if (*rx_len < tx_len) { 109448: e1d230b0 ldrh r3, [r2] 10944c: e1530001 cmp r3, r1 AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_SPI); } #ifdef SPI_USES_DMA static int spi_transceive(const u_int8_t *tx_data, u_int16_t tx_len, 109450: e1a07000 mov r7, r0 109454: e24dd00c sub sp, sp, #12 109458: e1a05002 mov r5, r2 10945c: e1a04001 mov r4, r1 u_int8_t *rx_data, u_int16_t *rx_len) { DEBUGPSPI("DMA Xfer tx=%s\r\n", hexdump(tx_data, tx_len)); if (*rx_len < tx_len) { DEBUGPCRF("rx_len=%u smaller tx_len=%u\n", *rx_len, tx_len); return -1; 109460: 33e00000 mvncc r0, #0 #ifdef SPI_USES_DMA static int spi_transceive(const u_int8_t *tx_data, u_int16_t tx_len, u_int8_t *rx_data, u_int16_t *rx_len) { DEBUGPSPI("DMA Xfer tx=%s\r\n", hexdump(tx_data, tx_len)); if (*rx_len < tx_len) { 109464: 2a000002 bcs 109474 DEBUGPSPI("DMA Xfer finished rx=%s\r\n", hexdump(rx_data, tx_len)); *rx_len = tx_len; return 0; } 109468: e28dd00c add sp, sp, #12 10946c: e8bd40f0 pop {r4, r5, r6, r7, lr} 109470: e12fff1e bx lr AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { unsigned int mask = 0x1 << irq_id; //* Disable the interrupt on the interrupt controller pAic->AIC_IDCR = mask ; 109474: e3e0cc0f mvn ip, #3840 ; 0xf00 unsigned char *pBuffer, unsigned int szBuffer, unsigned char *pNextBuffer, unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( 109478: e3a06000 mov r6, #0 AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { unsigned int mask = 0x1 << irq_id; //* Disable the interrupt on the interrupt controller pAic->AIC_IDCR = mask ; 10947c: e3a0e102 mov lr, #-2147483648 ; 0x80000000 109480: e58ce025 str lr, [ip, #37] ; 0x25 unsigned char *pBuffer, unsigned int szBuffer, unsigned char *pNextBuffer, unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( 109484: e59f1070 ldr r1, [pc, #112] ; 1094fc { unsigned int mask = 0x1 << irq_id; //* Disable the interrupt on the interrupt controller pAic->AIC_IDCR = mask ; //* Clear the interrupt on the Interrupt Controller ( if one is pending ) pAic->AIC_ICCR = mask ; 109488: e58ce029 str lr, [ip, #41] ; 0x29 unsigned char *pBuffer, unsigned int szBuffer, unsigned char *pNextBuffer, unsigned int szNextBuffer ) { return AT91F_PDC_ReceiveFrame( 10948c: e1a02004 mov r2, r4 109490: e1a03006 mov r3, r6 109494: e59f0064 ldr r0, [pc, #100] ; 109500 109498: e58d6000 str r6, [sp] 10949c: ebffecb9 bl 104788 const unsigned char *pBuffer, unsigned int szBuffer, const unsigned char *pNextBuffer, unsigned int szNextBuffer ) { return AT91F_PDC_SendFrame( 1094a0: e1a01007 mov r1, r7 1094a4: e1a02004 mov r2, r4 1094a8: e1a03006 mov r3, r6 1094ac: e59f004c ldr r0, [pc, #76] ; 109500 1094b0: e58d6000 str r6, [sp] 1094b4: ebffeca0 bl 10473c //* \brief Enable receive //*---------------------------------------------------------------------------- static inline void AT91F_PDC_EnableRx ( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller { pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 1094b8: e59fc044 ldr ip, [pc, #68] ; 109504 AT91F_SPI_SendFrame(pSPI, tx_data, tx_len, NULL, 0); AT91F_PDC_EnableRx(AT91C_BASE_PDC_SPI); AT91F_PDC_EnableTx(AT91C_BASE_PDC_SPI); pSPI->SPI_IER = AT91C_SPI_ENDTX|AT91C_SPI_ENDRX; 1094bc: e59f2044 ldr r2, [pc, #68] ; 109508 1094c0: e3a03001 mov r3, #1 //* \brief Enable transmit //*---------------------------------------------------------------------------- static inline void AT91F_PDC_EnableTx ( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller { pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 1094c4: e3a01c01 mov r1, #256 ; 0x100 1094c8: e3a00030 mov r0, #48 ; 0x30 //* \brief Enable receive //*---------------------------------------------------------------------------- static inline void AT91F_PDC_EnableRx ( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller { pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 1094cc: e50c30df str r3, [ip, #-223] ; 0xffffff21 //* \brief Enable transmit //*---------------------------------------------------------------------------- static inline void AT91F_PDC_EnableTx ( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller { pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 1094d0: e50c10df str r1, [ip, #-223] ; 0xffffff21 1094d4: e50200eb str r0, [r2, #-235] ; 0xffffff15 while (! (pSPI->SPI_SR & AT91C_SPI_ENDRX)) ; 1094d8: e51200ef ldr r0, [r2, #-239] ; 0xffffff11 1094dc: e3100010 tst r0, #16 1094e0: 0afffffc beq 1094d8 static inline void AT91F_AIC_EnableIt ( AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { //* Enable the interrupt on the interrupt controller pAic->AIC_IECR = 0x1 << irq_id ; 1094e4: e3a02102 mov r2, #-2147483648 ; 0x80000000 1094e8: e3e01c0f mvn r1, #3840 ; 0xf00 1094ec: e5812021 str r2, [r1, #33] ; 0x21 DEBUGPSPI("DMA Xfer finished rx=%s\r\n", hexdump(rx_data, tx_len)); *rx_len = tx_len; return 0; 1094f0: e3a00000 mov r0, #0 /* Re-enable RC632 interrupts */ AT91F_AIC_EnableIt(AT91C_BASE_AIC, OPENPCD_IRQ_RC632); DEBUGPSPI("DMA Xfer finished rx=%s\r\n", hexdump(rx_data, tx_len)); *rx_len = tx_len; 1094f4: e1c540b0 strh r4, [r5] 1094f8: eaffffda b 109468 1094fc: 00203928 .word 0x00203928 109500: fffe0100 .word 0xfffe0100 109504: fffe01ff .word 0xfffe01ff 109508: fffe00ff .word 0xfffe00ff 0010950c : /* RC632 access primitives */ int opcd_rc632_reg_write(struct rfid_asic_handle *hdl, u_int8_t addr, u_int8_t data) { 10950c: e92d4010 push {r4, lr} 109510: e24dd008 sub sp, sp, #8 u_int16_t rx_len = 2; 109514: e3a0e002 mov lr, #2 109518: e28dc008 add ip, sp, #8 DEBUG632("[0x%02x] <= 0x%02x", addr, data); addr = RC632_WRITE_ADDR(addr); spi_outbuf[0] = addr; 10951c: e59f302c ldr r3, [pc, #44] ; 109550 /* RC632 access primitives */ int opcd_rc632_reg_write(struct rfid_asic_handle *hdl, u_int8_t addr, u_int8_t data) { u_int16_t rx_len = 2; 109520: e16ce0b2 strh lr, [ip, #-2]! DEBUG632("[0x%02x] <= 0x%02x", addr, data); addr = RC632_WRITE_ADDR(addr); 109524: e1a01081 lsl r1, r1, #1 109528: e201407e and r4, r1, #126 ; 0x7e spi_outbuf[0] = addr; spi_outbuf[1] = data; 10952c: e5c32045 strb r2, [r3, #69] ; 0x45 return spi_transceive(spi_outbuf, 2, spi_inbuf, &rx_len); 109530: e2830044 add r0, r3, #68 ; 0x44 109534: e1a0100e mov r1, lr 109538: e1a0200c mov r2, ip DEBUG632("[0x%02x] <= 0x%02x", addr, data); addr = RC632_WRITE_ADDR(addr); spi_outbuf[0] = addr; 10953c: e5c34044 strb r4, [r3, #68] ; 0x44 spi_outbuf[1] = data; return spi_transceive(spi_outbuf, 2, spi_inbuf, &rx_len); 109540: ebffffbf bl 109444 } 109544: e28dd008 add sp, sp, #8 109548: e8bd4010 pop {r4, lr} 10954c: e12fff1e bx lr 109550: 00203928 .word 0x00203928 00109554 : #define RC632_REGSET_MAXSIZE (RC632_REGSET_END-RC632_REGSET_START) static u_int8_t regset_buf[RC632_REGSET_MAXSIZE * 2]; int opcd_rc632_reg_write_set(struct rfid_asic_handle *hdl, u_int8_t *regs, int len) { 109554: e92d4010 push {r4, lr} u_int8_t i, j = 0; u_int16_t rx_len; if (len > RC632_REGSET_MAXSIZE) 109558: e352002f cmp r2, #47 ; 0x2f #define RC632_REGSET_MAXSIZE (RC632_REGSET_END-RC632_REGSET_START) static u_int8_t regset_buf[RC632_REGSET_MAXSIZE * 2]; int opcd_rc632_reg_write_set(struct rfid_asic_handle *hdl, u_int8_t *regs, int len) { 10955c: e24dd008 sub sp, sp, #8 u_int8_t i, j = 0; u_int16_t rx_len; if (len > RC632_REGSET_MAXSIZE) return -E2BIG; 109560: c3e00006 mvngt r0, #6 u_int8_t *regs, int len) { u_int8_t i, j = 0; u_int16_t rx_len; if (len > RC632_REGSET_MAXSIZE) 109564: ca00001d bgt 1095e0 109568: e3a00000 mov r0, #0 10956c: e1a0c001 mov ip, r1 109570: e3a03010 mov r3, #16 109574: e1a01000 mov r1, r0 for (i = RC632_REGSET_START; i <= RC632_REGSET_END; i++) { /* skip bank registers */ if (i % 8 == 0) continue; regset_buf[j++] = RC632_WRITE_ADDR(i); 109578: e59fe06c ldr lr, [pc, #108] ; 1095ec 10957c: ea00000f b 1095c0 if (len > RC632_REGSET_MAXSIZE) return -E2BIG; for (i = RC632_REGSET_START; i <= RC632_REGSET_END; i++) { /* skip bank registers */ if (i % 8 == 0) 109580: e3120007 tst r2, #7 109584: 0a00000b beq 1095b8 #define RC632_REGSET_START 0x10 #define RC632_REGSET_END 0x3f #define RC632_REGSET_MAXSIZE (RC632_REGSET_END-RC632_REGSET_START) static u_int8_t regset_buf[RC632_REGSET_MAXSIZE * 2]; int opcd_rc632_reg_write_set(struct rfid_asic_handle *hdl, 109588: e2802011 add r2, r0, #17 for (i = RC632_REGSET_START; i <= RC632_REGSET_END; i++) { /* skip bank registers */ if (i % 8 == 0) continue; regset_buf[j++] = RC632_WRITE_ADDR(i); 10958c: e1a04082 lsl r4, r2, #1 109590: e204407e and r4, r4, #126 ; 0x7e 109594: e08e2001 add r2, lr, r1 109598: e5c24088 strb r4, [r2, #136] ; 0x88 10959c: e2814001 add r4, r1, #1 1095a0: e20410ff and r1, r4, #255 ; 0xff regset_buf[j++] = regs[i - RC632_REGSET_START]; 1095a4: e5dc4001 ldrb r4, [ip, #1] 1095a8: e08e2001 add r2, lr, r1 1095ac: e5c24088 strb r4, [r2, #136] ; 0x88 1095b0: e2811001 add r1, r1, #1 1095b4: e20110ff and r1, r1, #255 ; 0xff 1095b8: e2800001 add r0, r0, #1 1095bc: e28cc001 add ip, ip, #1 u_int16_t rx_len; if (len > RC632_REGSET_MAXSIZE) return -E2BIG; for (i = RC632_REGSET_START; i <= RC632_REGSET_END; i++) { 1095c0: e2832001 add r2, r3, #1 1095c4: e20230ff and r3, r2, #255 ; 0xff 1095c8: e3530040 cmp r3, #64 ; 0x40 1095cc: 1affffeb bne 109580 continue; regset_buf[j++] = RC632_WRITE_ADDR(i); regset_buf[j++] = regs[i - RC632_REGSET_START]; } rx_len = j; 1095d0: e28d2008 add r2, sp, #8 1095d4: e16210b2 strh r1, [r2, #-2]! return spi_transceive(regset_buf, j, spi_inbuf, &rx_len); 1095d8: e59f0010 ldr r0, [pc, #16] ; 1095f0 1095dc: ebffff98 bl 109444 } 1095e0: e28dd008 add sp, sp, #8 1095e4: e8bd4010 pop {r4, lr} 1095e8: e12fff1e bx lr 1095ec: 00203928 .word 0x00203928 1095f0: 002039b0 .word 0x002039b0 001095f4 : int opcd_rc632_fifo_write(struct rfid_asic_handle *hdl, u_int8_t len, u_int8_t *data, u_int8_t flags) { 1095f4: e92d4070 push {r4, r5, r6, lr} u_int16_t rx_len = sizeof(spi_inbuf); if (len > sizeof(spi_outbuf)-1) len = sizeof(spi_outbuf)-1; spi_outbuf[0] = FIFO_ADDR; 1095f8: e59f0050 ldr r0, [pc, #80] ; 109650 return spi_transceive(regset_buf, j, spi_inbuf, &rx_len); } int opcd_rc632_fifo_write(struct rfid_asic_handle *hdl, u_int8_t len, u_int8_t *data, u_int8_t flags) { 1095fc: e24dd008 sub sp, sp, #8 u_int16_t rx_len = sizeof(spi_inbuf); 109600: e3510040 cmp r1, #64 ; 0x40 109604: 31a06001 movcc r6, r1 109608: 23a06040 movcs r6, #64 ; 0x40 if (len > sizeof(spi_outbuf)-1) len = sizeof(spi_outbuf)-1; spi_outbuf[0] = FIFO_ADDR; 10960c: e1a05000 mov r5, r0 } int opcd_rc632_fifo_write(struct rfid_asic_handle *hdl, u_int8_t len, u_int8_t *data, u_int8_t flags) { u_int16_t rx_len = sizeof(spi_inbuf); 109610: e28d4008 add r4, sp, #8 if (len > sizeof(spi_outbuf)-1) len = sizeof(spi_outbuf)-1; spi_outbuf[0] = FIFO_ADDR; memcpy(&spi_outbuf[1], data, len); 109614: e1a01002 mov r1, r2 { u_int16_t rx_len = sizeof(spi_inbuf); if (len > sizeof(spi_outbuf)-1) len = sizeof(spi_outbuf)-1; spi_outbuf[0] = FIFO_ADDR; 109618: e3a03004 mov r3, #4 } int opcd_rc632_fifo_write(struct rfid_asic_handle *hdl, u_int8_t len, u_int8_t *data, u_int8_t flags) { u_int16_t rx_len = sizeof(spi_inbuf); 10961c: e3a02041 mov r2, #65 ; 0x41 109620: e16420b2 strh r2, [r4, #-2]! if (len > sizeof(spi_outbuf)-1) len = sizeof(spi_outbuf)-1; spi_outbuf[0] = FIFO_ADDR; 109624: e5e53044 strb r3, [r5, #68]! ; 0x44 memcpy(&spi_outbuf[1], data, len); 109628: e1a02006 mov r2, r6 10962c: e2800045 add r0, r0, #69 ; 0x45 109630: eb0002b5 bl 10a10c DEBUG632("[FIFO] <= %s", hexdump(data, len)); return spi_transceive(spi_outbuf, len+1, spi_inbuf, &rx_len); 109634: e1a00005 mov r0, r5 109638: e2861001 add r1, r6, #1 10963c: e1a02004 mov r2, r4 109640: ebffff7f bl 109444 } 109644: e28dd008 add sp, sp, #8 109648: e8bd4070 pop {r4, r5, r6, lr} 10964c: e12fff1e bx lr 109650: 00203928 .word 0x00203928 00109654 : int opcd_rc632_reg_read(struct rfid_asic_handle *hdl, u_int8_t addr, u_int8_t *val) { 109654: e92d4070 push {r4, r5, r6, lr} 109658: e24dd008 sub sp, sp, #8 u_int16_t rx_len = 2; 10965c: e3a0e002 mov lr, #2 109660: e28dc008 add ip, sp, #8 addr = (addr << 1) & 0x7e; 109664: e1a05081 lsl r5, r1, #1 spi_outbuf[0] = addr | 0x80; 109668: e59f4044 ldr r4, [pc, #68] ; 1096b4 } int opcd_rc632_reg_read(struct rfid_asic_handle *hdl, u_int8_t addr, u_int8_t *val) { u_int16_t rx_len = 2; 10966c: e16ce0b2 strh lr, [ip, #-2]! addr = (addr << 1) & 0x7e; 109670: e205107e and r1, r5, #126 ; 0x7e spi_outbuf[0] = addr | 0x80; 109674: e1e00c81 mvn r0, r1, lsl #25 109678: e1e03ca0 mvn r3, r0, lsr #25 return spi_transceive(spi_outbuf, len+1, spi_inbuf, &rx_len); } int opcd_rc632_reg_read(struct rfid_asic_handle *hdl, u_int8_t addr, u_int8_t *val) { 10967c: e1a06002 mov r6, r2 u_int16_t rx_len = 2; addr = (addr << 1) & 0x7e; spi_outbuf[0] = addr | 0x80; spi_outbuf[1] = 0x00; 109680: e3a05000 mov r5, #0 spi_transceive(spi_outbuf, 2, spi_inbuf, &rx_len); 109684: e2840044 add r0, r4, #68 ; 0x44 109688: e1a0100e mov r1, lr 10968c: e1a0200c mov r2, ip { u_int16_t rx_len = 2; addr = (addr << 1) & 0x7e; spi_outbuf[0] = addr | 0x80; 109690: e5c43044 strb r3, [r4, #68] ; 0x44 spi_outbuf[1] = 0x00; 109694: e5c45045 strb r5, [r4, #69] ; 0x45 spi_transceive(spi_outbuf, 2, spi_inbuf, &rx_len); 109698: ebffff69 bl 109444 *val = spi_inbuf[1]; 10969c: e5d43001 ldrb r3, [r4, #1] DEBUG632("[0x%02x] => 0x%02x", addr>>1, *val); return 0; } 1096a0: e1a00005 mov r0, r5 spi_outbuf[0] = addr | 0x80; spi_outbuf[1] = 0x00; spi_transceive(spi_outbuf, 2, spi_inbuf, &rx_len); *val = spi_inbuf[1]; 1096a4: e5c63000 strb r3, [r6] DEBUG632("[0x%02x] => 0x%02x", addr>>1, *val); return 0; } 1096a8: e28dd008 add sp, sp, #8 1096ac: e8bd4070 pop {r4, r5, r6, lr} 1096b0: e12fff1e bx lr 1096b4: 00203928 .word 0x00203928 001096b8 : } /* RC632 interrupt handling */ static void rc632_irq(void) { 1096b8: e52de004 push {lr} ; (str lr, [sp, #-4]!) struct req_ctx *irq_rctx; struct openpcd_hdr *irq_opcdh; u_int8_t cause; /* CL RC632 has interrupted us */ opcd_rc632_reg_read(NULL, RC632_REG_INTERRUPT_RQ, &cause); 1096bc: e3a01007 mov r1, #7 } /* RC632 interrupt handling */ static void rc632_irq(void) { 1096c0: e24dd00c sub sp, sp, #12 struct req_ctx *irq_rctx; struct openpcd_hdr *irq_opcdh; u_int8_t cause; /* CL RC632 has interrupted us */ opcd_rc632_reg_read(NULL, RC632_REG_INTERRUPT_RQ, &cause); 1096c4: e08d2001 add r2, sp, r1 1096c8: e3a00000 mov r0, #0 1096cc: ebffffe0 bl 109654 /* ACK all interrupts */ //rc632_reg_write(NULL, RC632_REG_INTERRUPT_RQ, cause); opcd_rc632_reg_write(NULL, RC632_REG_INTERRUPT_RQ, RC632_INT_TIMER); 1096d0: e3a01007 mov r1, #7 1096d4: e3a02020 mov r2, #32 1096d8: e3a00000 mov r0, #0 1096dc: ebffff8a bl 10950c DEBUGP("RxComplete "); if (cause & RC632_INT_TX) DEBUGP("TxComplete "); irq_rctx = req_ctx_find_get(0, RCTX_STATE_FREE, 1096e0: e59f3064 ldr r3, [pc, #100] ; 10974c 1096e4: e3a00000 mov r0, #0 1096e8: e3a010fe mov r1, #254 ; 0xfe 1096ec: e3a02004 mov r2, #4 1096f0: e1a0e00f mov lr, pc 1096f4: e12fff13 bx r3 RCTX_STATE_RC632IRQ_BUSY); if (!irq_rctx) { 1096f8: e2503000 subs r3, r0, #0 1096fc: 0a00000d beq 109738 /* disable rc632 interrupt until RCTX is free */ AT91F_AIC_DisableIt(AT91C_BASE_AIC, OPENPCD_IRQ_RC632); return; } irq_opcdh = (struct openpcd_hdr *) irq_rctx->data; 109700: e593e008 ldr lr, [r3, #8] /* initialize static part of openpcd_hdr for USB IRQ reporting */ irq_opcdh->cmd = OPENPCD_CMD_IRQ; irq_opcdh->flags = 0x00; irq_opcdh->reg = 0x07; 109704: e3a01007 mov r1, #7 } irq_opcdh = (struct openpcd_hdr *) irq_rctx->data; /* initialize static part of openpcd_hdr for USB IRQ reporting */ irq_opcdh->cmd = OPENPCD_CMD_IRQ; 109708: e3a0201a mov r2, #26 irq_opcdh->flags = 0x00; 10970c: e3a03000 mov r3, #0 irq_opcdh->reg = 0x07; 109710: e5ce1002 strb r1, [lr, #2] } irq_opcdh = (struct openpcd_hdr *) irq_rctx->data; /* initialize static part of openpcd_hdr for USB IRQ reporting */ irq_opcdh->cmd = OPENPCD_CMD_IRQ; 109714: e5ce2000 strb r2, [lr] irq_opcdh->flags = 0x00; 109718: e5ce3001 strb r3, [lr, #1] irq_opcdh->reg = 0x07; irq_opcdh->val = cause; 10971c: e5ddc007 ldrb ip, [sp, #7] req_ctx_set_state(irq_rctx, RCTX_STATE_UDP_EP3_PENDING); 109720: e3a01012 mov r1, #18 /* initialize static part of openpcd_hdr for USB IRQ reporting */ irq_opcdh->cmd = OPENPCD_CMD_IRQ; irq_opcdh->flags = 0x00; irq_opcdh->reg = 0x07; irq_opcdh->val = cause; 109724: e5cec003 strb ip, [lr, #3] req_ctx_set_state(irq_rctx, RCTX_STATE_UDP_EP3_PENDING); 109728: ebfffa11 bl 107f74 DEBUGPCR(""); } 10972c: e28dd00c add sp, sp, #12 109730: e49de004 pop {lr} ; (ldr lr, [sp], #4) 109734: e12fff1e bx lr AT91PS_AIC pAic, // \arg pointer to the AIC registers unsigned int irq_id ) // \arg interrupt number to initialize { unsigned int mask = 0x1 << irq_id; //* Disable the interrupt on the interrupt controller pAic->AIC_IDCR = mask ; 109738: e3e00c0f mvn r0, #3840 ; 0xf00 10973c: e3a02102 mov r2, #-2147483648 ; 0x80000000 109740: e5802025 str r2, [r0, #37] ; 0x25 //* Clear the interrupt on the Interrupt Controller ( if one is pending ) pAic->AIC_ICCR = mask ; 109744: e5802029 str r2, [r0, #41] ; 0x29 RCTX_STATE_RC632IRQ_BUSY); if (!irq_rctx) { DEBUGPCRF("NO RCTX!"); /* disable rc632 interrupt until RCTX is free */ AT91F_AIC_DisableIt(AT91C_BASE_AIC, OPENPCD_IRQ_RC632); return; 109748: eafffff7 b 10972c 10974c: 00200080 .word 0x00200080 00109750 : AT91F_SPI_Disable(pSPI); } #endif #ifdef DEBUG static int rc632_reg_write_verify(struct rfid_asic_handle *hdl, 109750: e92d4030 push {r4, r5, lr} u_int8_t reg, u_int8_t val) { u_int8_t tmp; opcd_rc632_reg_write(hdl, reg, val); 109754: e1a02001 mov r2, r1 AT91F_SPI_Disable(pSPI); } #endif #ifdef DEBUG static int rc632_reg_write_verify(struct rfid_asic_handle *hdl, 109758: e24dd00c sub sp, sp, #12 10975c: e1a04001 mov r4, r1 109760: e1a05000 mov r5, r0 u_int8_t reg, u_int8_t val) { u_int8_t tmp; opcd_rc632_reg_write(hdl, reg, val); 109764: e3a01021 mov r1, #33 ; 0x21 109768: ebffff67 bl 10950c opcd_rc632_reg_read(hdl, reg, &tmp); 10976c: e1a00005 mov r0, r5 109770: e3a01021 mov r1, #33 ; 0x21 109774: e28d2007 add r2, sp, #7 109778: ebffffb5 bl 109654 DEBUGPCRF("reg=0x%02x, write=0x%02x, read=0x%02x ", reg, val, tmp); return (val == tmp); 10977c: e5dd1007 ldrb r1, [sp, #7] } 109780: e0643001 rsb r3, r4, r1 109784: e2730000 rsbs r0, r3, #0 109788: e0a00003 adc r0, r0, r3 10978c: e28dd00c add sp, sp, #12 109790: e8bd4030 pop {r4, r5, lr} 109794: e12fff1e bx lr 00109798 : return 0; } int opcd_rc632_fifo_read(struct rfid_asic_handle *hdl, u_int8_t max_len, u_int8_t *data) { 109798: e92d4070 push {r4, r5, r6, lr} 10979c: e24dd008 sub sp, sp, #8 1097a0: e1a04001 mov r4, r1 1097a4: e1a06002 mov r6, r2 int ret; u_int8_t fifo_length; u_int8_t i; u_int16_t rx_len; ret = opcd_rc632_reg_read(hdl, RC632_REG_FIFO_LENGTH, &fifo_length); 1097a8: e3a01004 mov r1, #4 1097ac: e28d2007 add r2, sp, #7 1097b0: ebffffa7 bl 109654 if (ret < 0) 1097b4: e2505000 subs r5, r0, #0 1097b8: ba00002e blt 109878 return ret; rx_len = fifo_length+1; 1097bc: e5ddc007 ldrb ip, [sp, #7] if (max_len < fifo_length) 1097c0: e15c0004 cmp ip, r4 ret = opcd_rc632_reg_read(hdl, RC632_REG_FIFO_LENGTH, &fifo_length); if (ret < 0) return ret; rx_len = fifo_length+1; 1097c4: e28c1001 add r1, ip, #1 if (max_len < fifo_length) fifo_length = max_len; 1097c8: 81a0c004 movhi ip, r4 ret = opcd_rc632_reg_read(hdl, RC632_REG_FIFO_LENGTH, &fifo_length); if (ret < 0) return ret; rx_len = fifo_length+1; 1097cc: e1cd10b4 strh r1, [sp, #4] if (max_len < fifo_length) fifo_length = max_len; 1097d0: 85cd4007 strbhi r4, [sp, #7] 1097d4: 82841001 addhi r1, r4, #1 for (i = 0; i < fifo_length; i++) 1097d8: e35c0000 cmp ip, #0 1097dc: 0a000014 beq 109834 1097e0: e59fe0a0 ldr lr, [pc, #160] ; 109888 DEBUG632("[0x%02x] => 0x%02x", addr>>1, *val); return 0; } int opcd_rc632_fifo_read(struct rfid_asic_handle *hdl, 1097e4: e24c0001 sub r0, ip, #1 1097e8: e20020ff and r2, r0, #255 ; 0xff 1097ec: e1a0300e mov r3, lr 1097f0: e082e00e add lr, r2, lr if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) spi_outbuf[i] = FIFO_ADDR; 1097f4: e3a00004 mov r0, #4 rx_len = fifo_length+1; if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) 1097f8: e153000e cmp r3, lr 1097fc: e2022001 and r2, r2, #1 spi_outbuf[i] = FIFO_ADDR; 109800: e5c30000 strb r0, [r3] rx_len = fifo_length+1; if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) 109804: 0a00000a beq 109834 109808: e3520000 cmp r2, #0 10980c: 0a000002 beq 10981c spi_outbuf[i] = FIFO_ADDR; 109810: e5e30001 strb r0, [r3, #1]! rx_len = fifo_length+1; if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) 109814: e153000e cmp r3, lr 109818: 0a000005 beq 109834 DEBUG632("[0x%02x] => 0x%02x", addr>>1, *val); return 0; } int opcd_rc632_fifo_read(struct rfid_asic_handle *hdl, 10981c: e2834001 add r4, r3, #1 if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) spi_outbuf[i] = FIFO_ADDR; 109820: e5c30001 strb r0, [r3, #1] DEBUG632("[0x%02x] => 0x%02x", addr>>1, *val); return 0; } int opcd_rc632_fifo_read(struct rfid_asic_handle *hdl, 109824: e2833002 add r3, r3, #2 rx_len = fifo_length+1; if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) 109828: e153000e cmp r3, lr spi_outbuf[i] = FIFO_ADDR; 10982c: e5c40001 strb r0, [r4, #1] rx_len = fifo_length+1; if (max_len < fifo_length) fifo_length = max_len; for (i = 0; i < fifo_length; i++) 109830: 1afffff9 bne 10981c spi_outbuf[i] = FIFO_ADDR; spi_outbuf[0] |= 0x80; 109834: e59f4050 ldr r4, [pc, #80] ; 10988c 109838: e5d40044 ldrb r0, [r4, #68] ; 0x44 10983c: e1e02c80 mvn r2, r0, lsl #25 109840: e1e0eca2 mvn lr, r2, lsr #25 spi_outbuf[fifo_length] = 0x00; 109844: e084c00c add ip, r4, ip 109848: e3a03000 mov r3, #0 spi_transceive(spi_outbuf, fifo_length+1, spi_inbuf, &rx_len); 10984c: e28d2004 add r2, sp, #4 fifo_length = max_len; for (i = 0; i < fifo_length; i++) spi_outbuf[i] = FIFO_ADDR; spi_outbuf[0] |= 0x80; 109850: e5c4e044 strb lr, [r4, #68] ; 0x44 spi_outbuf[fifo_length] = 0x00; spi_transceive(spi_outbuf, fifo_length+1, spi_inbuf, &rx_len); 109854: e2840044 add r0, r4, #68 ; 0x44 for (i = 0; i < fifo_length; i++) spi_outbuf[i] = FIFO_ADDR; spi_outbuf[0] |= 0x80; spi_outbuf[fifo_length] = 0x00; 109858: e5cc3044 strb r3, [ip, #68] ; 0x44 spi_transceive(spi_outbuf, fifo_length+1, spi_inbuf, &rx_len); 10985c: ebfffef8 bl 109444 memcpy(data, spi_inbuf+1, rx_len-1); 109860: e1dd50b4 ldrh r5, [sp, #4] 109864: e2455001 sub r5, r5, #1 109868: e1a00006 mov r0, r6 10986c: e2841001 add r1, r4, #1 109870: e1a02005 mov r2, r5 109874: eb000224 bl 10a10c DEBUG632("[FIFO] => %s", hexdump(data, rx_len-1)); return rx_len-1; } 109878: e1a00005 mov r0, r5 10987c: e28dd008 add sp, sp, #8 109880: e8bd4070 pop {r4, r5, r6, lr} 109884: e12fff1e bx lr 109888: 0020396c .word 0x0020396c 10988c: 00203928 .word 0x00203928 00109890 : int opcd_rc632_set_bits(struct rfid_asic_handle *hdl, u_int8_t reg, u_int8_t bits) { 109890: e92d4070 push {r4, r5, r6, lr} 109894: e24dd008 sub sp, sp, #8 109898: e1a06002 mov r6, r2 u_int8_t val; int ret; ret = opcd_rc632_reg_read(hdl, reg, &val); 10989c: e28d2007 add r2, sp, #7 return rx_len-1; } int opcd_rc632_set_bits(struct rfid_asic_handle *hdl, u_int8_t reg, u_int8_t bits) { 1098a0: e1a05000 mov r5, r0 1098a4: e1a04001 mov r4, r1 u_int8_t val; int ret; ret = opcd_rc632_reg_read(hdl, reg, &val); 1098a8: ebffff69 bl 109654 if (ret < 0) 1098ac: e3500000 cmp r0, #0 1098b0: ba000006 blt 1098d0 return ret; val |= bits; 1098b4: e5dd3007 ldrb r3, [sp, #7] 1098b8: e1866003 orr r6, r6, r3 return opcd_rc632_reg_write(hdl, reg, val); 1098bc: e1a00005 mov r0, r5 1098c0: e1a01004 mov r1, r4 1098c4: e1a02006 mov r2, r6 ret = opcd_rc632_reg_read(hdl, reg, &val); if (ret < 0) return ret; val |= bits; 1098c8: e5cd6007 strb r6, [sp, #7] return opcd_rc632_reg_write(hdl, reg, val); 1098cc: ebffff0e bl 10950c } 1098d0: e28dd008 add sp, sp, #8 1098d4: e8bd4070 pop {r4, r5, r6, lr} 1098d8: e12fff1e bx lr 001098dc : int opcd_rc632_clear_bits(struct rfid_asic_handle *hdl, u_int8_t reg, u_int8_t bits) { 1098dc: e92d4070 push {r4, r5, r6, lr} 1098e0: e24dd008 sub sp, sp, #8 1098e4: e1a06002 mov r6, r2 u_int8_t val; int ret; ret = opcd_rc632_reg_read(hdl, reg, &val); 1098e8: e28d2007 add r2, sp, #7 return opcd_rc632_reg_write(hdl, reg, val); } int opcd_rc632_clear_bits(struct rfid_asic_handle *hdl, u_int8_t reg, u_int8_t bits) { 1098ec: e1a05000 mov r5, r0 1098f0: e1a04001 mov r4, r1 u_int8_t val; int ret; ret = opcd_rc632_reg_read(hdl, reg, &val); 1098f4: ebffff56 bl 109654 if (ret < 0) 1098f8: e3500000 cmp r0, #0 1098fc: ba000006 blt 10991c return ret; val &= ~bits; 109900: e5dd3007 ldrb r3, [sp, #7] 109904: e1c36006 bic r6, r3, r6 return opcd_rc632_reg_write(hdl, reg, val); 109908: e1a00005 mov r0, r5 10990c: e1a01004 mov r1, r4 109910: e1a02006 mov r2, r6 ret = opcd_rc632_reg_read(hdl, reg, &val); if (ret < 0) return ret; val &= ~bits; 109914: e5cd6007 strb r6, [sp, #7] return opcd_rc632_reg_write(hdl, reg, val); 109918: ebfffefb bl 10950c } 10991c: e28dd008 add sp, sp, #8 109920: e8bd4070 pop {r4, r5, r6, lr} 109924: e12fff1e bx lr 00109928 : /* turn off register paging */ opcd_rc632_reg_write(NULL, RC632_REG_PAGE0, 0x00); } static int rc632_usb_in(struct req_ctx *rctx) { 109928: e92d4038 push {r3, r4, r5, lr} struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int16_t len = rctx->tot_len-sizeof(*poh); /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); 10992c: e3a03004 mov r3, #4 } static int rc632_usb_in(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int16_t len = rctx->tot_len-sizeof(*poh); 109930: e1d0c0b6 ldrh ip, [r0, #6] opcd_rc632_reg_write(NULL, RC632_REG_PAGE0, 0x00); } static int rc632_usb_in(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; 109934: e5904008 ldr r4, [r0, #8] u_int16_t len = rctx->tot_len-sizeof(*poh); /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); 109938: e1c030b6 strh r3, [r0, #6] /* turn off register paging */ opcd_rc632_reg_write(NULL, RC632_REG_PAGE0, 0x00); } static int rc632_usb_in(struct req_ctx *rctx) { 10993c: e1a05000 mov r5, r0 u_int16_t len = rctx->tot_len-sizeof(*poh); /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); switch (poh->cmd) { 109940: e5d40000 ldrb r0, [r4] } static int rc632_usb_in(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int16_t len = rctx->tot_len-sizeof(*poh); 109944: e24c1004 sub r1, ip, #4 109948: e1a02801 lsl r2, r1, #16 /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); switch (poh->cmd) { 10994c: e2403011 sub r3, r0, #17 } static int rc632_usb_in(struct req_ctx *rctx) { struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data; u_int16_t len = rctx->tot_len-sizeof(*poh); 109950: e1a02822 lsr r2, r2, #16 /* initialize transmit length to header length */ rctx->tot_len = sizeof(*poh); switch (poh->cmd) { 109954: e353000a cmp r3, #10 109958: 979ff103 ldrls pc, [pc, r3, lsl #2] 10995c: ea00000d b 109998 109960: 001099a0 .word 0x001099a0 109964: 001099c4 .word 0x001099c4 109968: 0010998c .word 0x0010998c 10996c: 001099f4 .word 0x001099f4 109970: 00109a10 .word 0x00109a10 109974: 00109a2c .word 0x00109a2c 109978: 00109a4c .word 0x00109a4c 10997c: 0010998c .word 0x0010998c 109980: 0010998c .word 0x0010998c 109984: 00109998 .word 0x00109998 109988: 001099e0 .word 0x001099e0 } return (poh->flags & OPENPCD_FLAG_RESPOND) ? USB_RET_RESPOND : 0; not_impl: DEBUGP("NOT IMPLEMENTED YET "); return USB_ERR(USB_ERR_CMD_NOT_IMPL); 10998c: e59f00f0 ldr r0, [pc, #240] ; 109a84 } 109990: e8bd4038 pop {r3, r4, r5, lr} 109994: e12fff1e bx lr DEBUGP("DUMP REGS "); goto not_impl; break; default: DEBUGP("UNKNOWN "); return USB_ERR(USB_ERR_CMD_UNKNOWN); 109998: e59f00e8 ldr r0, [pc, #232] ; 109a88 10999c: eafffffb b 109990 //} } break; case OPENPCD_CMD_WRITE_REG: DEBUGP("WRITE_REG(0x%02x, 0x%02x) ", poh->reg, poh->val); opcd_rc632_reg_write(NULL, poh->reg, poh->val); 1099a0: e3a00000 mov r0, #0 1099a4: e5d41002 ldrb r1, [r4, #2] 1099a8: e5d42003 ldrb r2, [r4, #3] 1099ac: ebfffed6 bl 10950c 1099b0: e5d43001 ldrb r3, [r4, #1] default: DEBUGP("UNKNOWN "); return USB_ERR(USB_ERR_CMD_UNKNOWN); } return (poh->flags & OPENPCD_FLAG_RESPOND) ? USB_RET_RESPOND : 0; 1099b4: e2132001 ands r2, r3, #1 1099b8: 01a00002 moveq r0, r2 1099bc: 13a00c01 movne r0, #256 ; 0x100 1099c0: eafffff2 b 109990 opcd_rc632_reg_write_set(NULL, poh->data, len); break; case OPENPCD_CMD_WRITE_FIFO: DEBUGP("WRITE FIFO(len=%u): %s ", len, hexdump(poh->data, len)); opcd_rc632_fifo_write(NULL, len, poh->data, 0); 1099c4: e3a00000 mov r0, #0 1099c8: e20210ff and r1, r2, #255 ; 0xff 1099cc: e1a03000 mov r3, r0 1099d0: e2842004 add r2, r4, #4 1099d4: ebffff06 bl 1095f4 1099d8: e5d43001 ldrb r3, [r4, #1] break; 1099dc: eafffff4 b 1099b4 DEBUGP("WRITE_REG(0x%02x, 0x%02x) ", poh->reg, poh->val); opcd_rc632_reg_write(NULL, poh->reg, poh->val); break; case OPENPCD_CMD_WRITE_REG_SET: DEBUGP("WRITE_REG_SET(%s) ", hexdump(poh->data, len)); opcd_rc632_reg_write_set(NULL, poh->data, len); 1099e0: e3a00000 mov r0, #0 1099e4: e2841004 add r1, r4, #4 1099e8: ebfffed9 bl 109554 1099ec: e5d43001 ldrb r3, [r4, #1] break; 1099f0: eaffffef b 1099b4 DEBUGP("WRITE VFIFO "); goto not_impl; break; case OPENPCD_CMD_REG_BITS_CLEAR: DEBUGP("CLEAR BITS "); poh->val = opcd_rc632_clear_bits(NULL, poh->reg, poh->val); 1099f4: e3a00000 mov r0, #0 1099f8: e5d41002 ldrb r1, [r4, #2] 1099fc: e5d42003 ldrb r2, [r4, #3] 109a00: ebffffb5 bl 1098dc 109a04: e5d43001 ldrb r3, [r4, #1] 109a08: e5c40003 strb r0, [r4, #3] break; 109a0c: eaffffe8 b 1099b4 case OPENPCD_CMD_REG_BITS_SET: DEBUGP("SET BITS "); poh->val = opcd_rc632_set_bits(NULL, poh->reg, poh->val); 109a10: e3a00000 mov r0, #0 109a14: e5d41002 ldrb r1, [r4, #2] 109a18: e5d42003 ldrb r2, [r4, #3] 109a1c: ebffff9b bl 109890