dfu.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00001ac0  00000000  00000000  00008000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data.shared  00000008  00200020  00001ac0  00010020  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  2 .data         00000024  00201ac0  00001ac8  00011ac0  2**2
                  CONTENTS, ALLOC, LOAD, CODE
  3 .dfu.functab  00000030  00003fd0  00003fd0  00013fd0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .bss          00000105  00201ae4  00001aec  00011ae4  2**2
                  ALLOC
  5 .ARM.attributes 0000002e  00000000  00000000  00014000  2**0
                  CONTENTS, READONLY
  6 .comment      0000002a  00000000  00000000  0001402e  2**0
                  CONTENTS, READONLY
  7 .debug_aranges 000000c8  00000000  00000000  00014058  2**3
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_pubnames 000002b7  00000000  00000000  00014120  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_info   000040e7  00000000  00000000  000143d7  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00000bb3  00000000  00000000  000184be  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_line   0000089e  00000000  00000000  00019071  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_frame  00000540  00000000  00000000  00019910  2**2
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_str    00001637  00000000  00000000  00019e50  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_loc    00001193  00000000  00000000  0001b487  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 000001d0  00000000  00000000  0001c620  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_pubtypes 00000485  00000000  00000000  0001c7f0  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <reset>:
//*- guarantee a valid jump. For the moment, all are just looping.
//*- If an exception occurs before remap, this would result in an infinite loop.
//*- To ensure if a exeption occurs before start application to infinite loop.
//*------------------------------------------------------------------------------*/

                B           InitReset           /* 0x00 Reset handler */
       0:	ea000026 	b	a0 <InitReset>

00000004 <undefvec>:
undefvec:
                B           undefvec            /* 0x04 Undefined Instruction */
       4:	eafffffe 	b	4 <undefvec>

00000008 <swivec>:
swivec:
                B           swivec              /* 0x08 Software Interrupt */
       8:	eafffffe 	b	8 <swivec>

0000000c <pabtvec>:
pabtvec:
                B           pabtvec             /* 0x0C Prefetch Abort */
       c:	eafffffe 	b	c <pabtvec>

00000010 <dabtvec>:
dabtvec:
		b	dabtvec             /* 0x10 Data Abort */
      10:	eafffffe 	b	10 <dabtvec>

00000014 <rsvdvec>:
rsvdvec:
		b	rsvdvec             /* 0x14 reserved  */
      14:	eafffffe 	b	14 <rsvdvec>

00000018 <irqvec>:
irqvec:
		b	IRQ_Handler_Entry	/* 0x18 IRQ */
      18:	ea00000b 	b	4c <IRQ_Handler_Entry>

0000001c <fiqvec>:
fiqvec:
		ldr	pc, [pc, #-0xF20]	 /* 0x1c FIQ */
      1c:	e51fff20 	ldr	pc, [pc, #-3872]	; fffff104 <AT91C_BASE_AIC+0x104>

00000020 <dfu_state_dummy>:
      20:	00000000 	.word	0x00000000

00000024 <FIQ_Handler_Entry>:

/*- Switch in SVC/User Mode to allow User Stack access for C code 	*/
/* because the FIQ is not yet acknowledged*/

/*- Save and r0 in FIQ_Register */
		mov	r9, r0
      24:	e1a09000 	mov	r9, r0
		ldr	r0, [r8, #AIC_FVR]
      28:	e5980104 	ldr	r0, [r8, #260]	; 0x104
		msr	CPSR_c, #I_BIT | F_BIT | ARM_MODE_SVC
      2c:	e321f0d3 	msr	CPSR_c, #211	; 0xd3

		/*- Save scratch/used registers and LR in User Stack */
		stmfd	sp!, { r1-r3, r12, lr}
      30:	e92d500e 	push	{r1, r2, r3, ip, lr}

		/*- Branch to the routine pointed by the AIC_FVR */
		mov	r14, pc
      34:	e1a0e00f 	mov	lr, pc
		bx	r0
      38:	e12fff10 	bx	r0

		/*- Restore scratch/used registers and LR from User Stack */
		ldmia	sp!, { r1-r3, r12, lr}
      3c:	e8bd500e 	pop	{r1, r2, r3, ip, lr}

		/*- Leave Interrupts disabled and switch back in FIQ mode */
		msr	CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
      40:	e321f0d1 	msr	CPSR_c, #209	; 0xd1

		/*- Restore the R0 ARM_MODE_SVC register */
		mov	r0,r9
      44:	e1a00009 	mov	r0, r9

		/*- Restore the Program Counter using the LR_fiq directly in the PC */
		subs        pc, lr, #4
      48:	e25ef004 	subs	pc, lr, #4

0000004c <IRQ_Handler_Entry>:

IRQ_Handler_Entry:

		/*- Manage Exception Entry  */
		/*- Adjust and save LR_irq in IRQ stack  */
		sub         lr, lr, #4
      4c:	e24ee004 	sub	lr, lr, #4
		stmfd       sp!, {lr}
      50:	e52de004 	push	{lr}		; (str lr, [sp, #-4]!)

		/*- Save SPSR need to be saved for nested interrupt */
		mrs	r14, SPSR
      54:	e14fe000 	mrs	lr, SPSR
		stmfd	sp!, {r14}
      58:	e52de004 	push	{lr}		; (str lr, [sp, #-4]!)

		/*- Save and r0 in IRQ stack  */
		stmfd	sp!, {r0}
      5c:	e52d0004 	push	{r0}		; (str r0, [sp, #-4]!)

		/*- Write in the IVR to support Protect Mode  */
		/*- No effect in Normal Mode  */
		/*- De-assert the NIRQ and clear the source in Protect Mode */
		ldr	r14, =AT91C_BASE_AIC
      60:	e59fe148 	ldr	lr, [pc, #328]	; 1b0 <AT91F_Spurious_handler+0x4>
		ldr	r0 , [r14, #AIC_IVR]
      64:	e59e0100 	ldr	r0, [lr, #256]	; 0x100
		str	r14, [r14, #AIC_IVR]
      68:	e58ee100 	str	lr, [lr, #256]	; 0x100

		/*- Enable Interrupt and Switch in Supervisor Mode */
		msr	CPSR_c, #ARM_MODE_SVC
      6c:	e321f013 	msr	CPSR_c, #19

		/*- Save scratch/used registers and LR in User Stack */
		stmfd	sp!, { r1-r3, r12, r14}
      70:	e92d500e 	push	{r1, r2, r3, ip, lr}

		/*- Branch to the routine pointed by the AIC_IVR  */
		mov	r14, pc
      74:	e1a0e00f 	mov	lr, pc
		bx	r0
      78:	e12fff10 	bx	r0

		/*- Restore scratch/used registers and LR from User Stack*/
		ldmia	sp!, { r1-r3, r12, r14}
      7c:	e8bd500e 	pop	{r1, r2, r3, ip, lr}

		/*- Disable Interrupt and switch back in IRQ mode */
		msr	CPSR_c, #I_BIT | ARM_MODE_IRQ
      80:	e321f092 	msr	CPSR_c, #146	; 0x92

		/*- Mark the End of Interrupt on the AIC */
		ldr	r14, =AT91C_BASE_AIC
      84:	e59fe124 	ldr	lr, [pc, #292]	; 1b0 <AT91F_Spurious_handler+0x4>
		str	r14, [r14, #AIC_EOICR]
      88:	e58ee130 	str	lr, [lr, #304]	; 0x130

		/*- Restore SPSR_irq and r0 from IRQ stack */
		ldmia	sp!, {r0}
      8c:	e49d0004 	pop	{r0}		; (ldr r0, [sp], #4)

		/*- Restore SPSR_irq and r0 from IRQ stack */
		ldmia	sp!, {r14}
      90:	e49de004 	pop	{lr}		; (ldr lr, [sp], #4)
		msr	SPSR_cxsf, r14
      94:	e16ff00e 	msr	SPSR_fsxc, lr

		/*- Restore adjusted  LR_irq from IRQ stack directly in the PC */
		ldmia	sp!, {pc}^
      98:	e8fd8000 	ldm	sp!, {pc}^

0000009c <.RAM_TOP>:
      9c:	00208000 	.word	0x00208000

000000a0 <InitReset>:
/*------------------------------------------------------------------------------*/
            	.extern   AT91F_LowLevelInit
/*- minumum C initialization */
/*- call  AT91F_LowLevelInit( void) */

	ldr	r13,.RAM_TOP            /* temporary stack in internal RAM */
      a0:	e51fd00c 	ldr	sp, [pc, #-12]	; 9c <.RAM_TOP>
/*--Call Low level init function in ABSOLUTE through the Interworking	*/
        ldr	r0,=AT91F_LowLevelInit
      a4:	e59f0108 	ldr	r0, [pc, #264]	; 1b4 <AT91F_Spurious_handler+0x8>
	mov	lr, pc
      a8:	e1a0e00f 	mov	lr, pc
	bx	r0
      ac:	e12fff10 	bx	r0


/*------------------------------------------------------------------------------
//*- Setup the stack for each mode
//*-------------------------------*/
                mov     r0,r13
      b0:	e1a0000d 	mov	r0, sp

/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/
                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
      b4:	e321f0d1 	msr	CPSR_c, #209	; 0xd1
		mov	r13, r0
      b8:	e1a0d000 	mov	sp, r0
		sub	r0, r0, #FIQ_Stack_Size
      bc:	e2400b01 	sub	r0, r0, #1024	; 0x400

/*- Init the FIQ register*/
            	ldr     r8, =AT91C_BASE_AIC
      c0:	e59f80e8 	ldr	r8, [pc, #232]	; 1b0 <AT91F_Spurious_handler+0x4>

/*- Set up Interrupt Mode and set IRQ Mode Stack*/
                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
      c4:	e321f0d2 	msr	CPSR_c, #210	; 0xd2
                mov     r13, r0                     /* Init stack IRQ */
      c8:	e1a0d000 	mov	sp, r0
                sub     r0, r0, #IRQ_Stack_Size
      cc:	e2400b01 	sub	r0, r0, #1024	; 0x400

/*- Set up Supervisor Mode and set Supervisor Mode Stack*/
                msr     CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
      d0:	e321f0d3 	msr	CPSR_c, #211	; 0xd3
                mov     r13, r0                     /* Init stack Sup */
      d4:	e1a0d000 	mov	sp, r0

/* - Enable Interrupts and FIQ */
                msr     CPSR_c, #ARM_MODE_SVC
      d8:	e321f013 	msr	CPSR_c, #19

#ifdef CONFIG_DFU_MAGIC
		ldr	r1, =AT91C_RSTC_RSR
      dc:	e59f10d4 	ldr	r1, [pc, #212]	; 1b8 <AT91F_Spurious_handler+0xc>
		ldr	r2, [r1]
      e0:	e5912000 	ldr	r2, [r1]
		#and	r2, r2, AT91C_RSTC_RSTTYP
		tst	r2, #AT91C_RSTC_RSTTYP_SOFTWARE
      e4:	e3120c03 	tst	r2, #768	; 0x300
		beq	dfu_magic_end
      e8:	0a000003 	beq	fc <dfu_magic_end>

		ldr	r1, =dfu_state
      ec:	e59f10c8 	ldr	r1, [pc, #200]	; 1bc <AT91F_Spurious_handler+0x10>
		ldr	r2, [r1]
      f0:	e5912000 	ldr	r2, [r1]
		cmp	r2, #DFU_STATE_appDETACH
      f4:	e3520001 	cmp	r2, #1
		beq	_reloc_dfu
      f8:	0a000011 	beq	144 <_reloc_dfu>

000000fc <dfu_magic_end>:
dfu_magic_end:
#endif

# Relocate DFU .data.shared section (Copy from ROM to RAM)
                LDR     R1, =_etext
      fc:	e59f10bc 	ldr	r1, [pc, #188]	; 1c0 <AT91F_Spurious_handler+0x14>
                LDR     R2, =_data_shared
     100:	e59f20bc 	ldr	r2, [pc, #188]	; 1c4 <AT91F_Spurious_handler+0x18>
                LDR     R3, =_edata_shared
     104:	e59f30bc 	ldr	r3, [pc, #188]	; 1c8 <AT91F_Spurious_handler+0x1c>

00000108 <LoopRelDS>:
LoopRelDS:      CMP     R2, R3
     108:	e1520003 	cmp	r2, r3
                LDRLO   R0, [R1], #4
     10c:	34910004 	ldrcc	r0, [r1], #4
                STRLO   R0, [R2], #4
     110:	34820004 	strcc	r0, [r2], #4
                BLO     LoopRelDS
     114:	3afffffb 	bcc	108 <LoopRelDS>
                STRLO   R0, [R1], #4
                BLO     LoopZI
*/

		/* prepare c function call to main */
		mov	r0, #0	/* argc = 0 */
     118:	e3a00000 	mov	r0, #0
		ldr	lr, =exit
     11c:	e59fe0a8 	ldr	lr, [pc, #168]	; 1cc <AT91F_Spurious_handler+0x20>
		ldr	r10, =0x00104000
     120:	e3a0a941 	mov	sl, #1064960	; 0x104000

#ifdef CONFIG_DFU_SWITCH
		/* check whether bootloader button is pressed */
		ldr	r1, =AT91C_PMC_PCER
     124:	e59f10a4 	ldr	r1, [pc, #164]	; 1d0 <AT91F_Spurious_handler+0x24>
		mov	r2, #(1 << AT91C_ID_PIOA)
     128:	e3a02004 	mov	r2, #4
		str	r2, [r1] 
     12c:	e5812000 	str	r2, [r1]

		ldr 	r1, =AT91C_BASE_PIOA
     130:	e59f109c 	ldr	r1, [pc, #156]	; 1d4 <AT91F_Spurious_handler+0x28>
		ldr	r2, [r1, #PIOA_PDSR]
     134:	e591203c 	ldr	r2, [r1, #60]	; 0x3c
		tst	r2, #PIO_BOOTLDR
     138:	e3120302 	tst	r2, #134217728	; 0x8000000
		bne	_reloc_dfu
     13c:	1a000000 	bne	144 <_reloc_dfu>
#endif

		bx	r10
     140:	e12fff1a 	bx	sl

00000144 <_reloc_dfu>:

_reloc_dfu:
		/* Relocate DFU .data section (Copy from ROM to RAM) */
                LDR     R1, =_data_flash
     144:	e59f108c 	ldr	r1, [pc, #140]	; 1d8 <AT91F_Spurious_handler+0x2c>
                LDR     R2, =_data
     148:	e59f208c 	ldr	r2, [pc, #140]	; 1dc <AT91F_Spurious_handler+0x30>
                LDR     R3, =_edata
     14c:	e59f308c 	ldr	r3, [pc, #140]	; 1e0 <AT91F_Spurious_handler+0x34>

00000150 <LoopRel>:
LoopRel:        CMP     R2, R3
     150:	e1520003 	cmp	r2, r3
                LDRLO   R0, [R1], #4
     154:	34910004 	ldrcc	r0, [r1], #4
                STRLO   R0, [R2], #4
     158:	34820004 	strcc	r0, [r2], #4
                BLO     LoopRel
     15c:	3afffffb 	bcc	150 <LoopRel>

		/* Clear DFU .bss section (Zero init) */
                MOV     R0, #0
     160:	e3a00000 	mov	r0, #0
                LDR     R1, =__bss_start__
     164:	e59f1078 	ldr	r1, [pc, #120]	; 1e4 <AT91F_Spurious_handler+0x38>
                LDR     R2, =__bss_end__
     168:	e59f2078 	ldr	r2, [pc, #120]	; 1e8 <AT91F_Spurious_handler+0x3c>

0000016c <LoopZI>:
LoopZI:         CMP     R1, R2
     16c:	e1510002 	cmp	r1, r2
                STRLO   R0, [R1], #4
     170:	34810004 	strcc	r0, [r1], #4
                BLO     LoopZI
     174:	3afffffc 	bcc	16c <LoopZI>

		/* relocate DFU .text into RAM */
		ldr	r1, =0x00100000
     178:	e3a01601 	mov	r1, #1048576	; 0x100000
		ldr	r2, =0x00200000
     17c:	e3a02602 	mov	r2, #2097152	; 0x200000
		ldr	r3, =_etext
     180:	e59f3038 	ldr	r3, [pc, #56]	; 1c0 <AT91F_Spurious_handler+0x14>
		add	r3, r3, r2
     184:	e0833002 	add	r3, r3, r2

00000188 <loop_rel_t>:
loop_rel_t:	cmp	r2, r3
     188:	e1520003 	cmp	r2, r3
		ldrlo	r4, [r1], #4
     18c:	34914004 	ldrcc	r4, [r1], #4
		strlo	r4, [r2], #4
     190:	34824004 	strcc	r4, [r2], #4
		blo	loop_rel_t
     194:	3afffffb 	bcc	188 <loop_rel_t>
		ldr	r4, =_remap_call_dfu
     198:	e59f404c 	ldr	r4, [pc, #76]	; 1ec <AT91F_Spurious_handler+0x40>
		bx	r4
     19c:	e12fff14 	bx	r4

000001a0 <exit>:

/* "exit" dummy to avoid sbrk write read etc. needed by the newlib default "exit" */
        .global exit
        .func   exit
exit:
        b    .
     1a0:	eafffffe 	b	1a0 <exit>

000001a4 <AT91F_Default_FIQ_handler>:
//* This module is only linked if needed for closing files.
//*---------------------------------------------------------------*/
        .global AT91F_Default_FIQ_handler
        .func   AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler:
            b     AT91F_Default_FIQ_handler
     1a4:	eafffffe 	b	1a4 <AT91F_Default_FIQ_handler>

000001a8 <AT91F_Default_IRQ_handler>:
        .endfunc

        .global AT91F_Default_IRQ_handler
        .func   AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler:
            b     AT91F_Default_IRQ_handler
     1a8:	eafffffe 	b	1a8 <AT91F_Default_IRQ_handler>

000001ac <AT91F_Spurious_handler>:
        .endfunc

        .global AT91F_Spurious_handler
        .func   AT91F_Spurious_handler
AT91F_Spurious_handler:
            b     AT91F_Spurious_handler
     1ac:	eafffffe 	b	1ac <AT91F_Spurious_handler>
     1b0:	fffff000 	.word	0xfffff000
     1b4:	000001f0 	.word	0x000001f0
     1b8:	fffffd04 	.word	0xfffffd04
     1bc:	00200020 	.word	0x00200020
     1c0:	00001ac0 	.word	0x00001ac0
     1c4:	00200020 	.word	0x00200020
     1c8:	00200028 	.word	0x00200028
     1cc:	000001a0 	.word	0x000001a0
     1d0:	fffffc10 	.word	0xfffffc10
     1d4:	fffff400 	.word	0xfffff400
     1d8:	00001ac8 	.word	0x00001ac8
     1dc:	00201ac0 	.word	0x00201ac0
     1e0:	00201ae4 	.word	0x00201ae4
     1e4:	00201ae4 	.word	0x00201ae4
     1e8:	00201bec 	.word	0x00201bec
     1ec:	00201ac0 	.word	0x00201ac0

000001f0 <AT91F_LowLevelInit>:
//*        this function can be use a Stack, depending the compilation
//*        optimization mode
//*----------------------------------------------------------------------------
void
AT91F_LowLevelInit (void)
{
     1f0:	e24dd008 	sub	sp, sp, #8
  volatile int i;
  
  //* Debounce power supply
  for(i=0;i<1024;i++);
     1f4:	e3a03000 	mov	r3, #0
     1f8:	ea000001 	b	204 <AT91F_LowLevelInit+0x14>
     1fc:	e59d3004 	ldr	r3, [sp, #4]
     200:	e2833001 	add	r3, r3, #1
     204:	e58d3004 	str	r3, [sp, #4]
     208:	e59d3004 	ldr	r3, [sp, #4]
     20c:	e3530b01 	cmp	r3, #1024	; 0x400
     210:	bafffff9 	blt	1fc <AT91F_LowLevelInit+0xc>
  
  AT91PS_PMC pPMC = AT91C_BASE_PMC;
  //* Set Flash Waite sate
  //  Single Cycle Access at Up to 30 MHz, or 40
  //  if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
  AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN) & (48 << 16)) | AT91C_MC_FWS_1FWS;
     214:	e59f20c8 	ldr	r2, [pc, #200]	; 2e4 <AT91F_LowLevelInit+0xf4>
     218:	e3e03000 	mvn	r3, #0
     21c:	e503209f 	str	r2, [r3, #-159]	; 0xffffff61

  //* Set MCK at 47 923 200
  // 1 Enabling the Main Oscillator:
  // SCK = 1/32768 = 30.51 uSecond
  // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
  pPMC->PMC_MOR = ((AT91C_CKGR_OSCOUNT) & (0x06 << 8)) | AT91C_CKGR_MOSCEN;
     220:	e59f20c0 	ldr	r2, [pc, #192]	; 2e8 <AT91F_LowLevelInit+0xf8>
     224:	e50323df 	str	r2, [r3, #-991]	; 0xfffffc21
  // Wait the startup time
  while (!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
     228:	e3e03c03 	mvn	r3, #768	; 0x300
     22c:	e5132097 	ldr	r2, [r3, #-151]	; 0xffffff69
     230:	e3120001 	tst	r2, #1
     234:	0afffffb 	beq	228 <AT91F_LowLevelInit+0x38>
#if 0
  pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
		    (AT91C_CKGR_PLLCOUNT & (28 << 8)) |
		    (AT91C_CKGR_MUL & (25 << 16)));
#else
  pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 24) |
     238:	e59f20ac 	ldr	r2, [pc, #172]	; 2ec <AT91F_LowLevelInit+0xfc>
     23c:	e50320d3 	str	r2, [r3, #-211]	; 0xffffff2d
		    (AT91C_CKGR_PLLCOUNT & (28 << 8)) |
		    (AT91C_CKGR_MUL & (125 << 16)));
#endif

  // Wait the startup time
  while (!(pPMC->PMC_SR & AT91C_PMC_LOCK));
     240:	e3e03c03 	mvn	r3, #768	; 0x300
     244:	e5133097 	ldr	r3, [r3, #-151]	; 0xffffff69
     248:	e3130004 	tst	r3, #4
     24c:	0afffffb 	beq	240 <AT91F_LowLevelInit+0x50>
  while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
     250:	e3e03c03 	mvn	r3, #768	; 0x300
     254:	e5132097 	ldr	r2, [r3, #-151]	; 0xffffff69
     258:	e3120008 	tst	r2, #8
     25c:	0afffffb 	beq	250 <AT91F_LowLevelInit+0x60>
  // 4. Selection of Master Clock and Processor Clock
  // select the PLL clock divided by 2
  pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
     260:	e3a02004 	mov	r2, #4
     264:	e50320cf 	str	r2, [r3, #-207]	; 0xffffff31
  while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
     268:	e3e03c03 	mvn	r3, #768	; 0x300
     26c:	e5132097 	ldr	r2, [r3, #-151]	; 0xffffff69
     270:	e3120008 	tst	r2, #8
     274:	0afffffb 	beq	268 <AT91F_LowLevelInit+0x78>

  pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
     278:	e51320cf 	ldr	r2, [r3, #-207]	; 0xffffff31
     27c:	e3822003 	orr	r2, r2, #3
     280:	e50320cf 	str	r2, [r3, #-207]	; 0xffffff31
  while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
     284:	e3e03c03 	mvn	r3, #768	; 0x300
     288:	e5133097 	ldr	r3, [r3, #-151]	; 0xffffff69
     28c:	e3130008 	tst	r3, #8
     290:	0afffffb 	beq	284 <AT91F_LowLevelInit+0x94>

  // Set up the default interrupts handler vectors
  AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
     294:	e59f2054 	ldr	r2, [pc, #84]	; 2f0 <AT91F_LowLevelInit+0x100>
     298:	e3e03c0f 	mvn	r3, #3840	; 0xf00
     29c:	e503207f 	str	r2, [r3, #-127]	; 0xffffff81
  for (i = 1; i < 31; i++)
     2a0:	e3a03001 	mov	r3, #1
     2a4:	ea000005 	b	2c0 <AT91F_LowLevelInit+0xd0>
    {
      AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
     2a8:	e59d3004 	ldr	r3, [sp, #4]
     2ac:	e59f2040 	ldr	r2, [pc, #64]	; 2f4 <AT91F_LowLevelInit+0x104>
     2b0:	e1a03103 	lsl	r3, r3, #2
     2b4:	e5032f80 	str	r2, [r3, #-3968]	; 0xfffff080
  pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
  while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));

  // Set up the default interrupts handler vectors
  AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
  for (i = 1; i < 31; i++)
     2b8:	e59d3004 	ldr	r3, [sp, #4]
     2bc:	e2833001 	add	r3, r3, #1
     2c0:	e58d3004 	str	r3, [sp, #4]
     2c4:	e59d3004 	ldr	r3, [sp, #4]
     2c8:	e353001e 	cmp	r3, #30
     2cc:	dafffff5 	ble	2a8 <AT91F_LowLevelInit+0xb8>
    {
      AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
    }
  AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler;
     2d0:	e59f2020 	ldr	r2, [pc, #32]	; 2f8 <AT91F_LowLevelInit+0x108>
     2d4:	e3e03c0f 	mvn	r3, #3840	; 0xf00
     2d8:	e5832035 	str	r2, [r3, #53]	; 0x35

}
     2dc:	e28dd008 	add	sp, sp, #8
     2e0:	e12fff1e 	bx	lr
     2e4:	00300100 	.word	0x00300100
     2e8:	00000601 	.word	0x00000601
     2ec:	007d1c18 	.word	0x007d1c18
     2f0:	000001a4 	.word	0x000001a4
     2f4:	000001a8 	.word	0x000001a8
     2f8:	000001ac 	.word	0x000001ac

000002fc <AT91F_PDC_SetNextRx>:
static inline void AT91F_PDC_SetNextRx (
	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
	unsigned char *address,// \arg address to the next bloc to be received
	unsigned int bytes)  // \arg number of bytes to be received
{
	pPDC->PDC_RNPR = (unsigned int) address;
     2fc:	e5801010 	str	r1, [r0, #16]
	pPDC->PDC_RNCR = bytes;
     300:	e5802014 	str	r2, [r0, #20]
}
     304:	e12fff1e 	bx	lr

00000308 <AT91F_PDC_SetNextTx>:
static inline void AT91F_PDC_SetNextTx (
	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
	const unsigned char *address,// \arg address to the next bloc to be transmitted
	unsigned int bytes)    // \arg number of bytes to be transmitted
{
	pPDC->PDC_TNPR = (unsigned int) address;
     308:	e5801018 	str	r1, [r0, #24]
	pPDC->PDC_TNCR = bytes;
     30c:	e580201c 	str	r2, [r0, #28]
}
     310:	e12fff1e 	bx	lr

00000314 <AT91F_PDC_SetRx>:
static inline void AT91F_PDC_SetRx (
	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
	unsigned char *address,// \arg address to the next bloc to be received
	unsigned int bytes)    // \arg number of bytes to be received
{
	pPDC->PDC_RPR = (unsigned int) address;
     314:	e5801000 	str	r1, [r0]
	pPDC->PDC_RCR = bytes;
     318:	e5802004 	str	r2, [r0, #4]
}
     31c:	e12fff1e 	bx	lr

00000320 <AT91F_PDC_SetTx>:
static inline void AT91F_PDC_SetTx (
	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
	const unsigned char *address,// \arg address to the next bloc to be transmitted
	unsigned int bytes)    // \arg number of bytes to be transmitted
{
	pPDC->PDC_TPR = (unsigned int) address;
     320:	e5801008 	str	r1, [r0, #8]
	pPDC->PDC_TCR = bytes;
     324:	e580200c 	str	r2, [r0, #12]
}
     328:	e12fff1e 	bx	lr

0000032c <AT91F_PDC_DisableTx>:
//* \brief Disable transmit
//*----------------------------------------------------------------------------
static inline void AT91F_PDC_DisableTx (
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
     32c:	e3a03c02 	mov	r3, #512	; 0x200
     330:	e5803020 	str	r3, [r0, #32]
}
     334:	e12fff1e 	bx	lr

00000338 <AT91F_PDC_DisableRx>:
//* \brief Disable receive
//*----------------------------------------------------------------------------
static inline void AT91F_PDC_DisableRx (
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
     338:	e3a03002 	mov	r3, #2
     33c:	e5803020 	str	r3, [r0, #32]
}
     340:	e12fff1e 	bx	lr

00000344 <AT91F_CKGR_GetMainClock>:
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_CKGR_GetMainClock (
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
     344:	e5900004 	ldr	r0, [r0, #4]
     348:	e1a00800 	lsl	r0, r0, #16
     34c:	e1a00820 	lsr	r0, r0, #16
     350:	e0000091 	mul	r0, r1, r0
}
     354:	e1a00220 	lsr	r0, r0, #4
     358:	e12fff1e 	bx	lr

0000035c <AT91F_AIC_ConfigureIt>:
	unsigned int oldHandler;
    unsigned int mask ;

    oldHandler = pAic->AIC_SVR[irq_id];

    mask = 0x1 << irq_id ;
     35c:	e3a0c001 	mov	ip, #1
     360:	e1a0c11c 	lsl	ip, ip, r1
	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
	unsigned int irq_id,     // \arg interrupt number to initialize
	unsigned int priority,   // \arg priority to give to the interrupt
	unsigned int src_type,   // \arg activation and sense of activation
	void (*newHandler) () ) // \arg address of the interrupt handler
{
     364:	e92d0070 	push	{r4, r5, r6}
	unsigned int oldHandler;
    unsigned int mask ;

    oldHandler = pAic->AIC_SVR[irq_id];
     368:	e2814020 	add	r4, r1, #32
     36c:	e7905104 	ldr	r5, [r0, r4, lsl #2]

    mask = 0x1 << irq_id ;
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask ;
    //* Save the interrupt handler routine pointer and the interrupt priority
    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
     370:	e59d600c 	ldr	r6, [sp, #12]
    //* Store the Source Mode Register
    pAic->AIC_SMR[irq_id] = src_type | priority  ;
     374:	e1833002 	orr	r3, r3, r2

    oldHandler = pAic->AIC_SVR[irq_id];

    mask = 0x1 << irq_id ;
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask ;
     378:	e580c124 	str	ip, [r0, #292]	; 0x124
    //* Save the interrupt handler routine pointer and the interrupt priority
    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
     37c:	e7806104 	str	r6, [r0, r4, lsl #2]
    //* Store the Source Mode Register
    pAic->AIC_SMR[irq_id] = src_type | priority  ;
     380:	e7803101 	str	r3, [r0, r1, lsl #2]
    //* Clear the interrupt on the interrupt controller
    pAic->AIC_ICCR = mask ;
     384:	e580c128 	str	ip, [r0, #296]	; 0x128

	return oldHandler;
}
     388:	e1a00005 	mov	r0, r5
     38c:	e8bd0070 	pop	{r4, r5, r6}
     390:	e12fff1e 	bx	lr

00000394 <AT91F_AIC_SetExceptionVector>:
	unsigned int *pVector, // \arg pointer to the AIC registers
	void (*Handler) () )   // \arg Interrupt Handler
{
	unsigned int oldVector = *pVector;

	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
     394:	e59f2028 	ldr	r2, [pc, #40]	; 3c4 <AT91F_AIC_SetExceptionVector+0x30>
//* \brief Configure vector handler
//*----------------------------------------------------------------------------
unsigned int  AT91F_AIC_SetExceptionVector (
	unsigned int *pVector, // \arg pointer to the AIC registers
	void (*Handler) () )   // \arg Interrupt Handler
{
     398:	e1a03000 	mov	r3, r0
	unsigned int oldVector = *pVector;

	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
     39c:	e1510002 	cmp	r1, r2
		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
	else
		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
     3a0:	10632001 	rsbne	r2, r3, r1
     3a4:	12422008 	subne	r2, r2, #8
     3a8:	11a02122 	lsrne	r2, r2, #2
     3ac:	13c224ff 	bicne	r2, r2, #-16777216	; 0xff000000
     3b0:	138224ea 	orrne	r2, r2, #-369098752	; 0xea000000
//*----------------------------------------------------------------------------
unsigned int  AT91F_AIC_SetExceptionVector (
	unsigned int *pVector, // \arg pointer to the AIC registers
	void (*Handler) () )   // \arg Interrupt Handler
{
	unsigned int oldVector = *pVector;
     3b4:	e5900000 	ldr	r0, [r0]

	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
     3b8:	05831000 	streq	r1, [r3]
	else
		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
     3bc:	15832000 	strne	r2, [r3]

	return oldVector;
}
     3c0:	e12fff1e 	bx	lr
     3c4:	e51fff20 	.word	0xe51fff20

000003c8 <AT91F_AIC_Open>:
	void (*IrqHandler) (),  // \arg Default IRQ vector exception
	void (*FiqHandler) (),  // \arg Default FIQ vector exception
	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
	void (*SpuriousHandler) (), // \arg Default Spurious Handler
	unsigned int protectMode)   // \arg Debug Control Register
{
     3c8:	e92d41f3 	push	{r0, r1, r4, r5, r6, r7, r8, lr}
     3cc:	e1a04000 	mov	r4, r0
     3d0:	e1a06001 	mov	r6, r1
     3d4:	e1a08002 	mov	r8, r2
     3d8:	e1a07003 	mov	r7, r3
	int i;

	// Disable all interrupts and set IVR to the default handler
	for (i = 0; i < 32; ++i) {
     3dc:	e3a05000 	mov	r5, #0
//*----------------------------------------------------------------------------
static inline void AT91F_AIC_DisableIt (
	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
	unsigned int irq_id ) // \arg interrupt number to initialize
{
    unsigned int mask = 0x1 << irq_id;
     3e0:	e3a03001 	mov	r3, #1
     3e4:	e1a03513 	lsl	r3, r3, r5
		AT91F_AIC_DisableIt(pAic, i);
		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
     3e8:	e1a01005 	mov	r1, r5
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask ;
     3ec:	e5843124 	str	r3, [r4, #292]	; 0x124
     3f0:	e1a00004 	mov	r0, r4
    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
    pAic->AIC_ICCR = mask ;
     3f4:	e5843128 	str	r3, [r4, #296]	; 0x128
     3f8:	e3a02000 	mov	r2, #0
     3fc:	e3a03040 	mov	r3, #64	; 0x40
	unsigned int protectMode)   // \arg Debug Control Register
{
	int i;

	// Disable all interrupts and set IVR to the default handler
	for (i = 0; i < 32; ++i) {
     400:	e2855001 	add	r5, r5, #1
		AT91F_AIC_DisableIt(pAic, i);
		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
     404:	e58d7000 	str	r7, [sp]
     408:	ebffffd3 	bl	35c <AT91F_AIC_ConfigureIt>
	unsigned int protectMode)   // \arg Debug Control Register
{
	int i;

	// Disable all interrupts and set IVR to the default handler
	for (i = 0; i < 32; ++i) {
     40c:	e3550020 	cmp	r5, #32
     410:	1afffff2 	bne	3e0 <AT91F_AIC_Open+0x18>
		AT91F_AIC_DisableIt(pAic, i);
		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
	}

	// Set the IRQ exception vector
	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
     414:	e1a01006 	mov	r1, r6
     418:	e3a00018 	mov	r0, #24
     41c:	ebffffdc 	bl	394 <AT91F_AIC_SetExceptionVector>
	// Set the Fast Interrupt exception vector
	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
     420:	e3a0001c 	mov	r0, #28
     424:	e1a01008 	mov	r1, r8
     428:	ebffffd9 	bl	394 <AT91F_AIC_SetExceptionVector>

	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
     42c:	e59d3020 	ldr	r3, [sp, #32]
     430:	e5843134 	str	r3, [r4, #308]	; 0x134
	pAic->AIC_DCR = protectMode;
     434:	e59d3024 	ldr	r3, [sp, #36]	; 0x24
     438:	e5843138 	str	r3, [r4, #312]	; 0x138
}
     43c:	e8bd41fc 	pop	{r2, r3, r4, r5, r6, r7, r8, lr}
     440:	e12fff1e 	bx	lr

00000444 <AT91F_PDC_Open>:
//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_Open
//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
//*----------------------------------------------------------------------------
void AT91F_PDC_Open(AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
{
     444:	e92d4010 	push	{r4, lr}
     448:	e1a04000 	mov	r4, r0
    //* Disable the RX and TX PDC transfer requests
	AT91F_PDC_DisableRx(pPDC);
     44c:	ebffffb9 	bl	338 <AT91F_PDC_DisableRx>
	AT91F_PDC_DisableTx(pPDC);
     450:	e1a00004 	mov	r0, r4
     454:	ebffffb4 	bl	32c <AT91F_PDC_DisableTx>

	//* Reset all Counter register Next buffer first
	AT91F_PDC_SetNextTx(pPDC, NULL, 0);
     458:	e3a01000 	mov	r1, #0
     45c:	e1a02001 	mov	r2, r1
     460:	e1a00004 	mov	r0, r4
     464:	ebffffa7 	bl	308 <AT91F_PDC_SetNextTx>
	AT91F_PDC_SetNextRx(pPDC, NULL, 0);
     468:	e3a01000 	mov	r1, #0
     46c:	e1a02001 	mov	r2, r1
     470:	e1a00004 	mov	r0, r4
     474:	ebffffa0 	bl	2fc <AT91F_PDC_SetNextRx>
	AT91F_PDC_SetTx(pPDC, NULL, 0);
     478:	e3a01000 	mov	r1, #0
     47c:	e1a02001 	mov	r2, r1
     480:	e1a00004 	mov	r0, r4
     484:	ebffffa5 	bl	320 <AT91F_PDC_SetTx>
	AT91F_PDC_SetRx(pPDC, NULL, 0);
     488:	e3a01000 	mov	r1, #0
     48c:	e1a00004 	mov	r0, r4
     490:	e1a02001 	mov	r2, r1
     494:	ebffff9e 	bl	314 <AT91F_PDC_SetRx>
//* \brief Enable receive
//*----------------------------------------------------------------------------
static inline void AT91F_PDC_EnableRx (
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
     498:	e3a03001 	mov	r3, #1
     49c:	e5843020 	str	r3, [r4, #32]
//* \brief Enable transmit
//*----------------------------------------------------------------------------
static inline void AT91F_PDC_EnableTx (
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
     4a0:	e28330ff 	add	r3, r3, #255	; 0xff
     4a4:	e5843020 	str	r3, [r4, #32]

    //* Enable the RX and TX PDC transfer requests
	AT91F_PDC_EnableRx(pPDC);
	AT91F_PDC_EnableTx(pPDC);
}
     4a8:	e8bd4010 	pop	{r4, lr}
     4ac:	e12fff1e 	bx	lr

000004b0 <AT91F_PDC_Close>:
//*----------------------------------------------------------------------------
//* \fn    AT91F_PDC_Close
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
void AT91F_PDC_Close(AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
{
     4b0:	e92d4010 	push	{r4, lr}
     4b4:	e1a04000 	mov	r4, r0
    //* Disable the RX and TX PDC transfer requests
	AT91F_PDC_DisableRx(pPDC);
     4b8:	ebffff9e 	bl	338 <AT91F_PDC_DisableRx>
	AT91F_PDC_DisableTx(pPDC);
     4bc:	e1a00004 	mov	r0, r4
     4c0:	ebffff99 	bl	32c <AT91F_PDC_DisableTx>

	//* Reset all Counter register Next buffer first
	AT91F_PDC_SetNextTx(pPDC, NULL, 0);
     4c4:	e3a01000 	mov	r1, #0
     4c8:	e1a00004 	mov	r0, r4
     4cc:	e1a02001 	mov	r2, r1
     4d0:	ebffff8c 	bl	308 <AT91F_PDC_SetNextTx>
	AT91F_PDC_SetNextRx(pPDC, NULL, 0);
     4d4:	e3a01000 	mov	r1, #0
     4d8:	e1a00004 	mov	r0, r4
     4dc:	e1a02001 	mov	r2, r1
     4e0:	ebffff85 	bl	2fc <AT91F_PDC_SetNextRx>
	AT91F_PDC_SetTx(pPDC, NULL, 0);
     4e4:	e3a01000 	mov	r1, #0
     4e8:	e1a00004 	mov	r0, r4
     4ec:	e1a02001 	mov	r2, r1
     4f0:	ebffff8a 	bl	320 <AT91F_PDC_SetTx>
	AT91F_PDC_SetRx(pPDC, NULL, 0);
     4f4:	e3a01000 	mov	r1, #0
     4f8:	e1a00004 	mov	r0, r4
     4fc:	e1a02001 	mov	r2, r1

}
     500:	e8bd4010 	pop	{r4, lr}

	//* Reset all Counter register Next buffer first
	AT91F_PDC_SetNextTx(pPDC, NULL, 0);
	AT91F_PDC_SetNextRx(pPDC, NULL, 0);
	AT91F_PDC_SetTx(pPDC, NULL, 0);
	AT91F_PDC_SetRx(pPDC, NULL, 0);
     504:	eaffff82 	b	314 <AT91F_PDC_SetRx>

00000508 <AT91F_PDC_SendFrame>:
	AT91PS_PDC pPDC,
	const unsigned char *pBuffer,
	unsigned int szBuffer,
	const unsigned char *pNextBuffer,
	unsigned int szNextBuffer )
{
     508:	e92d4038 	push	{r3, r4, r5, lr}
     50c:	e1a05003 	mov	r5, r3
//* \brief Test if the current transfer descriptor has been sent
//*----------------------------------------------------------------------------
static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	return !(pPDC->PDC_TCR);
     510:	e590300c 	ldr	r3, [r0, #12]
	if (AT91F_PDC_IsTxEmpty(pPDC)) {
     514:	e3530000 	cmp	r3, #0
	AT91PS_PDC pPDC,
	const unsigned char *pBuffer,
	unsigned int szBuffer,
	const unsigned char *pNextBuffer,
	unsigned int szNextBuffer )
{
     518:	e1a04000 	mov	r4, r0
	if (AT91F_PDC_IsTxEmpty(pPDC)) {
     51c:	1a000006 	bne	53c <AT91F_PDC_SendFrame+0x34>
		//* Buffer and next buffer can be initialized
		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
     520:	ebffff7e 	bl	320 <AT91F_PDC_SetTx>
		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
     524:	e1a00004 	mov	r0, r4
     528:	e1a01005 	mov	r1, r5
     52c:	e59d2010 	ldr	r2, [sp, #16]
     530:	ebffff74 	bl	308 <AT91F_PDC_SetNextTx>
		return 2;
     534:	e3a00002 	mov	r0, #2
     538:	ea000005 	b	554 <AT91F_PDC_SendFrame+0x4c>
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	return !(pPDC->PDC_TNCR);
     53c:	e590301c 	ldr	r3, [r0, #28]
	}
	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
     540:	e3530000 	cmp	r3, #0
		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
		return 1;
	}
	else {
		//* All buffer are in use...
		return 0;
     544:	13a00000 	movne	r0, #0
		//* Buffer and next buffer can be initialized
		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
		return 2;
	}
	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
     548:	1a000001 	bne	554 <AT91F_PDC_SendFrame+0x4c>
		//* Only one buffer can be initialized
		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
     54c:	ebffff6d 	bl	308 <AT91F_PDC_SetNextTx>
		return 1;
     550:	e3a00001 	mov	r0, #1
	}
	else {
		//* All buffer are in use...
		return 0;
	}
}
     554:	e8bd4038 	pop	{r3, r4, r5, lr}
     558:	e12fff1e 	bx	lr

0000055c <AT91F_PDC_ReceiveFrame>:
	AT91PS_PDC pPDC,
	unsigned char *pBuffer,
	unsigned int szBuffer,
	unsigned char *pNextBuffer,
	unsigned int szNextBuffer )
{
     55c:	e92d4038 	push	{r3, r4, r5, lr}
     560:	e1a05003 	mov	r5, r3
//* \brief Test if the current transfer descriptor has been filled
//*----------------------------------------------------------------------------
static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	return !(pPDC->PDC_RCR);
     564:	e5903004 	ldr	r3, [r0, #4]
	if (AT91F_PDC_IsRxEmpty(pPDC)) {
     568:	e3530000 	cmp	r3, #0
	AT91PS_PDC pPDC,
	unsigned char *pBuffer,
	unsigned int szBuffer,
	unsigned char *pNextBuffer,
	unsigned int szNextBuffer )
{
     56c:	e1a04000 	mov	r4, r0
	if (AT91F_PDC_IsRxEmpty(pPDC)) {
     570:	1a000006 	bne	590 <AT91F_PDC_ReceiveFrame+0x34>
		//* Buffer and next buffer can be initialized
		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
     574:	ebffff66 	bl	314 <AT91F_PDC_SetRx>
		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
     578:	e1a00004 	mov	r0, r4
     57c:	e1a01005 	mov	r1, r5
     580:	e59d2010 	ldr	r2, [sp, #16]
     584:	ebffff5c 	bl	2fc <AT91F_PDC_SetNextRx>
		return 2;
     588:	e3a00002 	mov	r0, #2
     58c:	ea000005 	b	5a8 <AT91F_PDC_ReceiveFrame+0x4c>
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
{
	return !(pPDC->PDC_RNCR);
     590:	e5903014 	ldr	r3, [r0, #20]
	}
	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
     594:	e3530000 	cmp	r3, #0
		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
		return 1;
	}
	else {
		//* All buffer are in use...
		return 0;
     598:	13a00000 	movne	r0, #0
		//* Buffer and next buffer can be initialized
		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
		return 2;
	}
	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
     59c:	1a000001 	bne	5a8 <AT91F_PDC_ReceiveFrame+0x4c>
		//* Only one buffer can be initialized
		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
     5a0:	ebffff55 	bl	2fc <AT91F_PDC_SetNextRx>
		return 1;
     5a4:	e3a00001 	mov	r0, #1
	}
	else {
		//* All buffer are in use...
		return 0;
	}
}
     5a8:	e8bd4038 	pop	{r3, r4, r5, lr}
     5ac:	e12fff1e 	bx	lr

000005b0 <AT91F_PMC_GetMasterClock>:
//*------------------------------------------------------------------------------
unsigned int AT91F_PMC_GetMasterClock (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
     5b0:	e92d4038 	push	{r3, r4, r5, lr}
     5b4:	e1a03000 	mov	r3, r0
	unsigned int reg = pPMC->PMC_MCKR;
     5b8:	e5933030 	ldr	r3, [r3, #48]	; 0x30
//*------------------------------------------------------------------------------
unsigned int AT91F_PMC_GetMasterClock (
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
     5bc:	e1a00001 	mov	r0, r1
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
     5c0:	e203401c 	and	r4, r3, #28
     5c4:	e3a01001 	mov	r1, #1
	unsigned int pllDivider, pllMultiplier;

	switch (reg & AT91C_PMC_CSS) {
     5c8:	e2033003 	and	r3, r3, #3
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
     5cc:	e1a04124 	lsr	r4, r4, #2
	unsigned int pllDivider, pllMultiplier;

	switch (reg & AT91C_PMC_CSS) {
     5d0:	e1530001 	cmp	r3, r1
	AT91PS_PMC pPMC, // \arg pointer to PMC controller
	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
	unsigned int slowClock)  // \arg slowClock in Hz
{
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
     5d4:	e1a04411 	lsl	r4, r1, r4
	unsigned int pllDivider, pllMultiplier;

	switch (reg & AT91C_PMC_CSS) {
     5d8:	0a000005 	beq	5f4 <AT91F_PMC_GetMasterClock+0x44>
		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
			return slowClock / prescaler;
     5dc:	31a00002 	movcc	r0, r2
{
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
	unsigned int pllDivider, pllMultiplier;

	switch (reg & AT91C_PMC_CSS) {
     5e0:	3a000010 	bcc	628 <AT91F_PMC_GetMasterClock+0x78>
     5e4:	e3530003 	cmp	r3, #3
			reg = pCKGR->CKGR_PLLR;
			pllDivider    = (reg  & AT91C_CKGR_DIV);
			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
	}
	return 0;
     5e8:	13a00000 	movne	r0, #0
{
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
	unsigned int pllDivider, pllMultiplier;

	switch (reg & AT91C_PMC_CSS) {
     5ec:	1a00000f 	bne	630 <AT91F_PMC_GetMasterClock+0x80>
     5f0:	ea000002 	b	600 <AT91F_PMC_GetMasterClock+0x50>
		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
			return slowClock / prescaler;
		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
     5f4:	e1a01002 	mov	r1, r2
     5f8:	ebffff51 	bl	344 <AT91F_CKGR_GetMainClock>
     5fc:	ea000009 	b	628 <AT91F_PMC_GetMasterClock+0x78>
		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
			reg = pCKGR->CKGR_PLLR;
     600:	e590500c 	ldr	r5, [r0, #12]
			pllDivider    = (reg  & AT91C_CKGR_DIV);
			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
     604:	e1a01002 	mov	r1, r2
     608:	ebffff4d 	bl	344 <AT91F_CKGR_GetMainClock>
			return slowClock / prescaler;
		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
			reg = pCKGR->CKGR_PLLR;
			pllDivider    = (reg  & AT91C_CKGR_DIV);
     60c:	e20510ff 	and	r1, r5, #255	; 0xff
			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
     610:	eb0003d0 	bl	1558 <__aeabi_uidiv>
		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
			reg = pCKGR->CKGR_PLLR;
			pllDivider    = (reg  & AT91C_CKGR_DIV);
			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
     614:	e59f301c 	ldr	r3, [pc, #28]	; 638 <AT91F_PMC_GetMasterClock+0x88>
     618:	e0053003 	and	r3, r5, r3
     61c:	e1a03823 	lsr	r3, r3, #16
     620:	e2833001 	add	r3, r3, #1
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
     624:	e0000093 	mul	r0, r3, r0
     628:	e1a01004 	mov	r1, r4
     62c:	eb0003c9 	bl	1558 <__aeabi_uidiv>
	}
	return 0;
}
     630:	e8bd4038 	pop	{r3, r4, r5, lr}
     634:	e12fff1e 	bx	lr
     638:	07ff0000 	.word	0x07ff0000

0000063c <AT91F_RTTReadValue>:
//*--------------------------------------------------------------------------------------
//* \fn     AT91F_RTT_ReadValue()
//* \brief  Read the RTT value
//*--------------------------------------------------------------------------------------
unsigned int AT91F_RTTReadValue(AT91PS_RTTC pRTTC)
{
     63c:	e24dd008 	sub	sp, sp, #8
        register volatile unsigned int val1,val2;
	do
	{
		val1 = pRTTC->RTTC_RTVR;
     640:	e5903008 	ldr	r3, [r0, #8]
     644:	e58d3004 	str	r3, [sp, #4]
		val2 = pRTTC->RTTC_RTVR;
     648:	e5903008 	ldr	r3, [r0, #8]
     64c:	e58d3000 	str	r3, [sp]
	}	
	while(val1 != val2);
     650:	e59d2004 	ldr	r2, [sp, #4]
     654:	e59d3000 	ldr	r3, [sp]
     658:	e1520003 	cmp	r2, r3
     65c:	1afffff7 	bne	640 <AT91F_RTTReadValue+0x4>
	return(val1);
     660:	e59d0004 	ldr	r0, [sp, #4]
}
     664:	e28dd008 	add	sp, sp, #8
     668:	e12fff1e 	bx	lr

0000066c <AT91F_SPI_Close>:
//* \brief Close SPI: disable IT disable transfert, close PDC
//*----------------------------------------------------------------------------
void AT91F_SPI_Close(AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
{
    //* Reset all the Chip Select register
    pSPI->SPI_CSR[0] = 0 ;
     66c:	e3a03000 	mov	r3, #0
//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Close
//* \brief Close SPI: disable IT disable transfert, close PDC
//*----------------------------------------------------------------------------
void AT91F_SPI_Close(AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
{
     670:	e92d4010 	push	{r4, lr}
    //* Reset all the Chip Select register
    pSPI->SPI_CSR[0] = 0 ;
     674:	e5803030 	str	r3, [r0, #48]	; 0x30
    pSPI->SPI_CSR[1] = 0 ;
     678:	e5803034 	str	r3, [r0, #52]	; 0x34
    pSPI->SPI_CSR[2] = 0 ;
     67c:	e5803038 	str	r3, [r0, #56]	; 0x38
    pSPI->SPI_CSR[3] = 0 ;
     680:	e580303c 	str	r3, [r0, #60]	; 0x3c

    //* Reset the SPI mode
    pSPI->SPI_MR = 0  ;
     684:	e5803004 	str	r3, [r0, #4]

    //* Disable all interrupts
    pSPI->SPI_IDR = 0xFFFFFFFF ;
     688:	e3e03000 	mvn	r3, #0
     68c:	e5803018 	str	r3, [r0, #24]
//*----------------------------------------------------------------------------
//* \fn    AT91F_SPI_Close
//* \brief Close SPI: disable IT disable transfert, close PDC
//*----------------------------------------------------------------------------
void AT91F_SPI_Close(AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
{
     690:	e1a04000 	mov	r4, r0

    //* Disable all interrupts
    pSPI->SPI_IDR = 0xFFFFFFFF ;

    //* Abort the Peripheral Data Transfers
    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
     694:	e2800c01 	add	r0, r0, #256	; 0x100
     698:	ebffff84 	bl	4b0 <AT91F_PDC_Close>

    //* Disable receiver and transmitter and stop any activity immediately
    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
     69c:	e3a03002 	mov	r3, #2
     6a0:	e5843000 	str	r3, [r4]
}
     6a4:	e8bd4010 	pop	{r4, lr}
     6a8:	e12fff1e 	bx	lr

000006ac <AT91F_ADC_CfgTimings>:
	AT91PS_ADC pADC, // pointer to a ADC controller
	unsigned int mck_clock, // in MHz 
	unsigned int adc_clock, // in MHz 
	unsigned int startup_time, // in us 
	unsigned int sample_and_hold_time)	// in ns  
{
     6ac:	e92d40f8 	push	{r3, r4, r5, r6, r7, lr}
     6b0:	e1a04000 	mov	r4, r0
	unsigned int prescal,startup,shtim;
	
	prescal = mck_clock/(2*adc_clock) - 1;
     6b4:	e1a00001 	mov	r0, r1
     6b8:	e1a01082 	lsl	r1, r2, #1
	startup = adc_clock*startup_time/8 - 1;
     6bc:	e0070392 	mul	r7, r2, r3
	AT91PS_ADC pADC, // pointer to a ADC controller
	unsigned int mck_clock, // in MHz 
	unsigned int adc_clock, // in MHz 
	unsigned int startup_time, // in us 
	unsigned int sample_and_hold_time)	// in ns  
{
     6c0:	e1a05002 	mov	r5, r2
	unsigned int prescal,startup,shtim;
	
	prescal = mck_clock/(2*adc_clock) - 1;
     6c4:	eb0003a3 	bl	1558 <__aeabi_uidiv>
     6c8:	e2406001 	sub	r6, r0, #1
	startup = adc_clock*startup_time/8 - 1;
	shtim = adc_clock*sample_and_hold_time/1000 - 1;
     6cc:	e59d0018 	ldr	r0, [sp, #24]
     6d0:	e3a01ffa 	mov	r1, #1000	; 0x3e8
     6d4:	e0000095 	mul	r0, r5, r0
     6d8:	eb00039e 	bl	1558 <__aeabi_uidiv>
	unsigned int sample_and_hold_time)	// in ns  
{
	unsigned int prescal,startup,shtim;
	
	prescal = mck_clock/(2*adc_clock) - 1;
	startup = adc_clock*startup_time/8 - 1;
     6dc:	e1a071a7 	lsr	r7, r7, #3
     6e0:	e2477001 	sub	r7, r7, #1
	shtim = adc_clock*sample_and_hold_time/1000 - 1;
	
	//* Write to the MR register
	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
     6e4:	e1a07807 	lsl	r7, r7, #16
     6e8:	e1a06406 	lsl	r6, r6, #8
{
	unsigned int prescal,startup,shtim;
	
	prescal = mck_clock/(2*adc_clock) - 1;
	startup = adc_clock*startup_time/8 - 1;
	shtim = adc_clock*sample_and_hold_time/1000 - 1;
     6ec:	e2403001 	sub	r3, r0, #1
	
	//* Write to the MR register
	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
     6f0:	e207781f 	and	r7, r7, #2031616	; 0x1f0000
     6f4:	e2066c3f 	and	r6, r6, #16128	; 0x3f00
     6f8:	e1a03c03 	lsl	r3, r3, #24
     6fc:	e1876006 	orr	r6, r7, r6
     700:	e203340f 	and	r3, r3, #251658240	; 0xf000000
     704:	e1866003 	orr	r6, r6, r3
     708:	e5846004 	str	r6, [r4, #4]
}
     70c:	e8bd40f8 	pop	{r3, r4, r5, r6, r7, lr}
     710:	e12fff1e 	bx	lr

00000714 <AT91F_SSC_SetBaudrate>:
        unsigned int mainClock, // \arg peripheral clock
        unsigned int speed)     // \arg SSC baudrate
{
        unsigned int baud_value;
        //* Define the baud rate divisor register
        if (speed == 0)
     714:	e3520000 	cmp	r2, #0
//*----------------------------------------------------------------------------
void AT91F_SSC_SetBaudrate (
        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
        unsigned int mainClock, // \arg peripheral clock
        unsigned int speed)     // \arg SSC baudrate
{
     718:	e92d4070 	push	{r4, r5, r6, lr}
     71c:	e1a04000 	mov	r4, r0
        unsigned int baud_value;
        //* Define the baud rate divisor register
        if (speed == 0)
           baud_value = 0;
     720:	01a00002 	moveq	r0, r2
        unsigned int mainClock, // \arg peripheral clock
        unsigned int speed)     // \arg SSC baudrate
{
        unsigned int baud_value;
        //* Define the baud rate divisor register
        if (speed == 0)
     724:	0a000010 	beq	76c <AT91F_SSC_SetBaudrate+0x58>
           baud_value = 0;
        else
        {
           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
     728:	e3a0500a 	mov	r5, #10
     72c:	e0000195 	mul	r0, r5, r1
     730:	e1a01082 	lsl	r1, r2, #1
     734:	eb000387 	bl	1558 <__aeabi_uidiv>
           if ((baud_value % 10) >= 5)
     738:	e1a01005 	mov	r1, r5
        //* Define the baud rate divisor register
        if (speed == 0)
           baud_value = 0;
        else
        {
           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
     73c:	e1a06000 	mov	r6, r0
           if ((baud_value % 10) >= 5)
     740:	eb0003c1 	bl	164c <__aeabi_uidivmod>
     744:	e3510004 	cmp	r1, #4
     748:	9a000004 	bls	760 <AT91F_SSC_SetBaudrate+0x4c>
                  baud_value = (baud_value / 10) + 1;
     74c:	e1a00006 	mov	r0, r6
     750:	e1a01005 	mov	r1, r5
     754:	eb00037f 	bl	1558 <__aeabi_uidiv>
     758:	e2800001 	add	r0, r0, #1
     75c:	ea000002 	b	76c <AT91F_SSC_SetBaudrate+0x58>
           else
                  baud_value /= 10;
     760:	e1a00006 	mov	r0, r6
     764:	e1a01005 	mov	r1, r5
     768:	eb00037a 	bl	1558 <__aeabi_uidiv>
        }

        pSSC->SSC_CMR = baud_value;
     76c:	e5840004 	str	r0, [r4, #4]
}
     770:	e8bd4070 	pop	{r4, r5, r6, lr}
     774:	e12fff1e 	bx	lr

00000778 <AT91F_SSC_Configure>:
             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
             unsigned int clock_rx,    // \arg Receiver Clock Parameters
             unsigned int mode_rx,     // \arg mode Register to be programmed
             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
             unsigned int mode_tx)     // \arg mode Register to be programmed
{
     778:	e92d41f0 	push	{r4, r5, r6, r7, r8, lr}
     77c:	e1a08003 	mov	r8, r3
    //* Disable interrupts
	pSSC->SSC_IDR = (unsigned int) -1;
     780:	e3e03000 	mvn	r3, #0
     784:	e5803048 	str	r3, [r0, #72]	; 0x48

    //* Reset receiver and transmitter
	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
     788:	e59f3030 	ldr	r3, [pc, #48]	; 7c0 <AT91F_SSC_Configure+0x48>
     78c:	e5803000 	str	r3, [r0]
             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
             unsigned int clock_rx,    // \arg Receiver Clock Parameters
             unsigned int mode_rx,     // \arg mode Register to be programmed
             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
             unsigned int mode_tx)     // \arg mode Register to be programmed
{
     790:	e1a04000 	mov	r4, r0
     794:	e28d6018 	add	r6, sp, #24
     798:	e89600c0 	ldm	r6, {r6, r7}
     79c:	e59d5020 	ldr	r5, [sp, #32]

    //* Reset receiver and transmitter
	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;

    //* Define the Clock Mode Register
	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
     7a0:	ebffffdb 	bl	714 <AT91F_SSC_SetBaudrate>

     //* Write the Transmit Frame Mode Register
	pSSC->SSC_TFMR =  mode_tx;

    //* Clear Transmit and Receive Counters
	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
     7a4:	e2840c01 	add	r0, r4, #256	; 0x100

    //* Define the Clock Mode Register
	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);

     //* Write the Receive Clock Mode Register
	pSSC->SSC_RCMR =  clock_rx;
     7a8:	e5848010 	str	r8, [r4, #16]

     //* Write the Transmit Clock Mode Register
	pSSC->SSC_TCMR =  clock_tx;
     7ac:	e5847018 	str	r7, [r4, #24]

     //* Write the Receive Frame Mode Register
	pSSC->SSC_RFMR =  mode_rx;
     7b0:	e5846014 	str	r6, [r4, #20]

     //* Write the Transmit Frame Mode Register
	pSSC->SSC_TFMR =  mode_tx;
     7b4:	e584501c 	str	r5, [r4, #28]

    //* Clear Transmit and Receive Counters
	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));


}
     7b8:	e8bd41f0 	pop	{r4, r5, r6, r7, r8, lr}

     //* Write the Transmit Frame Mode Register
	pSSC->SSC_TFMR =  mode_tx;

    //* Clear Transmit and Receive Counters
	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
     7bc:	eaffff20 	b	444 <AT91F_PDC_Open>
     7c0:	00008202 	.word	0x00008202

000007c4 <AT91F_US_Configure>:
	AT91PS_USART pUSART,     // \arg pointer to a USART controller
	unsigned int mainClock,  // \arg peripheral clock
	unsigned int mode ,      // \arg mode Register to be programmed
	unsigned int baudRate ,  // \arg baudrate to be programmed
	unsigned int timeguard ) // \arg timeguard to be programmed
{
     7c4:	e92d40f8 	push	{r3, r4, r5, r6, r7, lr}
     7c8:	e1a06002 	mov	r6, r2
    //* Disable interrupts
    pUSART->US_IDR = (unsigned int) -1;
     7cc:	e3e02000 	mvn	r2, #0
     7d0:	e580200c 	str	r2, [r0, #12]
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_US_Baudrate (
	const unsigned int main_clock, // \arg peripheral clock
	const unsigned int baud_rate)  // \arg UART baudrate
{
	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
     7d4:	e3a0500a 	mov	r5, #10

    //* Reset receiver and transmitter
    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
     7d8:	e28220ad 	add	r2, r2, #173	; 0xad
     7dc:	e5802000 	str	r2, [r0]
	AT91PS_USART pUSART,     // \arg pointer to a USART controller
	unsigned int mainClock,  // \arg peripheral clock
	unsigned int mode ,      // \arg mode Register to be programmed
	unsigned int baudRate ,  // \arg baudrate to be programmed
	unsigned int timeguard ) // \arg timeguard to be programmed
{
     7e0:	e1a04000 	mov	r4, r0
     7e4:	e0000195 	mul	r0, r5, r1
     7e8:	e1a01203 	lsl	r1, r3, #4
     7ec:	eb000359 	bl	1558 <__aeabi_uidiv>
	if ((baud_value % 10) >= 5)
     7f0:	e1a01005 	mov	r1, r5
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_US_Baudrate (
	const unsigned int main_clock, // \arg peripheral clock
	const unsigned int baud_rate)  // \arg UART baudrate
{
	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
     7f4:	e1a07000 	mov	r7, r0
	if ((baud_value % 10) >= 5)
     7f8:	eb000393 	bl	164c <__aeabi_uidivmod>
     7fc:	e3510004 	cmp	r1, #4
     800:	9a000004 	bls	818 <AT91F_US_Configure+0x54>
		baud_value = (baud_value / 10) + 1;
     804:	e1a00007 	mov	r0, r7
     808:	e1a01005 	mov	r1, r5
     80c:	eb000351 	bl	1558 <__aeabi_uidiv>
     810:	e2800001 	add	r0, r0, #1
     814:	ea000002 	b	824 <AT91F_US_Configure+0x60>
	else
		baud_value /= 10;
     818:	e1a00007 	mov	r0, r7
     81c:	e1a01005 	mov	r1, r5
     820:	eb00034c 	bl	1558 <__aeabi_uidiv>
static inline void AT91F_US_SetTimeguard (
	AT91PS_USART pUSART,    // \arg pointer to a USART controller
	unsigned int timeguard) // \arg timeguard value
{
	//* Write the Timeguard Register
	pUSART->US_TTGR = timeguard ;
     824:	e59d3018 	ldr	r3, [sp, #24]
	AT91PS_USART pUSART,    // \arg pointer to a USART controller
	unsigned int mainClock, // \arg peripheral clock
	unsigned int speed)     // \arg UART baudrate
{
	//* Define the baud rate divisor register
	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
     828:	e5840020 	str	r0, [r4, #32]
static inline void AT91F_US_SetTimeguard (
	AT91PS_USART pUSART,    // \arg pointer to a USART controller
	unsigned int timeguard) // \arg timeguard value
{
	//* Write the Timeguard Register
	pUSART->US_TTGR = timeguard ;
     82c:	e5843028 	str	r3, [r4, #40]	; 0x28

	//* Write the Timeguard Register
	AT91F_US_SetTimeguard(pUSART, timeguard);

    //* Clear Transmit and Receive Counters
    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
     830:	e2840c01 	add	r0, r4, #256	; 0x100
     834:	ebffff02 	bl	444 <AT91F_PDC_Open>

    //* Define the USART mode
    pUSART->US_MR = mode  ;
     838:	e5846004 	str	r6, [r4, #4]

}
     83c:	e8bd40f8 	pop	{r3, r4, r5, r6, r7, lr}
     840:	e12fff1e 	bx	lr

00000844 <AT91F_US_Close>:
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
void AT91F_US_Close(AT91PS_USART pUSART)     // \arg pointer to a USART controller
{
    //* Reset the baud rate divisor register
    pUSART->US_BRGR = 0 ;
     844:	e3a03000 	mov	r3, #0
//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Close
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
void AT91F_US_Close(AT91PS_USART pUSART)     // \arg pointer to a USART controller
{
     848:	e92d4010 	push	{r4, lr}
    //* Reset the baud rate divisor register
    pUSART->US_BRGR = 0 ;
     84c:	e5803020 	str	r3, [r0, #32]

    //* Reset the USART mode
    pUSART->US_MR = 0  ;
     850:	e5803004 	str	r3, [r0, #4]

    //* Reset the Timeguard Register
    pUSART->US_TTGR = 0;
     854:	e5803028 	str	r3, [r0, #40]	; 0x28

    //* Disable all interrupts
    pUSART->US_IDR = 0xFFFFFFFF ;
     858:	e3e03000 	mvn	r3, #0
     85c:	e580300c 	str	r3, [r0, #12]
//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Close
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
void AT91F_US_Close(AT91PS_USART pUSART)     // \arg pointer to a USART controller
{
     860:	e1a04000 	mov	r4, r0

    //* Disable all interrupts
    pUSART->US_IDR = 0xFFFFFFFF ;

    //* Abort the Peripheral Data Transfers
    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
     864:	e2800c01 	add	r0, r0, #256	; 0x100
     868:	ebffff10 	bl	4b0 <AT91F_PDC_Close>

    //* Disable receiver and transmitter and stop any activity immediately
    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
     86c:	e3a030ac 	mov	r3, #172	; 0xac
     870:	e5843000 	str	r3, [r4]
}
     874:	e8bd4010 	pop	{r4, lr}
     878:	e12fff1e 	bx	lr

0000087c <udp_ep0_send_data>:
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUPv4);
}

/* Send Data through the control endpoint */
static void __dfufunc udp_ep0_send_data(const char *pData, u_int32_t length)
{
     87c:	e92d0033 	push	{r0, r1, r4, r5}
	AT91_REG csr;

	DEBUGE("send_data: %u bytes ", length);

	do {
		cpt = MIN(length, 8);
     880:	e3510008 	cmp	r1, #8
     884:	31a02001 	movcc	r2, r1
     888:	23a02008 	movcs	r2, #8
     88c:	e1a0c002 	mov	ip, r2
		length -= cpt;

		while (cpt--)
     890:	e1a04000 	mov	r4, r0
     894:	ea000001 	b	8a0 <udp_ep0_send_data+0x24>
			pUdp->UDP_FDR[0] = *pData++;
     898:	e4d45001 	ldrb	r5, [r4], #1
     89c:	e50350af 	str	r5, [r3, #-175]	; 0xffffff51

	do {
		cpt = MIN(length, 8);
		length -= cpt;

		while (cpt--)
     8a0:	e24cc001 	sub	ip, ip, #1
     8a4:	e37c0001 	cmn	ip, #1
     8a8:	e59f30a4 	ldr	r3, [pc, #164]	; 954 <udp_ep0_send_data+0xd8>
     8ac:	1afffff9 	bne	898 <udp_ep0_send_data+0x1c>
			pUdp->UDP_FDR[0] = *pData++;

		if (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) {
     8b0:	e513c0cf 	ldr	ip, [r3, #-207]	; 0xffffff31
     8b4:	e31c0001 	tst	ip, #1

	do {
		cpt = MIN(length, 8);
		length -= cpt;

		while (cpt--)
     8b8:	e0800002 	add	r0, r0, r2
			pUdp->UDP_FDR[0] = *pData++;

		if (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) {
     8bc:	0a000006 	beq	8dc <udp_ep0_send_data+0x60>
			pUdp->UDP_CSR[0] &= ~(AT91C_UDP_TXCOMP);
     8c0:	e513c0cf 	ldr	ip, [r3, #-207]	; 0xffffff31
     8c4:	e3ccc001 	bic	ip, ip, #1
     8c8:	e503c0cf 	str	ip, [r3, #-207]	; 0xffffff31
			while (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) ;
     8cc:	e59f3080 	ldr	r3, [pc, #128]	; 954 <udp_ep0_send_data+0xd8>
     8d0:	e51330cf 	ldr	r3, [r3, #-207]	; 0xffffff31
     8d4:	e3130001 	tst	r3, #1
     8d8:	1afffffb 	bne	8cc <udp_ep0_send_data+0x50>
		}

		pUdp->UDP_CSR[0] |= AT91C_UDP_TXPKTRDY;
     8dc:	e59f3070 	ldr	r3, [pc, #112]	; 954 <udp_ep0_send_data+0xd8>
     8e0:	e513c0cf 	ldr	ip, [r3, #-207]	; 0xffffff31
     8e4:	e38cc010 	orr	ip, ip, #16
     8e8:	e503c0cf 	str	ip, [r3, #-207]	; 0xffffff31
		do {
			csr = pUdp->UDP_CSR[0];
     8ec:	e59f3060 	ldr	r3, [pc, #96]	; 954 <udp_ep0_send_data+0xd8>
     8f0:	e513c0cf 	ldr	ip, [r3, #-207]	; 0xffffff31
     8f4:	e58dc004 	str	ip, [sp, #4]

			/* Data IN stage has been stopped by a status OUT */
			if (csr & AT91C_UDP_RX_DATA_BK0) {
     8f8:	e59dc004 	ldr	ip, [sp, #4]
     8fc:	e31c0002 	tst	ip, #2
				pUdp->UDP_CSR[0] &= ~(AT91C_UDP_RX_DATA_BK0);
     900:	151320cf 	ldrne	r2, [r3, #-207]	; 0xffffff31
     904:	13c22002 	bicne	r2, r2, #2
     908:	150320cf 	strne	r2, [r3, #-207]	; 0xffffff31
				DEBUGE("stopped by status out ");
				return;
     90c:	1a00000e 	bne	94c <udp_ep0_send_data+0xd0>
			}
		} while (!(csr & AT91C_UDP_TXCOMP));
     910:	e59dc004 	ldr	ip, [sp, #4]
     914:	e31c0001 	tst	ip, #1
     918:	0afffff3 	beq	8ec <udp_ep0_send_data+0x70>

	} while (length);
     91c:	e0511002 	subs	r1, r1, r2
     920:	1affffd6 	bne	880 <udp_ep0_send_data+0x4>

	if (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) {
     924:	e51320cf 	ldr	r2, [r3, #-207]	; 0xffffff31
     928:	e3120001 	tst	r2, #1
     92c:	0a000006 	beq	94c <udp_ep0_send_data+0xd0>
		pUdp->UDP_CSR[0] &= ~(AT91C_UDP_TXCOMP);
     930:	e51320cf 	ldr	r2, [r3, #-207]	; 0xffffff31
     934:	e3c22001 	bic	r2, r2, #1
     938:	e50320cf 	str	r2, [r3, #-207]	; 0xffffff31
		while (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) ;
     93c:	e59f3010 	ldr	r3, [pc, #16]	; 954 <udp_ep0_send_data+0xd8>
     940:	e51330cf 	ldr	r3, [r3, #-207]	; 0xffffff31
     944:	e3130001 	tst	r3, #1
     948:	1afffffb 	bne	93c <udp_ep0_send_data+0xc0>
	}
}
     94c:	e8bd003c 	pop	{r2, r3, r4, r5}
     950:	e12fff1e 	bx	lr
     954:	fffb00ff 	.word	0xfffb00ff

00000958 <udp_ep0_send_zlp>:

/* Send zero length packet through the control endpoint */
static void __dfufunc udp_ep0_send_zlp(void)
{
	AT91PS_UDP pUdp = AT91C_BASE_UDP;
	pUdp->UDP_CSR[0] |= AT91C_UDP_TXPKTRDY;
     958:	e59f3038 	ldr	r3, [pc, #56]	; 998 <udp_ep0_send_zlp+0x40>
     95c:	e51320cf 	ldr	r2, [r3, #-207]	; 0xffffff31
     960:	e3822010 	orr	r2, r2, #16
     964:	e50320cf 	str	r2, [r3, #-207]	; 0xffffff31
	while (!(pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP)) ;
     968:	e51310cf 	ldr	r1, [r3, #-207]	; 0xffffff31
     96c:	e3110001 	tst	r1, #1
     970:	e59f2020 	ldr	r2, [pc, #32]	; 998 <udp_ep0_send_zlp+0x40>
     974:	0afffffb 	beq	968 <udp_ep0_send_zlp+0x10>
	pUdp->UDP_CSR[0] &= ~(AT91C_UDP_TXCOMP);
     978:	e51230cf 	ldr	r3, [r2, #-207]	; 0xffffff31
     97c:	e3c33001 	bic	r3, r3, #1
     980:	e50230cf 	str	r3, [r2, #-207]	; 0xffffff31
	while (pUdp->UDP_CSR[0] & AT91C_UDP_TXCOMP) ;
     984:	e59f300c 	ldr	r3, [pc, #12]	; 998 <udp_ep0_send_zlp+0x40>
     988:	e51330cf 	ldr	r3, [r3, #-207]	; 0xffffff31
     98c:	e3130001 	tst	r3, #1
     990:	1afffffb 	bne	984 <udp_ep0_send_zlp+0x2c>
}
     994:	e12fff1e 	bx	lr
     998:	fffb00ff 	.word	0xfffb00ff

0000099c <udp_ep0_send_stall>:

/* Stall the control endpoint */
static void __dfufunc udp_ep0_send_stall(void)
{
	AT91PS_UDP pUdp = AT91C_BASE_UDP;
	pUdp->UDP_CSR[0] |= AT91C_UDP_FORCESTALL;
     99c:	e59f3038 	ldr	r3, [pc, #56]	; 9dc <udp_ep0_send_stall+0x40>
     9a0:	e51320cf 	ldr	r2, [r3, #-207]	; 0xffffff31
     9a4:	e3822020 	orr	r2, r2, #32
     9a8:	e50320cf 	str	r2, [r3, #-207]	; 0xffffff31
	while (!(pUdp->UDP_CSR[0] & AT91C_UDP_ISOERROR)) ;
     9ac:	e51310cf 	ldr	r1, [r3, #-207]	; 0xffffff31
     9b0:	e3110008 	tst	r1, #8
     9b4:	e59f2020 	ldr	r2, [pc, #32]	; 9dc <udp_ep0_send_stall+0x40>
     9b8:	0afffffb 	beq	9ac <udp_ep0_send_stall+0x10>
	pUdp->UDP_CSR[0] &= ~(AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR);
     9bc:	e51230cf 	ldr	r3, [r2, #-207]	; 0xffffff31
     9c0:	e3c33028 	bic	r3, r3, #40	; 0x28
     9c4:	e50230cf 	str	r3, [r2, #-207]	; 0xffffff31
	while (pUdp->UDP_CSR[0] & (AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR)) ;
     9c8:	e59f300c 	ldr	r3, [pc, #12]	; 9dc <udp_ep0_send_stall+0x40>
     9cc:	e51330cf 	ldr	r3, [r3, #-207]	; 0xffffff31
     9d0:	e3130028 	tst	r3, #40	; 0x28
     9d4:	1afffffb 	bne	9c8 <udp_ep0_send_stall+0x2c>
}
     9d8:	e12fff1e 	bx	lr
     9dc:	fffb00ff 	.word	0xfffb00ff

000009e0 <handle_getstate>:

	udp_ep0_send_data((char *)&dstat, sizeof(dstat));
}

static void __dfufunc handle_getstate(void)
{
     9e0:	e92d4007 	push	{r0, r1, r2, lr}
	u_int8_t u8 = dfu_state;
     9e4:	e59f3018 	ldr	r3, [pc, #24]	; a04 <handle_getstate+0x24>
     9e8:	e5933000 	ldr	r3, [r3]
     9ec:	e28d0008 	add	r0, sp, #8
     9f0:	e5603001 	strb	r3, [r0, #-1]!
	DEBUGE("getstate ");

	udp_ep0_send_data((char *)&u8, sizeof(u8));
     9f4:	e3a01001 	mov	r1, #1
     9f8:	ebffff9f 	bl	87c <udp_ep0_send_data>
}
     9fc:	e8bd400e 	pop	{r1, r2, r3, lr}
     a00:	e12fff1e 	bx	lr
     a04:	00200020 	.word	0x00200020

00000a08 <handle_upload.clone.0>:

#define AT91C_IFLASH_END ((u_int8_t *)AT91C_IFLASH + AT91C_IFLASH_SIZE)
static __dfufunc int handle_upload(u_int16_t val, u_int16_t len)
{
	DEBUGE("upload ");
	if (len > AT91C_IFLASH_PAGE_SIZE) {
     a08:	e3500c01 	cmp	r0, #256	; 0x100

	return RET_ZLP;
}

#define AT91C_IFLASH_END ((u_int8_t *)AT91C_IFLASH + AT91C_IFLASH_SIZE)
static __dfufunc int handle_upload(u_int16_t val, u_int16_t len)
     a0c:	e92d4070 	push	{r4, r5, r6, lr}
     a10:	e1a04000 	mov	r4, r0
{
	DEBUGE("upload ");
	if (len > AT91C_IFLASH_PAGE_SIZE) {
     a14:	9a000007 	bls	a38 <handle_upload.clone.0+0x30>
		/* Too big */
		dfu_state = DFU_STATE_dfuERROR;
     a18:	e59f3054 	ldr	r3, [pc, #84]	; a74 <handle_upload.clone.0+0x6c>
     a1c:	e3a0200a 	mov	r2, #10
     a20:	e5832000 	str	r2, [r3]
		dfu_status = DFU_STATUS_errADDRESS;
     a24:	e3a02008 	mov	r2, #8
     a28:	e5c32004 	strb	r2, [r3, #4]
		udp_ep0_send_stall();
     a2c:	ebffffda 	bl	99c <udp_ep0_send_stall>
		return -EINVAL;
     a30:	e3e00015 	mvn	r0, #21
     a34:	ea00000c 	b	a6c <handle_upload.clone.0+0x64>
	}

	if (ptr + len > AT91C_IFLASH_END)
     a38:	e59f6038 	ldr	r6, [pc, #56]	; a78 <handle_upload.clone.0+0x70>
     a3c:	e5965000 	ldr	r5, [r6]
     a40:	e0853000 	add	r3, r5, r0
     a44:	e3530812 	cmp	r3, #1179648	; 0x120000
		len = AT91C_IFLASH_END - (u_int8_t *)ptr;
     a48:	82654000 	rsbhi	r4, r5, #0
     a4c:	81a04804 	lslhi	r4, r4, #16
     a50:	81a04824 	lsrhi	r4, r4, #16

	udp_ep0_send_data((char *)ptr, len);
     a54:	e1a00005 	mov	r0, r5
     a58:	e1a01004 	mov	r1, r4
	ptr+= len;
     a5c:	e0855004 	add	r5, r5, r4
	}

	if (ptr + len > AT91C_IFLASH_END)
		len = AT91C_IFLASH_END - (u_int8_t *)ptr;

	udp_ep0_send_data((char *)ptr, len);
     a60:	ebffff85 	bl	87c <udp_ep0_send_data>
	ptr+= len;
     a64:	e5865000 	str	r5, [r6]

	return len;
     a68:	e1a00004 	mov	r0, r4
}
     a6c:	e8bd4070 	pop	{r4, r5, r6, lr}
     a70:	e12fff1e 	bx	lr
     a74:	00200020 	.word	0x00200020
     a78:	00201adc 	.word	0x00201adc

00000a7c <handle_dnload.clone.1>:
__dfudata u_int32_t dfu_state = DFU_STATE_appIDLE;
static u_int32_t pagebuf32[AT91C_IFLASH_PAGE_SIZE/4];

static int __dfufunc handle_dnload(u_int16_t val, u_int16_t len)
{
	volatile u_int32_t *p = (volatile u_int32_t *)ptr;
     a7c:	e59f3134 	ldr	r3, [pc, #308]	; bb8 <handle_dnload.clone.1+0x13c>
	u_int8_t *pagebuf = (u_int8_t *) pagebuf32;
	int i;

	DEBUGE("download ");

	if (len > AT91C_IFLASH_PAGE_SIZE) {
     a80:	e3500c01 	cmp	r0, #256	; 0x100
static u_int8_t *ptr = (u_int8_t *) AT91C_IFLASH + SAM7DFU_SIZE;
static __dfudata u_int8_t dfu_status;
__dfudata u_int32_t dfu_state = DFU_STATE_appIDLE;
static u_int32_t pagebuf32[AT91C_IFLASH_PAGE_SIZE/4];

static int __dfufunc handle_dnload(u_int16_t val, u_int16_t len)
     a84:	e92d41f3 	push	{r0, r1, r4, r5, r6, r7, r8, lr}
{
	volatile u_int32_t *p = (volatile u_int32_t *)ptr;
     a88:	e5934000 	ldr	r4, [r3]
	u_int8_t *pagebuf = (u_int8_t *) pagebuf32;
	int i;

	DEBUGE("download ");

	if (len > AT91C_IFLASH_PAGE_SIZE) {
     a8c:	8a00000d 	bhi	ac8 <handle_dnload.clone.1+0x4c>
		DEBUGP("length exceeds flash page size ");
	    	dfu_state = DFU_STATE_dfuERROR;
		dfu_status = DFU_STATUS_errADDRESS;
		return RET_STALL;
	}
	if (len & 0x3) {
     a90:	e2103003 	ands	r3, r0, #3
     a94:	1a00000b 	bne	ac8 <handle_dnload.clone.1+0x4c>
		DEBUGP("not four-byte-aligned length ");
		dfu_state = DFU_STATE_dfuERROR;
		dfu_status = DFU_STATUS_errADDRESS;
		return RET_STALL;
	}
	if (len == 0) {
     a98:	e3500000 	cmp	r0, #0
     a9c:	1a000005 	bne	ab8 <handle_dnload.clone.1+0x3c>
		DEBUGP("zero-size write -> MANIFEST_SYNC ");
		flash_page(p);
     aa0:	e1a00004 	mov	r0, r4
     aa4:	eb00028f 	bl	14e8 <flash_page>
		dfu_state = DFU_STATE_dfuMANIFEST_SYNC;
     aa8:	e59f310c 	ldr	r3, [pc, #268]	; bbc <handle_dnload.clone.1+0x140>
     aac:	e3a02006 	mov	r2, #6
     ab0:	e5832000 	str	r2, [r3]
     ab4:	ea00003c 	b	bac <handle_dnload.clone.1+0x130>
		return RET_ZLP;
	}
	if (ptr + len >= (u_int8_t *) AT91C_IFLASH + AT91C_IFLASH_SIZE - ENVIRONMENT_SIZE ) {
     ab8:	e59f2100 	ldr	r2, [pc, #256]	; bc0 <handle_dnload.clone.1+0x144>
     abc:	e0841000 	add	r1, r4, r0
     ac0:	e1510002 	cmp	r1, r2
     ac4:	9a000006 	bls	ae4 <handle_dnload.clone.1+0x68>
		DEBUGP("end of write exceeds flash end ");
		dfu_state = DFU_STATE_dfuERROR;
     ac8:	e59f30ec 	ldr	r3, [pc, #236]	; bbc <handle_dnload.clone.1+0x140>
     acc:	e3a0200a 	mov	r2, #10
     ad0:	e5832000 	str	r2, [r3]
		dfu_status = DFU_STATUS_errADDRESS;
     ad4:	e3a02008 	mov	r2, #8
     ad8:	e5c32004 	strb	r2, [r3, #4]
		return RET_STALL;
     adc:	e3a00002 	mov	r0, #2
     ae0:	ea000032 	b	bb0 <handle_dnload.clone.1+0x134>
static u_int32_t pagebuf32[AT91C_IFLASH_PAGE_SIZE/4];

static int __dfufunc handle_dnload(u_int16_t val, u_int16_t len)
{
	volatile u_int32_t *p = (volatile u_int32_t *)ptr;
	u_int8_t *pagebuf = (u_int8_t *) pagebuf32;
     ae4:	e59f10d8 	ldr	r1, [pc, #216]	; bc4 <handle_dnload.clone.1+0x148>

	do {
		/* FIXME: do we need to check whether we've been interrupted
		 * by a RX SETUP stage? */
		do {
			csr = pUdp->UDP_CSR[0];
     ae8:	e59f20d8 	ldr	r2, [pc, #216]	; bc8 <handle_dnload.clone.1+0x14c>
     aec:	e512c0cf 	ldr	ip, [r2, #-207]	; 0xffffff31
     af0:	e58dc004 	str	ip, [sp, #4]
			DEBUGR("CSR=%08x ", csr);
		} while (!(csr & AT91C_UDP_RX_DATA_BK0)) ;
     af4:	e59dc004 	ldr	ip, [sp, #4]
     af8:	e31c0002 	tst	ip, #2
     afc:	0afffff9 	beq	ae8 <handle_dnload.clone.1+0x6c>
	
		num_rcv = pUdp->UDP_CSR[0] >> 16;
     b00:	e51250cf 	ldr	r5, [r2, #-207]	; 0xffffff31
     b04:	e1a05825 	lsr	r5, r5, #16

		/* make sure we don't read more than requested */
		if (num_rcv_total + num_rcv > len)
     b08:	e0832005 	add	r2, r3, r5
     b0c:	e1520000 	cmp	r2, r0
			num_rcv = num_rcv_total - len;
     b10:	80605003 	rsbhi	r5, r0, r3
     b14:	81a05805 	lslhi	r5, r5, #16
     b18:	81a05825 	lsrhi	r5, r5, #16
static u_int32_t pagebuf32[AT91C_IFLASH_PAGE_SIZE/4];

static int __dfufunc handle_dnload(u_int16_t val, u_int16_t len)
{
	volatile u_int32_t *p = (volatile u_int32_t *)ptr;
	u_int8_t *pagebuf = (u_int8_t *) pagebuf32;
     b1c:	e1a06001 	mov	r6, r1
		/* make sure we don't read more than requested */
		if (num_rcv_total + num_rcv > len)
			num_rcv = num_rcv_total - len;

		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
     b20:	e3a02000 	mov	r2, #0
     b24:	ea000004 	b	b3c <handle_dnload.clone.1+0xc0>
			*data++ = pUdp->UDP_FDR[0];
     b28:	e51cc0af 	ldr	ip, [ip, #-175]	; 0xffffff51
		/* make sure we don't read more than requested */
		if (num_rcv_total + num_rcv > len)
			num_rcv = num_rcv_total - len;

		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
     b2c:	e2822001 	add	r2, r2, #1
     b30:	e1a02802 	lsl	r2, r2, #16
			*data++ = pUdp->UDP_FDR[0];
     b34:	e4c6c001 	strb	ip, [r6], #1
		/* make sure we don't read more than requested */
		if (num_rcv_total + num_rcv > len)
			num_rcv = num_rcv_total - len;

		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
     b38:	e1a02822 	lsr	r2, r2, #16
     b3c:	e1520005 	cmp	r2, r5
     b40:	e59fc080 	ldr	ip, [pc, #128]	; bc8 <handle_dnload.clone.1+0x14c>
     b44:	1afffff7 	bne	b28 <handle_dnload.clone.1+0xac>
			*data++ = pUdp->UDP_FDR[0];
		pUdp->UDP_CSR[0] &= ~(AT91C_UDP_RX_DATA_BK0);
     b48:	e51c50cf 	ldr	r5, [ip, #-207]	; 0xffffff31

		num_rcv_total += num_rcv;

		/* we need to continue to pull data until we either receive 
		 * a packet < endpoint size or == 0 */
	} while (num_rcv == 8 && num_rcv_total < len);
     b4c:	e3520008 	cmp	r2, #8
			num_rcv = num_rcv_total - len;

		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
			*data++ = pUdp->UDP_FDR[0];
		pUdp->UDP_CSR[0] &= ~(AT91C_UDP_RX_DATA_BK0);
     b50:	e3c55002 	bic	r5, r5, #2
		/* make sure we don't read more than requested */
		if (num_rcv_total + num_rcv > len)
			num_rcv = num_rcv_total - len;

		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
     b54:	e0811002 	add	r1, r1, r2
			*data++ = pUdp->UDP_FDR[0];
		pUdp->UDP_CSR[0] &= ~(AT91C_UDP_RX_DATA_BK0);
     b58:	e50c50cf 	str	r5, [ip, #-207]	; 0xffffff31

		num_rcv_total += num_rcv;

		/* we need to continue to pull data until we either receive 
		 * a packet < endpoint size or == 0 */
	} while (num_rcv == 8 && num_rcv_total < len);
     b5c:	1a000002 	bne	b6c <handle_dnload.clone.1+0xf0>
		DEBUGR("num_rcv = %u ", num_rcv);
		for (i = 0; i < num_rcv; i++)
			*data++ = pUdp->UDP_FDR[0];
		pUdp->UDP_CSR[0] &= ~(AT91C_UDP_RX_DATA_BK0);

		num_rcv_total += num_rcv;
     b60:	e2833008 	add	r3, r3, #8

		/* we need to continue to pull data until we either receive 
		 * a packet < endpoint size or == 0 */
	} while (num_rcv == 8 && num_rcv_total < len);
     b64:	e1530000 	cmp	r3, r0
     b68:	3affffde 	bcc	ae8 <handle_dnload.clone.1+0x6c>

	/* we can only access the write buffer with correctly aligned
	 * 32bit writes ! */
#ifndef DEBUG_DFU_NOFLASH
	DEBUGP("copying ");
	for (i = 0; i < len/4; i++) {
     b6c:	e1a07120 	lsr	r7, r0, #2
     b70:	e59f8054 	ldr	r8, [pc, #84]	; bcc <handle_dnload.clone.1+0x150>
     b74:	e1a05004 	mov	r5, r4
     b78:	e3a06000 	mov	r6, #0
     b7c:	ea000005 	b	b98 <handle_dnload.clone.1+0x11c>
		*p++ = pagebuf32[i];
     b80:	e5b83004 	ldr	r3, [r8, #4]!
     b84:	e4853004 	str	r3, [r5], #4
		/* If we have filled a page buffer, flash it */
		if (((unsigned long)p % AT91C_IFLASH_PAGE_SIZE) == 0) {
     b88:	e31500ff 	tst	r5, #255	; 0xff
			DEBUGP("page_full  ");
			flash_page(p-1);
     b8c:	02450004 	subeq	r0, r5, #4
     b90:	0b000254 	bleq	14e8 <flash_page>

	/* we can only access the write buffer with correctly aligned
	 * 32bit writes ! */
#ifndef DEBUG_DFU_NOFLASH
	DEBUGP("copying ");
	for (i = 0; i < len/4; i++) {
     b94:	e2866001 	add	r6, r6, #1
     b98:	e1560007 	cmp	r6, r7
     b9c:	bafffff7 	blt	b80 <handle_dnload.clone.1+0x104>
		if (((unsigned long)p % AT91C_IFLASH_PAGE_SIZE) == 0) {
			DEBUGP("page_full  ");
			flash_page(p-1);
		}
	}
	ptr = (u_int8_t *) p;
     ba0:	e59f3010 	ldr	r3, [pc, #16]	; bb8 <handle_dnload.clone.1+0x13c>
     ba4:	e0844107 	add	r4, r4, r7, lsl #2
     ba8:	e5834000 	str	r4, [r3]
#endif

	return RET_ZLP;
     bac:	e3a00001 	mov	r0, #1
}
     bb0:	e8bd41fc 	pop	{r2, r3, r4, r5, r6, r7, r8, lr}
     bb4:	e12fff1e 	bx	lr
     bb8:	00201adc 	.word	0x00201adc
     bbc:	00200020 	.word	0x00200020
     bc0:	0011feff 	.word	0x0011feff
     bc4:	00201ae4 	.word	0x00201ae4
     bc8:	fffb00ff 	.word	0xfffb00ff
     bcc:	00201ae0 	.word	0x00201ae0

00000bd0 <handle_getstatus>:
//* \brief Return MC EFC Status
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_MC_EFC_GetStatus(
	AT91PS_MC pMC) // pointer to a MC controller
{
	return pMC->MC_FSR;
     bd0:	e3e03000 	mvn	r3, #0

	return len;
}

static __dfufunc void handle_getstatus(void)
{
     bd4:	e92d4007 	push	{r0, r1, r2, lr}
     bd8:	e5132097 	ldr	r2, [r3, #-151]	; 0xffffff69
	struct dfu_status dstat;
	u_int32_t fsr = AT91F_MC_EFC_GetStatus(AT91C_BASE_MC);

	DEBUGE("getstatus(fsr=0x%08x) ", fsr);

	switch (dfu_state) {
     bdc:	e59f308c 	ldr	r3, [pc, #140]	; c70 <handle_getstatus+0xa0>
     be0:	e5931000 	ldr	r1, [r3]
     be4:	e3510003 	cmp	r1, #3
     be8:	3a000014 	bcc	c40 <handle_getstatus+0x70>
     bec:	e3510004 	cmp	r1, #4
     bf0:	9a000002 	bls	c00 <handle_getstatus+0x30>
     bf4:	e3510006 	cmp	r1, #6
     bf8:	1a000010 	bne	c40 <handle_getstatus+0x70>
     bfc:	ea00000d 	b	c38 <handle_getstatus+0x68>
	case DFU_STATE_dfuDNLOAD_SYNC:
	case DFU_STATE_dfuDNBUSY:
		if (fsr & AT91C_MC_PROGE) {
     c00:	e3120008 	tst	r2, #8
			DEBUGE("errPROG ");
			dfu_status = DFU_STATUS_errPROG;
     c04:	13a02006 	movne	r2, #6
     c08:	15c32004 	strbne	r2, [r3, #4]
			dfu_state = DFU_STATE_dfuERROR;
     c0c:	12822004 	addne	r2, r2, #4
	DEBUGE("getstatus(fsr=0x%08x) ", fsr);

	switch (dfu_state) {
	case DFU_STATE_dfuDNLOAD_SYNC:
	case DFU_STATE_dfuDNBUSY:
		if (fsr & AT91C_MC_PROGE) {
     c10:	1a000009 	bne	c3c <handle_getstatus+0x6c>
			DEBUGE("errPROG ");
			dfu_status = DFU_STATUS_errPROG;
			dfu_state = DFU_STATE_dfuERROR;
		} else if (fsr & AT91C_MC_LOCKE) {
     c14:	e3120004 	tst	r2, #4
			DEBUGE("errWRITE ");
			dfu_status = DFU_STATUS_errWRITE;
     c18:	13a02003 	movne	r2, #3
     c1c:	15c32004 	strbne	r2, [r3, #4]
			dfu_state = DFU_STATE_dfuERROR;
     c20:	12822007 	addne	r2, r2, #7
	case DFU_STATE_dfuDNBUSY:
		if (fsr & AT91C_MC_PROGE) {
			DEBUGE("errPROG ");
			dfu_status = DFU_STATUS_errPROG;
			dfu_state = DFU_STATE_dfuERROR;
		} else if (fsr & AT91C_MC_LOCKE) {
     c24:	1a000004 	bne	c3c <handle_getstatus+0x6c>
			DEBUGE("errWRITE ");
			dfu_status = DFU_STATUS_errWRITE;
			dfu_state = DFU_STATE_dfuERROR;
		} else if (fsr & AT91C_MC_FRDY) {
     c28:	e3120001 	tst	r2, #1
			DEBUGE("DNLOAD_IDLE ");
			dfu_state = DFU_STATE_dfuDNLOAD_IDLE;
     c2c:	13a02005 	movne	r2, #5
		} else {
			DEBUGE("DNBUSY ");
			dfu_state = DFU_STATE_dfuDNBUSY;
     c30:	03a02004 	moveq	r2, #4
     c34:	ea000000 	b	c3c <handle_getstatus+0x6c>
		}
		break;
	case DFU_STATE_dfuMANIFEST_SYNC:
		dfu_state = DFU_STATE_dfuMANIFEST;
     c38:	e3a02007 	mov	r2, #7
     c3c:	e5832000 	str	r2, [r3]
		break;
	}

	/* send status response */
	dstat.bStatus = dfu_status;
     c40:	e59f3028 	ldr	r3, [pc, #40]	; c70 <handle_getstatus+0xa0>
     c44:	e5d32004 	ldrb	r2, [r3, #4]
	dstat.bState = dfu_state;
     c48:	e5933000 	ldr	r3, [r3]
	dstat.iString = 0;
	/* FIXME: set dstat.bwPollTimeout */

	udp_ep0_send_data((char *)&dstat, sizeof(dstat));
     c4c:	e1a0000d 	mov	r0, sp
		break;
	}

	/* send status response */
	dstat.bStatus = dfu_status;
	dstat.bState = dfu_state;
     c50:	e5cd3004 	strb	r3, [sp, #4]
	dstat.iString = 0;
	/* FIXME: set dstat.bwPollTimeout */

	udp_ep0_send_data((char *)&dstat, sizeof(dstat));
     c54:	e3a01006 	mov	r1, #6
	}

	/* send status response */
	dstat.bStatus = dfu_status;
	dstat.bState = dfu_state;
	dstat.iString = 0;
     c58:	e3a03000 	mov	r3, #0
		dfu_state = DFU_STATE_dfuMANIFEST;
		break;
	}

	/* send status response */
	dstat.bStatus = dfu_status;
     c5c:	e5cd2000 	strb	r2, [sp]
	dstat.bState = dfu_state;
	dstat.iString = 0;
     c60:	e5cd3005 	strb	r3, [sp, #5]
	/* FIXME: set dstat.bwPollTimeout */

	udp_ep0_send_data((char *)&dstat, sizeof(dstat));
     c64:	ebffff04 	bl	87c <udp_ep0_send_data>
}
     c68:	e8bd400e 	pop	{r1, r2, r3, lr}
     c6c:	e12fff1e 	bx	lr
     c70:	00200020 	.word	0x00200020

00000c74 <dfu_ep0_handler>:
}

/* callback function for DFU requests */
int __dfufunc dfu_ep0_handler(u_int8_t req_type, u_int8_t req,
		    u_int16_t val, u_int16_t len)
{
     c74:	e92d4010 	push	{r4, lr}
     c78:	e1a04003 	mov	r4, r3
	int rc, ret = RET_NOTHING;

	DEBUGE("old_state = %u ", dfu_state);

	switch (dfu_state) {
     c7c:	e59f3204 	ldr	r3, [pc, #516]	; e88 <dfu_ep0_handler+0x214>
     c80:	e5932000 	ldr	r2, [r3]
     c84:	e352000a 	cmp	r2, #10
     c88:	979ff102 	ldrls	pc, [pc, r2, lsl #2]
     c8c:	ea00007a 	b	e7c <dfu_ep0_handler+0x208>
     c90:	00000cbc 	.word	0x00000cbc
     c94:	00000cdc 	.word	0x00000cdc
     c98:	00000cf4 	.word	0x00000cf4
     c9c:	00000d9c 	.word	0x00000d9c
     ca0:	00000e2c 	.word	0x00000e2c
     ca4:	00000d58 	.word	0x00000d58
     ca8:	00000d9c 	.word	0x00000d9c
     cac:	00000da8 	.word	0x00000da8
     cb0:	00000e7c 	.word	0x00000e7c
     cb4:	00000dc8 	.word	0x00000dc8
     cb8:	00000e1c 	.word	0x00000e1c
	case DFU_STATE_appIDLE:
		switch (req) {
     cbc:	e3510003 	cmp	r1, #3
     cc0:	0a00005b 	beq	e34 <dfu_ep0_handler+0x1c0>
     cc4:	e3510005 	cmp	r1, #5
     cc8:	0a00005b 	beq	e3c <dfu_ep0_handler+0x1c8>
     ccc:	e3510000 	cmp	r1, #0
			break;
		case USB_REQ_DFU_GETSTATE:
			handle_getstate();
			break;
		case USB_REQ_DFU_DETACH:
			dfu_state = DFU_STATE_appDETACH;
     cd0:	03a02001 	moveq	r2, #1

	DEBUGE("old_state = %u ", dfu_state);

	switch (dfu_state) {
	case DFU_STATE_appIDLE:
		switch (req) {
     cd4:	0a00004e 	beq	e14 <dfu_ep0_handler+0x1a0>
     cd8:	ea000066 	b	e78 <dfu_ep0_handler+0x204>
		default:
			ret = RET_STALL;
		}
		break;
	case DFU_STATE_appDETACH:
		switch (req) {
     cdc:	e3510003 	cmp	r1, #3
     ce0:	0a000053 	beq	e34 <dfu_ep0_handler+0x1c0>
     ce4:	e3510005 	cmp	r1, #5
			break;
		case USB_REQ_DFU_GETSTATE:
			handle_getstate();
			break;
		default:
			dfu_state = DFU_STATE_appIDLE;
     ce8:	13a02000 	movne	r2, #0
		default:
			ret = RET_STALL;
		}
		break;
	case DFU_STATE_appDETACH:
		switch (req) {
     cec:	1a00005a 	bne	e5c <dfu_ep0_handler+0x1e8>
     cf0:	ea000051 	b	e3c <dfu_ep0_handler+0x1c8>
			break;
		}
		/* FIXME: implement timer to return to appIDLE */
		break;
	case DFU_STATE_dfuIDLE:
		switch (req) {
     cf4:	e2411001 	sub	r1, r1, #1
     cf8:	e3510005 	cmp	r1, #5
     cfc:	979ff101 	ldrls	pc, [pc, r1, lsl #2]
     d00:	ea000054 	b	e58 <dfu_ep0_handler+0x1e4>
     d04:	00000d1c 	.word	0x00000d1c
     d08:	00000d38 	.word	0x00000d38
     d0c:	00000e34 	.word	0x00000e34
     d10:	00000e58 	.word	0x00000e58
     d14:	00000e3c 	.word	0x00000e3c
     d18:	00000e70 	.word	0x00000e70
		case USB_REQ_DFU_DNLOAD:
			if (len == 0) {
     d1c:	e3540000 	cmp	r4, #0
     d20:	0a00004c 	beq	e58 <dfu_ep0_handler+0x1e4>
				dfu_state = DFU_STATE_dfuERROR;
				ret = RET_STALL;
				goto out;
			}
			dfu_state = DFU_STATE_dfuDNLOAD_SYNC;
     d24:	e3a02003 	mov	r2, #3
     d28:	e5832000 	str	r2, [r3]
			ptr = (u_int8_t *) AT91C_IFLASH + SAM7DFU_SIZE;
     d2c:	e3a02941 	mov	r2, #1064960	; 0x104000
     d30:	e59f3154 	ldr	r3, [pc, #340]	; e8c <dfu_ep0_handler+0x218>
     d34:	ea000012 	b	d84 <dfu_ep0_handler+0x110>
			ret = handle_dnload(val, len);
			break;
		case USB_REQ_DFU_UPLOAD:
			ptr = (u_int8_t *) AT91C_IFLASH + SAM7DFU_SIZE;
     d38:	e59f214c 	ldr	r2, [pc, #332]	; e8c <dfu_ep0_handler+0x218>
     d3c:	e3a01941 	mov	r1, #1064960	; 0x104000
     d40:	e5821000 	str	r1, [r2]
			dfu_state = DFU_STATE_dfuUPLOAD_IDLE;
     d44:	e3a02009 	mov	r2, #9
     d48:	e5832000 	str	r2, [r3]
			handle_upload(val, len);
     d4c:	e1a00004 	mov	r0, r4
     d50:	ebffff2c 	bl	a08 <handle_upload.clone.0>
			break;
     d54:	ea000048 	b	e7c <dfu_ep0_handler+0x208>
			ret = RET_STALL;
			goto out;
		}
		break;
	case DFU_STATE_dfuDNLOAD_IDLE:
		switch (req) {
     d58:	e2411001 	sub	r1, r1, #1
     d5c:	e3510005 	cmp	r1, #5
     d60:	979ff101 	ldrls	pc, [pc, r1, lsl #2]
     d64:	ea00003b 	b	e58 <dfu_ep0_handler+0x1e4>
     d68:	00000d80 	.word	0x00000d80
     d6c:	00000e58 	.word	0x00000e58
     d70:	00000e34 	.word	0x00000e34
     d74:	00000e58 	.word	0x00000e58
     d78:	00000e3c 	.word	0x00000e3c
     d7c:	00000e10 	.word	0x00000e10
		case USB_REQ_DFU_DNLOAD:
			dfu_state = DFU_STATE_dfuDNLOAD_SYNC;
     d80:	e3a02003 	mov	r2, #3
     d84:	e5832000 	str	r2, [r3]
			ret = handle_dnload(val, len);
     d88:	e1a00004 	mov	r0, r4
     d8c:	ebffff3a 	bl	a7c <handle_dnload.clone.1>
	}

out:
	DEBUGE("new_state = %u\r\n", dfu_state);

	switch (ret) {
     d90:	e3500001 	cmp	r0, #1
     d94:	1a000032 	bne	e64 <dfu_ep0_handler+0x1f0>
     d98:	ea000034 	b	e70 <dfu_ep0_handler+0x1fc>
			ret = RET_STALL;
			break;
		}
		break;
	case DFU_STATE_dfuMANIFEST_SYNC:
		switch (req) {
     d9c:	e3510003 	cmp	r1, #3
     da0:	1a000002 	bne	db0 <dfu_ep0_handler+0x13c>
     da4:	ea000022 	b	e34 <dfu_ep0_handler+0x1c0>
			ret = RET_STALL;
			break;
		}
		break;
	case DFU_STATE_dfuMANIFEST:
		switch (req) {
     da8:	e3510003 	cmp	r1, #3
     dac:	0a000002 	beq	dbc <dfu_ep0_handler+0x148>
     db0:	e3510005 	cmp	r1, #5
     db4:	1a000027 	bne	e58 <dfu_ep0_handler+0x1e4>
     db8:	ea00001f 	b	e3c <dfu_ep0_handler+0x1c8>
		case USB_REQ_DFU_GETSTATUS:
			dfu_state = DFU_STATE_dfuIDLE;
     dbc:	e3a02002 	mov	r2, #2
     dc0:	e5832000 	str	r2, [r3]
     dc4:	ea00001a 	b	e34 <dfu_ep0_handler+0x1c0>
		break;
	case DFU_STATE_dfuMANIFEST_WAIT_RST:
		/* we should never go here */
		break;
	case DFU_STATE_dfuUPLOAD_IDLE:
		switch (req) {
     dc8:	e2411002 	sub	r1, r1, #2
     dcc:	e3510004 	cmp	r1, #4
     dd0:	979ff101 	ldrls	pc, [pc, r1, lsl #2]
     dd4:	ea00001f 	b	e58 <dfu_ep0_handler+0x1e4>
     dd8:	00000dec 	.word	0x00000dec
     ddc:	00000e34 	.word	0x00000e34
     de0:	00000e58 	.word	0x00000e58
     de4:	00000e3c 	.word	0x00000e3c
     de8:	00000e10 	.word	0x00000e10
		case USB_REQ_DFU_UPLOAD:
			/* state transition if less data then requested */
			rc = handle_upload(val, len);
     dec:	e1a00004 	mov	r0, r4
     df0:	ebffff04 	bl	a08 <handle_upload.clone.0>
			if (rc >= 0 && rc < len)
     df4:	e3500000 	cmp	r0, #0
     df8:	ba00001f 	blt	e7c <dfu_ep0_handler+0x208>
     dfc:	e1500004 	cmp	r0, r4
				dfu_state = DFU_STATE_dfuIDLE;
     e00:	b59f3080 	ldrlt	r3, [pc, #128]	; e88 <dfu_ep0_handler+0x214>
     e04:	b3a02002 	movlt	r2, #2
     e08:	b5832000 	strlt	r2, [r3]
     e0c:	ea00001a 	b	e7c <dfu_ep0_handler+0x208>
			break;
		case USB_REQ_DFU_ABORT:
			dfu_state = DFU_STATE_dfuIDLE;
     e10:	e3a02002 	mov	r2, #2
     e14:	e5832000 	str	r2, [r3]
			/* no zlp? */
			ret = RET_ZLP;
			break;
     e18:	ea000014 	b	e70 <dfu_ep0_handler+0x1fc>
			ret = RET_STALL;
			break;
		}
		break;
	case DFU_STATE_dfuERROR:
		switch (req) {
     e1c:	e3510004 	cmp	r1, #4
     e20:	0a000007 	beq	e44 <dfu_ep0_handler+0x1d0>
     e24:	e3510005 	cmp	r1, #5
     e28:	0a000003 	beq	e3c <dfu_ep0_handler+0x1c8>
     e2c:	e3510003 	cmp	r1, #3
     e30:	1a000008 	bne	e58 <dfu_ep0_handler+0x1e4>
		case USB_REQ_DFU_GETSTATUS:
			handle_getstatus();
     e34:	ebffff65 	bl	bd0 <handle_getstatus>
			break;
     e38:	ea00000f 	b	e7c <dfu_ep0_handler+0x208>
		case USB_REQ_DFU_GETSTATE:
			handle_getstate();
     e3c:	ebfffee7 	bl	9e0 <handle_getstate>
			break;
     e40:	ea00000d 	b	e7c <dfu_ep0_handler+0x208>
		case USB_REQ_DFU_CLRSTATUS:
			dfu_state = DFU_STATE_dfuIDLE;
     e44:	e3a02002 	mov	r2, #2
     e48:	e5832000 	str	r2, [r3]
			dfu_status = DFU_STATUS_OK;
     e4c:	e3a02000 	mov	r2, #0
     e50:	e5c32004 	strb	r2, [r3, #4]
     e54:	ea000005 	b	e70 <dfu_ep0_handler+0x1fc>
			/* no zlp? */
			ret = RET_ZLP;
			break;
		default:
			dfu_state = DFU_STATE_dfuERROR;
     e58:	e3a0200a 	mov	r2, #10
     e5c:	e5832000 	str	r2, [r3]
     e60:	ea000004 	b	e78 <dfu_ep0_handler+0x204>
	}

out:
	DEBUGE("new_state = %u\r\n", dfu_state);

	switch (ret) {
     e64:	e3500002 	cmp	r0, #2
     e68:	1a000003 	bne	e7c <dfu_ep0_handler+0x208>
     e6c:	ea000001 	b	e78 <dfu_ep0_handler+0x204>
	case RET_NOTHING:
		break;
	case RET_ZLP:
		udp_ep0_send_zlp();
     e70:	ebfffeb8 	bl	958 <udp_ep0_send_zlp>
		break;
     e74:	ea000000 	b	e7c <dfu_ep0_handler+0x208>
	case RET_STALL:
		udp_ep0_send_stall();
     e78:	ebfffec7 	bl	99c <udp_ep0_send_stall>
		break;
	}
	return 0;
}
     e7c:	e3a00000 	mov	r0, #0
     e80:	e8bd4010 	pop	{r4, lr}
     e84:	e12fff1e 	bx	lr
     e88:	00200020 	.word	0x00200020
     e8c:	00201adc 	.word	0x00201adc

00000e90 <AT91F_PIO_CfgOutput.clone.5>:
//*----------------------------------------------------------------------------
static inline void AT91F_PIO_CfgOutput(
	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
	unsigned int pioEnable)      // \arg PIO to be enabled
{
	pPio->PIO_PER = pioEnable; // Set in PIO mode
     e90:	e3e03c0b 	mvn	r3, #2816	; 0xb00
     e94:	e50300ff 	str	r0, [r3, #-255]	; 0xffffff01
	pPio->PIO_OER = pioEnable; // Configure in Output
     e98:	e50300ef 	str	r0, [r3, #-239]	; 0xffffff11
}
     e9c:	e12fff1e 	bx	lr

00000ea0 <udp_init>:
#define led2off()	AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPCD_PIO_LED2)

static void __dfufunc udp_init(void)
{
	/* Set the PLL USB Divider */
	AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
     ea0:	e3e03c03 	mvn	r3, #768	; 0x300
     ea4:	e51320d3 	ldr	r2, [r3, #-211]	; 0xffffff2d
     ea8:	e3822201 	orr	r2, r2, #268435456	; 0x10000000

#define led2on()	AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, OPENPCD_PIO_LED2)
#define led2off()	AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPCD_PIO_LED2)

static void __dfufunc udp_init(void)
{
     eac:	e92d4010 	push	{r4, lr}
	/* Set the PLL USB Divider */
	AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
     eb0:	e50320d3 	str	r2, [r3, #-211]	; 0xffffff2d

	/* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock */
	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;
     eb4:	e3a02080 	mov	r2, #128	; 0x80
     eb8:	e50320ff 	str	r2, [r3, #-255]	; 0xffffff01
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);
     ebc:	e2822d1e 	add	r2, r2, #1920	; 0x780
     ec0:	e50320ef 	str	r2, [r3, #-239]	; 0xffffff11

	/* Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the
	 * corresponding PIO Set in PIO mode and Configure in Output */
#if defined(PCD)
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUP);
     ec4:	e3a00501 	mov	r0, #4194304	; 0x400000
     ec8:	ebfffff0 	bl	e90 <AT91F_PIO_CfgOutput.clone.5>
#endif
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUPv4);
     ecc:	e3a00801 	mov	r0, #65536	; 0x10000
}
     ed0:	e8bd4010 	pop	{r4, lr}
	/* Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the
	 * corresponding PIO Set in PIO mode and Configure in Output */
#if defined(PCD)
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUP);
#endif
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUPv4);
     ed4:	eaffffed 	b	e90 <AT91F_PIO_CfgOutput.clone.5>

00000ed8 <AT91F_PIO_SetOutput.clone.6>:
//*----------------------------------------------------------------------------
static inline void AT91F_PIO_SetOutput(
	const AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
	const unsigned int flag) // \arg  output to be set
{
	pPio->PIO_SODR = flag;
     ed8:	e3e03c0b 	mvn	r3, #2816	; 0xb00
     edc:	e50300cf 	str	r0, [r3, #-207]	; 0xffffff31
}
     ee0:	e12fff1e 	bx	lr

00000ee4 <AT91F_PIO_ClearOutput.clone.7>:
//*----------------------------------------------------------------------------
static inline void AT91F_PIO_ClearOutput(
	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
	unsigned int flag) // \arg  output to be cleared
{
	pPio->PIO_CODR = flag;
     ee4:	e3e03c0b 	mvn	r3, #2816	; 0xb00
     ee8:	e50300cb 	str	r0, [r3, #-203]	; 0xffffff35
}
     eec:	e12fff1e 	bx	lr

00000ef0 <AT91F_RSTSoftReset.clone.8>:
//*----------------------------------------------------------------------------
static inline void AT91F_RSTSoftReset(
        AT91PS_RSTC pRSTC,
        unsigned int reset)
{
	pRSTC->RSTC_RCR = (0xA5000000 | reset);
     ef0:	e59f2008 	ldr	r2, [pc, #8]	; f00 <AIC_MCR_RCR>
     ef4:	e3e03c02 	mvn	r3, #512	; 0x200
     ef8:	e50320ff 	str	r2, [r3, #-255]	; 0xffffff01
}
     efc:	e12fff1e 	bx	lr
     f00:	a500000d 	.word	0xa500000d

00000f04 <dfu_udp_irq>:
	DEBUGE("\r\n");
}

/* minimal USB IRQ handler in DFU mode */
static __dfufunc void dfu_udp_irq(void)
{
     f04:	e92d4037 	push	{r0, r1, r2, r4, r5, lr}
	AT91PS_UDP pUDP = AT91C_BASE_UDP;
	AT91_REG isr = pUDP->UDP_ISR;
     f08:	e59f4384 	ldr	r4, [pc, #900]	; 1294 <dfu_udp_irq+0x390>
     f0c:	e51430e3 	ldr	r3, [r4, #-227]	; 0xffffff1d
	led1on();
     f10:	e3a00402 	mov	r0, #33554432	; 0x2000000

/* minimal USB IRQ handler in DFU mode */
static __dfufunc void dfu_udp_irq(void)
{
	AT91PS_UDP pUDP = AT91C_BASE_UDP;
	AT91_REG isr = pUDP->UDP_ISR;
     f14:	e58d3000 	str	r3, [sp]
	led1on();
     f18:	ebfffff1 	bl	ee4 <AT91F_PIO_ClearOutput.clone.7>

	if (isr & AT91C_UDP_ENDBUSRES) {
     f1c:	e59d3000 	ldr	r3, [sp]
     f20:	e3130a01 	tst	r3, #4096	; 0x1000
     f24:	0a000012 	beq	f74 <dfu_udp_irq+0x70>
		led2on();
     f28:	e3a00301 	mov	r0, #67108864	; 0x4000000
     f2c:	ebffffec 	bl	ee4 <AT91F_PIO_ClearOutput.clone.7>
		pUDP->UDP_IER = AT91C_UDP_EPINT0;
     f30:	e3a03001 	mov	r3, #1
     f34:	e50430ef 	str	r3, [r4, #-239]	; 0xffffff11
		/* reset all endpoints */
		pUDP->UDP_RSTEP = (unsigned int)-1;
     f38:	e3e03000 	mvn	r3, #0
     f3c:	e50430d7 	str	r3, [r4, #-215]	; 0xffffff29
		pUDP->UDP_RSTEP = 0;
		/* Enable the function */
		pUDP->UDP_FADDR = AT91C_UDP_FEN;
     f40:	e3a02c01 	mov	r2, #256	; 0x100
	if (isr & AT91C_UDP_ENDBUSRES) {
		led2on();
		pUDP->UDP_IER = AT91C_UDP_EPINT0;
		/* reset all endpoints */
		pUDP->UDP_RSTEP = (unsigned int)-1;
		pUDP->UDP_RSTEP = 0;
     f44:	e2833001 	add	r3, r3, #1
     f48:	e50430d7 	str	r3, [r4, #-215]	; 0xffffff29
		/* Enable the function */
		pUDP->UDP_FADDR = AT91C_UDP_FEN;
     f4c:	e50420f7 	str	r2, [r4, #-247]	; 0xffffff09
		/* Configure endpoint 0 */
		pUDP->UDP_CSR[0] = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL);
     f50:	e2822c7f 	add	r2, r2, #32512	; 0x7f00
     f54:	e50420cf 	str	r2, [r4, #-207]	; 0xffffff31
		cur_config = 0;
     f58:	e59f2338 	ldr	r2, [pc, #824]	; 1298 <dfu_udp_irq+0x394>
     f5c:	e5c23100 	strb	r3, [r2, #256]	; 0x100

		if (dfu_state == DFU_STATE_dfuMANIFEST_WAIT_RST ||
     f60:	e59f3334 	ldr	r3, [pc, #820]	; 129c <dfu_udp_irq+0x398>
     f64:	e5933000 	ldr	r3, [r3]
     f68:	e2433007 	sub	r3, r3, #7
     f6c:	e3530001 	cmp	r3, #1
		    dfu_state == DFU_STATE_dfuMANIFEST) {
			AT91F_RSTSoftReset(AT91C_BASE_RSTC, AT91C_RSTC_PROCRST|
     f70:	9bffffde 	blls	ef0 <AT91F_RSTSoftReset.clone.8>
							    AT91C_RSTC_EXTRST);
		}
			
	}

	if (isr & AT91C_UDP_EPINT0)
     f74:	e59d3000 	ldr	r3, [sp]
     f78:	e3130001 	tst	r3, #1
     f7c:	0a0000ba 	beq	126c <dfu_udp_irq+0x368>
static __dfufunc void dfu_udp_ep0_handler(void)
{
	AT91PS_UDP pUDP = AT91C_BASE_UDP;
	u_int8_t bmRequestType, bRequest;
	u_int16_t wValue, wIndex, wLength, wStatus;
	u_int32_t csr = pUDP->UDP_CSR[0];
     f80:	e59f230c 	ldr	r2, [pc, #780]	; 1294 <dfu_udp_irq+0x390>
     f84:	e51230cf 	ldr	r3, [r2, #-207]	; 0xffffff31

	DEBUGE("CSR=0x%04x ", csr);

	if (csr & AT91C_UDP_STALLSENT) {
     f88:	e3130008 	tst	r3, #8
		DEBUGE("ACK_STALLSENT ");
		pUDP->UDP_CSR[0] = ~AT91C_UDP_STALLSENT;
     f8c:	13e01008 	mvnne	r1, #8
     f90:	150210cf 	strne	r1, [r2, #-207]	; 0xffffff31
	}

	if (csr & AT91C_UDP_RX_DATA_BK0) {
     f94:	e3130002 	tst	r3, #2
		DEBUGE("ACK_BANK0 ");
		pUDP->UDP_CSR[0] &= ~AT91C_UDP_RX_DATA_BK0;
     f98:	151210cf 	ldrne	r1, [r2, #-207]	; 0xffffff31
     f9c:	13c11002 	bicne	r1, r1, #2
     fa0:	150210cf 	strne	r1, [r2, #-207]	; 0xffffff31
	}

	if (!(csr & AT91C_UDP_RXSETUP)) {
     fa4:	e3130004 	tst	r3, #4
     fa8:	0a0000af 	beq	126c <dfu_udp_irq+0x368>
		DEBUGE("no setup packet\r\n");
		return;
	}

	DEBUGE("len=%d ", csr >> 16);
	if (csr >> 16  == 0) {
     fac:	e1b03823 	lsrs	r3, r3, #16
     fb0:	0a0000ad 	beq	126c <dfu_udp_irq+0x368>
		DEBUGE("empty packet\r\n");
		return;
	}

	bmRequestType = pUDP->UDP_FDR[0];
     fb4:	e59f22d8 	ldr	r2, [pc, #728]	; 1294 <dfu_udp_irq+0x390>
     fb8:	e51200af 	ldr	r0, [r2, #-175]	; 0xffffff51
	bRequest = pUDP->UDP_FDR[0];
     fbc:	e51210af 	ldr	r1, [r2, #-175]	; 0xffffff51
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
     fc0:	e51240af 	ldr	r4, [r2, #-175]	; 0xffffff51
	wValue |= (pUDP->UDP_FDR[0] << 8);
     fc4:	e51230af 	ldr	r3, [r2, #-175]	; 0xffffff51
		return;
	}

	bmRequestType = pUDP->UDP_FDR[0];
	bRequest = pUDP->UDP_FDR[0];
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
     fc8:	e20440ff 	and	r4, r4, #255	; 0xff
	wValue |= (pUDP->UDP_FDR[0] << 8);
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
     fcc:	e512e0af 	ldr	lr, [r2, #-175]	; 0xffffff51
	}

	bmRequestType = pUDP->UDP_FDR[0];
	bRequest = pUDP->UDP_FDR[0];
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
	wValue |= (pUDP->UDP_FDR[0] << 8);
     fd0:	e1844403 	orr	r4, r4, r3, lsl #8
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
	wIndex |= (pUDP->UDP_FDR[0] << 8);
     fd4:	e51230af 	ldr	r3, [r2, #-175]	; 0xffffff51
	wLength = (pUDP->UDP_FDR[0] & 0xFF);
     fd8:	e51230af 	ldr	r3, [r2, #-175]	; 0xffffff51
	wLength |= (pUDP->UDP_FDR[0] << 8);
     fdc:	e512c0af 	ldr	ip, [r2, #-175]	; 0xffffff51
	bRequest = pUDP->UDP_FDR[0];
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
	wValue |= (pUDP->UDP_FDR[0] << 8);
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
	wIndex |= (pUDP->UDP_FDR[0] << 8);
	wLength = (pUDP->UDP_FDR[0] & 0xFF);
     fe0:	e20330ff 	and	r3, r3, #255	; 0xff
	if (csr >> 16  == 0) {
		DEBUGE("empty packet\r\n");
		return;
	}

	bmRequestType = pUDP->UDP_FDR[0];
     fe4:	e20000ff 	and	r0, r0, #255	; 0xff
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
	wValue |= (pUDP->UDP_FDR[0] << 8);
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
	wIndex |= (pUDP->UDP_FDR[0] << 8);
	wLength = (pUDP->UDP_FDR[0] & 0xFF);
	wLength |= (pUDP->UDP_FDR[0] << 8);
     fe8:	e183340c 	orr	r3, r3, ip, lsl #8
	}

	bmRequestType = pUDP->UDP_FDR[0];
	bRequest = pUDP->UDP_FDR[0];
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
	wValue |= (pUDP->UDP_FDR[0] << 8);
     fec:	e1a04804 	lsl	r4, r4, #16
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
	wIndex |= (pUDP->UDP_FDR[0] << 8);
	wLength = (pUDP->UDP_FDR[0] & 0xFF);
	wLength |= (pUDP->UDP_FDR[0] << 8);
     ff0:	e1a03803 	lsl	r3, r3, #16

	DEBUGE("bmRequestType=0x%2x ", bmRequestType);

	if (bmRequestType & 0x80) {
     ff4:	e3100080 	tst	r0, #128	; 0x80
		DEBUGE("empty packet\r\n");
		return;
	}

	bmRequestType = pUDP->UDP_FDR[0];
	bRequest = pUDP->UDP_FDR[0];
     ff8:	e20110ff 	and	r1, r1, #255	; 0xff
	wValue = (pUDP->UDP_FDR[0] & 0xFF);
	wValue |= (pUDP->UDP_FDR[0] << 8);
     ffc:	e1a04824 	lsr	r4, r4, #16
	wIndex = (pUDP->UDP_FDR[0] & 0xFF);
	wIndex |= (pUDP->UDP_FDR[0] << 8);
	wLength = (pUDP->UDP_FDR[0] & 0xFF);
	wLength |= (pUDP->UDP_FDR[0] << 8);
    1000:	e1a03823 	lsr	r3, r3, #16

	DEBUGE("bmRequestType=0x%2x ", bmRequestType);

	if (bmRequestType & 0x80) {
    1004:	0a000005 	beq	1020 <dfu_udp_irq+0x11c>
		DEBUGE("DATA_IN=1 ");
		pUDP->UDP_CSR[0] |= AT91C_UDP_DIR;
    1008:	e512c0cf 	ldr	ip, [r2, #-207]	; 0xffffff31
    100c:	e38cc080 	orr	ip, ip, #128	; 0x80
    1010:	e502c0cf 	str	ip, [r2, #-207]	; 0xffffff31
		while (!(pUDP->UDP_CSR[0] & AT91C_UDP_DIR)) ;
    1014:	e512c0cf 	ldr	ip, [r2, #-207]	; 0xffffff31
    1018:	e31c0080 	tst	ip, #128	; 0x80
    101c:	0afffffc 	beq	1014 <dfu_udp_irq+0x110>
	}
	pUDP->UDP_CSR[0] &= ~AT91C_UDP_RXSETUP;
    1020:	e59f226c 	ldr	r2, [pc, #620]	; 1294 <dfu_udp_irq+0x390>
    1024:	e512c0cf 	ldr	ip, [r2, #-207]	; 0xffffff31
    1028:	e3ccc004 	bic	ip, ip, #4
    102c:	e502c0cf 	str	ip, [r2, #-207]	; 0xffffff31
	while ((pUDP->UDP_CSR[0] & AT91C_UDP_RXSETUP)) ;
    1030:	e512c0cf 	ldr	ip, [r2, #-207]	; 0xffffff31
    1034:	e21cc004 	ands	ip, ip, #4
    1038:	e59f5254 	ldr	r5, [pc, #596]	; 1294 <dfu_udp_irq+0x390>
    103c:	1afffffb 	bne	1030 <dfu_udp_irq+0x12c>

	/* Handle supported standard device request Cf Table 9-3 in USB
	 * speciication Rev 1.1 */
	switch ((bRequest << 8) | bmRequestType) {
    1040:	e1802401 	orr	r2, r0, r1, lsl #8
    1044:	e3520c03 	cmp	r2, #768	; 0x300
    1048:	0a000086 	beq	1268 <dfu_udp_irq+0x364>
    104c:	ca000010 	bgt	1094 <dfu_udp_irq+0x190>
    1050:	e3520082 	cmp	r2, #130	; 0x82
    1054:	0a000065 	beq	11f0 <dfu_udp_irq+0x2ec>
    1058:	ca000004 	bgt	1070 <dfu_udp_irq+0x16c>
    105c:	e3520080 	cmp	r2, #128	; 0x80
    1060:	0a00005f 	beq	11e4 <dfu_udp_irq+0x2e0>
    1064:	e3520081 	cmp	r2, #129	; 0x81
    1068:	1a000078 	bne	1250 <dfu_udp_irq+0x34c>
    106c:	ea00005c 	b	11e4 <dfu_udp_irq+0x2e0>
    1070:	e59fc228 	ldr	ip, [pc, #552]	; 12a0 <dfu_udp_irq+0x39c>
    1074:	e152000c 	cmp	r2, ip
    1078:	0a000072 	beq	1248 <dfu_udp_irq+0x344>
    107c:	e28cc001 	add	ip, ip, #1
    1080:	e152000c 	cmp	r2, ip
    1084:	0a000077 	beq	1268 <dfu_udp_irq+0x364>
    1088:	e3520c01 	cmp	r2, #256	; 0x100
    108c:	1a00006f 	bne	1250 <dfu_udp_irq+0x34c>
    1090:	ea000074 	b	1268 <dfu_udp_irq+0x364>
    1094:	e3520d1a 	cmp	r2, #1664	; 0x680
    1098:	0a00000f 	beq	10dc <dfu_udp_irq+0x1d8>
    109c:	ca000006 	bgt	10bc <dfu_udp_irq+0x1b8>
    10a0:	e59fc1fc 	ldr	ip, [pc, #508]	; 12a4 <dfu_udp_irq+0x3a0>
    10a4:	e152000c 	cmp	r2, ip
    10a8:	0a00006e 	beq	1268 <dfu_udp_irq+0x364>
    10ac:	ba000065 	blt	1248 <dfu_udp_irq+0x344>
    10b0:	e3520c05 	cmp	r2, #1280	; 0x500
    10b4:	1a000065 	bne	1250 <dfu_udp_irq+0x34c>
    10b8:	ea00002d 	b	1174 <dfu_udp_irq+0x270>
    10bc:	e3520c09 	cmp	r2, #2304	; 0x900
    10c0:	0a000032 	beq	1190 <dfu_udp_irq+0x28c>
    10c4:	e59fc1dc 	ldr	ip, [pc, #476]	; 12a8 <dfu_udp_irq+0x3a4>
    10c8:	e152000c 	cmp	r2, ip
    10cc:	0a00005d 	beq	1248 <dfu_udp_irq+0x344>
    10d0:	e3520d22 	cmp	r2, #2176	; 0x880
    10d4:	1a00005d 	bne	1250 <dfu_udp_irq+0x34c>
    10d8:	ea00003e 	b	11d8 <dfu_udp_irq+0x2d4>
		u_int8_t desc_type, desc_index;
	case STD_GET_DESCRIPTOR:
		DEBUGE("GET_DESCRIPTOR ");
		desc_type = wValue >> 8;
		desc_index = wValue & 0xff;
		switch (desc_type) {
    10dc:	e1a02424 	lsr	r2, r4, #8
    10e0:	e3520002 	cmp	r2, #2
    10e4:	0a00000d 	beq	1120 <dfu_udp_irq+0x21c>
    10e8:	8a000002 	bhi	10f8 <dfu_udp_irq+0x1f4>
    10ec:	e3520001 	cmp	r2, #1
    10f0:	1a00005c 	bne	1268 <dfu_udp_irq+0x364>
    10f4:	ea000004 	b	110c <dfu_udp_irq+0x208>
    10f8:	e3520003 	cmp	r2, #3
    10fc:	0a00000d 	beq	1138 <dfu_udp_irq+0x234>
    1100:	e3520021 	cmp	r2, #33	; 0x21
    1104:	1a000057 	bne	1268 <dfu_udp_irq+0x364>
    1108:	ea000014 	b	1160 <dfu_udp_irq+0x25c>
		case USB_DT_DEVICE:
			/* Return Device Descriptor */
			udp_ep0_send_data((const char *) 
    110c:	e59f0198 	ldr	r0, [pc, #408]	; 12ac <dfu_udp_irq+0x3a8>
    1110:	e3530012 	cmp	r3, #18
    1114:	31a01003 	movcc	r1, r3
    1118:	23a01012 	movcs	r1, #18
    111c:	ea000003 	b	1130 <dfu_udp_irq+0x22c>
					  MIN(sizeof(dfu_dev_descriptor),
					      wLength));
			break;
		case USB_DT_CONFIG:
			/* Return Configuration Descriptor */
			udp_ep0_send_data((const char *)
    1120:	e59f0188 	ldr	r0, [pc, #392]	; 12b0 <dfu_udp_irq+0x3ac>
    1124:	e3530024 	cmp	r3, #36	; 0x24
    1128:	31a01003 	movcc	r1, r3
    112c:	23a01024 	movcs	r1, #36	; 0x24
    1130:	ebfffdd1 	bl	87c <udp_ep0_send_data>
    1134:	ea00004c 	b	126c <dfu_udp_irq+0x368>
	switch ((bRequest << 8) | bmRequestType) {
		u_int8_t desc_type, desc_index;
	case STD_GET_DESCRIPTOR:
		DEBUGE("GET_DESCRIPTOR ");
		desc_type = wValue >> 8;
		desc_index = wValue & 0xff;
    1138:	e20440ff 	and	r4, r4, #255	; 0xff
					  MIN(sizeof(dfu_cfg_descriptor),
					      wLength));
			break;
		case USB_DT_STRING:
			/* Return String Descriptor */
			if (desc_index > ARRAY_SIZE(usb_strings)) {
    113c:	e3540006 	cmp	r4, #6
    1140:	8a000048 	bhi	1268 <dfu_udp_irq+0x364>
				udp_ep0_send_stall();
				break;
			}
			DEBUGE("bLength=%u, wLength=%u ", 
				usb_strings[desc_index]->bLength, wLength);
			udp_ep0_send_data((const char *) usb_strings[desc_index],
    1144:	e59f2160 	ldr	r2, [pc, #352]	; 12ac <dfu_udp_irq+0x3a8>
    1148:	e0824104 	add	r4, r2, r4, lsl #2
    114c:	e5940038 	ldr	r0, [r4, #56]	; 0x38
					  MIN(usb_strings[desc_index]->bLength, 
    1150:	e5d01000 	ldrb	r1, [r0]
				udp_ep0_send_stall();
				break;
			}
			DEBUGE("bLength=%u, wLength=%u ", 
				usb_strings[desc_index]->bLength, wLength);
			udp_ep0_send_data((const char *) usb_strings[desc_index],
    1154:	e1530001 	cmp	r3, r1
    1158:	31a01003 	movcc	r1, r3
    115c:	eafffff3 	b	1130 <dfu_udp_irq+0x22c>
					  MIN(usb_strings[desc_index]->bLength, 
					      wLength));
			break;
		case USB_DT_CS_DEVICE:
			/* Return Function descriptor */
			udp_ep0_send_data((const char *) &dfu_cfg_descriptor.func_dfu,
    1160:	e59f014c 	ldr	r0, [pc, #332]	; 12b4 <dfu_udp_irq+0x3b0>
    1164:	e3530009 	cmp	r3, #9
    1168:	31a01003 	movcc	r1, r3
    116c:	23a01009 	movcs	r1, #9
    1170:	eaffffee 	b	1130 <dfu_udp_irq+0x22c>
			break;
		}
		break;
	case STD_SET_ADDRESS:
		DEBUGE("SET_ADDRESS ");
		udp_ep0_send_zlp();
    1174:	ebfffdf7 	bl	958 <udp_ep0_send_zlp>
		pUDP->UDP_FADDR = (AT91C_UDP_FEN | wValue);
    1178:	e3843c01 	orr	r3, r4, #256	; 0x100
		pUDP->UDP_GLBSTATE = (wValue) ? AT91C_UDP_FADDEN : 0;
    117c:	e2544000 	subs	r4, r4, #0
    1180:	13a04001 	movne	r4, #1
		}
		break;
	case STD_SET_ADDRESS:
		DEBUGE("SET_ADDRESS ");
		udp_ep0_send_zlp();
		pUDP->UDP_FADDR = (AT91C_UDP_FEN | wValue);
    1184:	e50530f7 	str	r3, [r5, #-247]	; 0xffffff09
		pUDP->UDP_GLBSTATE = (wValue) ? AT91C_UDP_FADDEN : 0;
    1188:	e50540fb 	str	r4, [r5, #-251]	; 0xffffff05
    118c:	ea000036 	b	126c <dfu_udp_irq+0x368>
		break;
	case STD_SET_CONFIGURATION:
		DEBUGE("SET_CONFIG ");
		if (wValue)
			DEBUGE("VALUE!=0 ");
		cur_config = wValue;
    1190:	e59f3100 	ldr	r3, [pc, #256]	; 1298 <dfu_udp_irq+0x394>
    1194:	e5c34100 	strb	r4, [r3, #256]	; 0x100
		udp_ep0_send_zlp();
    1198:	ebfffdee 	bl	958 <udp_ep0_send_zlp>
		pUDP->UDP_GLBSTATE =
		    (wValue) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN;
    119c:	e3540000 	cmp	r4, #0
    11a0:	03a03001 	moveq	r3, #1
    11a4:	13a03002 	movne	r3, #2
		DEBUGE("SET_CONFIG ");
		if (wValue)
			DEBUGE("VALUE!=0 ");
		cur_config = wValue;
		udp_ep0_send_zlp();
		pUDP->UDP_GLBSTATE =
    11a8:	e50530fb 	str	r3, [r5, #-251]	; 0xffffff05
		    (wValue) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN;
		pUDP->UDP_CSR[1] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) :
    11ac:	01a03004 	moveq	r3, r4
    11b0:	13a03c82 	movne	r3, #33280	; 0x8200
			DEBUGE("VALUE!=0 ");
		cur_config = wValue;
		udp_ep0_send_zlp();
		pUDP->UDP_GLBSTATE =
		    (wValue) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN;
		pUDP->UDP_CSR[1] =
    11b4:	e50530cb 	str	r3, [r5, #-203]	; 0xffffff35
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) :
		    0;
		pUDP->UDP_CSR[2] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN) : 0;
    11b8:	01a03004 	moveq	r3, r4
    11bc:	13a03c86 	movne	r3, #34304	; 0x8600
		pUDP->UDP_GLBSTATE =
		    (wValue) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN;
		pUDP->UDP_CSR[1] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) :
		    0;
		pUDP->UDP_CSR[2] =
    11c0:	e50530c7 	str	r3, [r5, #-199]	; 0xffffff39
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN) : 0;
		pUDP->UDP_CSR[3] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN) : 0;
    11c4:	13a04c87 	movne	r4, #34560	; 0x8700
		pUDP->UDP_IER = (AT91C_UDP_EPINT0|AT91C_UDP_EPINT1|
    11c8:	e3a0300f 	mov	r3, #15
		pUDP->UDP_CSR[1] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) :
		    0;
		pUDP->UDP_CSR[2] =
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN) : 0;
		pUDP->UDP_CSR[3] =
    11cc:	e50540c3 	str	r4, [r5, #-195]	; 0xffffff3d
		    (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN) : 0;
		pUDP->UDP_IER = (AT91C_UDP_EPINT0|AT91C_UDP_EPINT1|
    11d0:	e50530ef 	str	r3, [r5, #-239]	; 0xffffff11
    11d4:	ea000024 	b	126c <dfu_udp_irq+0x368>
				 AT91C_UDP_EPINT2|AT91C_UDP_EPINT3);
		break;
	case STD_GET_CONFIGURATION:
		DEBUGE("GET_CONFIG ");
		udp_ep0_send_data((char *)&(cur_config),
    11d8:	e59f00d8 	ldr	r0, [pc, #216]	; 12b8 <dfu_udp_irq+0x3b4>
    11dc:	e3a01001 	mov	r1, #1
    11e0:	eaffffd2 	b	1130 <dfu_udp_irq+0x22c>
		wStatus = 0;
		udp_ep0_send_data((char *)&wStatus, sizeof(wStatus));
		break;
	case STD_GET_STATUS_INTERFACE:
		DEBUGE("GET_STATUS_INTERFACE ");
		wStatus = 0;
    11e4:	e28d0008 	add	r0, sp, #8
    11e8:	e160c0b2 	strh	ip, [r0, #-2]!
    11ec:	ea000013 	b	1240 <dfu_udp_irq+0x33c>
		break;
	case STD_GET_STATUS_ENDPOINT:
		DEBUGE("GET_STATUS_ENDPOINT(EPidx=%u) ", wIndex&0x0f);
		wStatus = 0;
		wIndex &= 0x0F;
		if ((pUDP->UDP_GLBSTATE & AT91C_UDP_CONFG) && (wIndex == 0)) {
    11f0:	e51530fb 	ldr	r3, [r5, #-251]	; 0xffffff05
    11f4:	e3130002 	tst	r3, #2
		wStatus = 0;
		udp_ep0_send_data((char *)&wStatus, sizeof(wStatus));
		break;
	case STD_GET_STATUS_ENDPOINT:
		DEBUGE("GET_STATUS_ENDPOINT(EPidx=%u) ", wIndex&0x0f);
		wStatus = 0;
    11f8:	e1cdc0b6 	strh	ip, [sp, #6]
		wIndex &= 0x0F;
    11fc:	e20e200f 	and	r2, lr, #15
		if ((pUDP->UDP_GLBSTATE & AT91C_UDP_CONFG) && (wIndex == 0)) {
    1200:	0a000002 	beq	1210 <dfu_udp_irq+0x30c>
    1204:	e3520000 	cmp	r2, #0
			wStatus =
			    (pUDP->UDP_CSR[wIndex] & AT91C_UDP_EPEDS) ? 0 : 1;
    1208:	051530cf 	ldreq	r3, [r5, #-207]	; 0xffffff31
		break;
	case STD_GET_STATUS_ENDPOINT:
		DEBUGE("GET_STATUS_ENDPOINT(EPidx=%u) ", wIndex&0x0f);
		wStatus = 0;
		wIndex &= 0x0F;
		if ((pUDP->UDP_GLBSTATE & AT91C_UDP_CONFG) && (wIndex == 0)) {
    120c:	0a000006 	beq	122c <dfu_udp_irq+0x328>
			wStatus =
			    (pUDP->UDP_CSR[wIndex] & AT91C_UDP_EPEDS) ? 0 : 1;
			udp_ep0_send_data((char *)&wStatus,
					   sizeof(wStatus));
		} else if ((pUDP->UDP_GLBSTATE & AT91C_UDP_FADDEN)
    1210:	e59f307c 	ldr	r3, [pc, #124]	; 1294 <dfu_udp_irq+0x390>
    1214:	e51310fb 	ldr	r1, [r3, #-251]	; 0xffffff05
    1218:	e3110001 	tst	r1, #1
    121c:	0a000011 	beq	1268 <dfu_udp_irq+0x364>
			   && (wIndex == 0)) {
    1220:	e3520000 	cmp	r2, #0
    1224:	1a00000f 	bne	1268 <dfu_udp_irq+0x364>
			wStatus =
			    (pUDP->UDP_CSR[wIndex] & AT91C_UDP_EPEDS) ? 0 : 1;
    1228:	e51330cf 	ldr	r3, [r3, #-207]	; 0xffffff31
    122c:	e3130902 	tst	r3, #32768	; 0x8000
    1230:	13a03000 	movne	r3, #0
    1234:	03a03001 	moveq	r3, #1
    1238:	e28d0008 	add	r0, sp, #8
    123c:	e16030b2 	strh	r3, [r0, #-2]!
			udp_ep0_send_data((char *)&wStatus,
    1240:	e3a01002 	mov	r1, #2
    1244:	eaffffb9 	b	1130 <dfu_udp_irq+0x22c>
		break;
	case STD_SET_INTERFACE:
		DEBUGE("SET INTERFACE ");
		/* FIXME: store the interface number somewhere, once
		 * we need to support DFU flashing DFU */
		udp_ep0_send_zlp();
    1248:	ebfffdc2 	bl	958 <udp_ep0_send_zlp>
    124c:	ea000006 	b	126c <dfu_udp_irq+0x368>
		break;
	default:
		DEBUGE("DEFAULT(req=0x%02x, type=0x%02x) ",
			bRequest, bmRequestType);
		if ((bmRequestType & 0x3f) == USB_TYPE_DFU) {
    1250:	e200203f 	and	r2, r0, #63	; 0x3f
    1254:	e3520021 	cmp	r2, #33	; 0x21
    1258:	1a000002 	bne	1268 <dfu_udp_irq+0x364>
			dfu_ep0_handler(bmRequestType, bRequest,
    125c:	e1a02004 	mov	r2, r4
    1260:	ebfffe83 	bl	c74 <dfu_ep0_handler>
    1264:	ea000000 	b	126c <dfu_udp_irq+0x368>
					wValue, wLength);
		} else
			udp_ep0_send_stall();
    1268:	ebfffdcb 	bl	99c <udp_ep0_send_stall>

	if (isr & AT91C_UDP_EPINT0)
		dfu_udp_ep0_handler();

	/* clear all interrupts */
	pUDP->UDP_ICR = isr;
    126c:	e59d2000 	ldr	r2, [sp]
    1270:	e59f301c 	ldr	r3, [pc, #28]	; 1294 <dfu_udp_irq+0x390>
    1274:	e50320df 	str	r2, [r3, #-223]	; 0xffffff21
static inline void AT91F_AIC_ClearIt (
	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
	unsigned int irq_id) // \arg interrupt number to initialize
{
    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
    pAic->AIC_ICCR = (0x1 << irq_id);
    1278:	e3a02b02 	mov	r2, #2048	; 0x800
    127c:	e2833a4f 	add	r3, r3, #323584	; 0x4f000
    1280:	e5832029 	str	r2, [r3, #41]	; 0x29

	AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_UDP);

	led1off();
    1284:	e3a00402 	mov	r0, #33554432	; 0x2000000
    1288:	ebffff12 	bl	ed8 <AT91F_PIO_SetOutput.clone.6>
}
    128c:	e8bd403e 	pop	{r1, r2, r3, r4, r5, lr}
    1290:	e12fff1e 	bx	lr
    1294:	fffb00ff 	.word	0xfffb00ff
    1298:	00201ae4 	.word	0x00201ae4
    129c:	00200020 	.word	0x00200020
    12a0:	00000101 	.word	0x00000101
    12a4:	00000302 	.word	0x00000302
    12a8:	00000b01 	.word	0x00000b01
    12ac:	000017b8 	.word	0x000017b8
    12b0:	000017ca 	.word	0x000017ca
    12b4:	000017e5 	.word	0x000017e5
    12b8:	00201be4 	.word	0x00201be4

000012bc <dfu_switch>:

/* this is only called once before DFU mode, no __dfufunc required */
static void dfu_switch(void)
{
    12bc:	e92d4008 	push	{r3, lr}
	AT91PS_AIC pAic = AT91C_BASE_AIC;

	DEBUGE("\r\nsam7dfu: switching to DFU mode\r\n");

	dfu_state = DFU_STATE_appDETACH;
    12c0:	e59f300c 	ldr	r3, [pc, #12]	; 12d4 <dfu_switch+0x18>
    12c4:	e3a02001 	mov	r2, #1
    12c8:	e5832000 	str	r2, [r3]
	AT91F_RSTSoftReset(AT91C_BASE_RSTC, AT91C_RSTC_PROCRST|
    12cc:	ebffff07 	bl	ef0 <AT91F_RSTSoftReset.clone.8>
    12d0:	eafffffe 	b	12d0 <dfu_switch+0x14>
    12d4:	00200020 	.word	0x00200020

000012d8 <dfu_main>:
	 * caller since he doesn't expect us to do so */
	while (1) ;
}

void __dfufunc dfu_main(void)
{
    12d8:	e92d4008 	push	{r3, lr}
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_LED1);
    12dc:	e3a00402 	mov	r0, #33554432	; 0x2000000
    12e0:	ebfffeea 	bl	e90 <AT91F_PIO_CfgOutput.clone.5>
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_PIO_LED2);
    12e4:	e3a00301 	mov	r0, #67108864	; 0x4000000
    12e8:	ebfffee8 	bl	e90 <AT91F_PIO_CfgOutput.clone.5>
	led1off();
    12ec:	e3a00402 	mov	r0, #33554432	; 0x2000000
    12f0:	ebfffef8 	bl	ed8 <AT91F_PIO_SetOutput.clone.6>
	led2off();
    12f4:	e3a00301 	mov	r0, #67108864	; 0x4000000
    12f8:	ebfffef6 	bl	ed8 <AT91F_PIO_SetOutput.clone.6>

	AT91F_DBGU_Init();
    12fc:	eb00002b 	bl	13b0 <AT91F_DBGU_Init>
	AT91F_DBGU_Printk("\n\r\n\rsam7dfu - AT91SAM7 USB DFU bootloader\n\r"
    1300:	e59f0078 	ldr	r0, [pc, #120]	; 1380 <dfu_main+0xa8>
    1304:	eb00004d 	bl	1440 <AT91F_DBGU_Printk>
		 "(C) 2006-2008 by Harald Welte <hwelte@hmw-consulting.de>\n\r"
		 "This software is FREE SOFTWARE licensed under GNU GPL\n\r");
	AT91F_DBGU_Printk("Version " COMPILE_SVNREV 
    1308:	e59f0074 	ldr	r0, [pc, #116]	; 1384 <dfu_main+0xac>
    130c:	eb00004b 	bl	1440 <AT91F_DBGU_Printk>
			  " compiled " COMPILE_DATE 
			  " by " COMPILE_BY "\n\r\n\r");

	udp_init();
    1310:	ebfffee2 	bl	ea0 <udp_init>

	dfu_state = DFU_STATE_dfuIDLE;
    1314:	e59f306c 	ldr	r3, [pc, #108]	; 1388 <dfu_main+0xb0>
    1318:	e3a01002 	mov	r1, #2
			      OPENPCD_IRQ_PRIO_UDP,
			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, dfu_udp_irq);
	*/
	AT91PS_AIC pAic = AT91C_BASE_AIC;
	pAic->AIC_IDCR = 1 << AT91C_ID_UDP;
	pAic->AIC_SVR[AT91C_ID_UDP] = (unsigned int) &dfu_udp_irq;
    131c:	e59f0068 	ldr	r0, [pc, #104]	; 138c <dfu_main+0xb4>
	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_UDP,
			      OPENPCD_IRQ_PRIO_UDP,
			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, dfu_udp_irq);
	*/
	AT91PS_AIC pAic = AT91C_BASE_AIC;
	pAic->AIC_IDCR = 1 << AT91C_ID_UDP;
    1320:	e3a02b02 	mov	r2, #2048	; 0x800
			  " compiled " COMPILE_DATE 
			  " by " COMPILE_BY "\n\r\n\r");

	udp_init();

	dfu_state = DFU_STATE_dfuIDLE;
    1324:	e5831000 	str	r1, [r3]
	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_UDP,
			      OPENPCD_IRQ_PRIO_UDP,
			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, dfu_udp_irq);
	*/
	AT91PS_AIC pAic = AT91C_BASE_AIC;
	pAic->AIC_IDCR = 1 << AT91C_ID_UDP;
    1328:	e3e03c0f 	mvn	r3, #3840	; 0xf00
    132c:	e5832025 	str	r2, [r3, #37]	; 0x25
	pAic->AIC_SVR[AT91C_ID_UDP] = (unsigned int) &dfu_udp_irq;
    1330:	e5030053 	str	r0, [r3, #-83]	; 0xffffffad
	pAic->AIC_SMR[AT91C_ID_UDP] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 
    1334:	e50310d3 	str	r1, [r3, #-211]	; 0xffffff2d

	/* End-of-Bus-Reset is always enabled */

	/* Clear for set the Pull up resistor */
#if defined(PCD)
	AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUP);
    1338:	e3a00501 	mov	r0, #4194304	; 0x400000
	AT91PS_AIC pAic = AT91C_BASE_AIC;
	pAic->AIC_IDCR = 1 << AT91C_ID_UDP;
	pAic->AIC_SVR[AT91C_ID_UDP] = (unsigned int) &dfu_udp_irq;
	pAic->AIC_SMR[AT91C_ID_UDP] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 
					OPENPCD_IRQ_PRIO_UDP;
	pAic->AIC_ICCR = 1 << AT91C_ID_UDP;
    133c:	e5832029 	str	r2, [r3, #41]	; 0x29
static inline void AT91F_AIC_EnableIt (
	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
	unsigned int irq_id ) // \arg interrupt number to initialize
{
    //* Enable the interrupt on the interrupt controller
    pAic->AIC_IECR = 0x1 << irq_id ;
    1340:	e5832021 	str	r2, [r3, #33]	; 0x21

	/* End-of-Bus-Reset is always enabled */

	/* Clear for set the Pull up resistor */
#if defined(PCD)
	AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUP);
    1344:	ebfffee3 	bl	ed8 <AT91F_PIO_SetOutput.clone.6>
#endif
	AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, OPENPCD_PIO_UDP_PUPv4);
    1348:	e3a00801 	mov	r0, #65536	; 0x10000
    134c:	ebfffee4 	bl	ee4 <AT91F_PIO_ClearOutput.clone.7>

	flash_init();
    1350:	eb00007b 	bl	1544 <flash_init>

	AT91F_DBGU_Printk("You may now start the DFU up/download process\r\n");
    1354:	e59f0034 	ldr	r0, [pc, #52]	; 1390 <dfu_main+0xb8>
    1358:	eb000038 	bl	1440 <AT91F_DBGU_Printk>
	/* do nothing, since all of DFU is interrupt driven */
	int i = 0;
    135c:	e3a01000 	mov	r1, #0
	while (1) {
	    /* Occasionally reset watchdog */
	    i = (i+1) % 10000;
    1360:	e2810001 	add	r0, r1, #1
    1364:	e59f1028 	ldr	r1, [pc, #40]	; 1394 <dfu_main+0xbc>
    1368:	eb000109 	bl	1794 <__aeabi_idivmod>
	    if( i== 0) {
    136c:	e3510000 	cmp	r1, #0
//* \brief Restart Watchdog
//*----------------------------------------------------------------------------
static inline void AT91F_WDTRestart(
        AT91PS_WDTC pWDTC)
{
	pWDTC->WDTC_WDCR = 0xA5000001;
    1370:	059f2020 	ldreq	r2, [pc, #32]	; 1398 <dfu_main+0xc0>
    1374:	03e03c02 	mvneq	r3, #512	; 0x200
    1378:	050320bf 	streq	r2, [r3, #-191]	; 0xffffff41
    137c:	eafffff7 	b	1360 <dfu_main+0x88>
    1380:	0000199c 	.word	0x0000199c
    1384:	00001a39 	.word	0x00001a39
    1388:	00200020 	.word	0x00200020
    138c:	00000f04 	.word	0x00000f04
    1390:	00001a7c 	.word	0x00001a7c
    1394:	00002710 	.word	0x00002710
    1398:	a5000001 	.word	0xa5000001

0000139c <AT91F_DBGU_Ready>:
#include <string.h>

#define USART_SYS_LEVEL 4
void AT91F_DBGU_Ready(void)
{
	while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY)) ;
    139c:	e3e03c0d 	mvn	r3, #3328	; 0xd00
    13a0:	e51330eb 	ldr	r3, [r3, #-235]	; 0xffffff15
    13a4:	e3130c02 	tst	r3, #512	; 0x200
    13a8:	0afffffb 	beq	139c <AT91F_DBGU_Ready>
}
    13ac:	e12fff1e 	bx	lr

000013b0 <AT91F_DBGU_Init>:
		AT91F_DBGU_Printk("\n\r");
	}
}

void AT91F_DBGU_Init(void)
{
    13b0:	e92d4037 	push	{r0, r1, r2, r4, r5, lr}
	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
	unsigned int periphAEnable,  // \arg PERIPH A to enable
	unsigned int periphBEnable)  // \arg PERIPH B to enable

{
	pPio->PIO_ASR = periphAEnable;
    13b4:	e3e03c0b 	mvn	r3, #2816	; 0xb00
    13b8:	e3a02c06 	mov	r2, #1536	; 0x600
	pPio->PIO_BSR = periphBEnable;
    13bc:	e3a04000 	mov	r4, #0
	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
	unsigned int periphAEnable,  // \arg PERIPH A to enable
	unsigned int periphBEnable)  // \arg PERIPH B to enable

{
	pPio->PIO_ASR = periphAEnable;
    13c0:	e503208f 	str	r2, [r3, #-143]	; 0xffffff71
	/* Open PIO for DBGU */
	AT91F_DBGU_CfgPIO();
	/* Enable Transmitter & receivier */
	((AT91PS_USART) AT91C_BASE_DBGU)->US_CR = 
    13c4:	e3e05c0d 	mvn	r5, #3328	; 0xd00
	pPio->PIO_BSR = periphBEnable;
    13c8:	e503408b 	str	r4, [r3, #-139]	; 0xffffff75
	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
    13cc:	e50320fb 	str	r2, [r3, #-251]	; 0xffffff05
    13d0:	e3a0300c 	mov	r3, #12
    13d4:	e50530ff 	str	r3, [r5, #-255]	; 0xffffff01
					AT91C_US_RSTTX | AT91C_US_RSTRX;

	/* Configure DBGU */
	AT91F_US_Configure(AT91C_BASE_DBGU,
    13d8:	e59f004c 	ldr	r0, [pc, #76]	; 142c <AT91F_DBGU_Init+0x7c>
    13dc:	e59f104c 	ldr	r1, [pc, #76]	; 1430 <AT91F_DBGU_Init+0x80>
    13e0:	e2822d0b 	add	r2, r2, #704	; 0x2c0
    13e4:	e59f3048 	ldr	r3, [pc, #72]	; 1434 <AT91F_DBGU_Init+0x84>
    13e8:	e58d4000 	str	r4, [sp]
    13ec:	ebfffcf4 	bl	7c4 <AT91F_US_Configure>
			   MCK, AT91C_US_ASYNC_MODE,
			   AT91C_DBGU_BAUD, 0);

	/* Enable Transmitter & receivier */
	((AT91PS_USART) AT91C_BASE_DBGU)->US_CR = 
    13f0:	e3a03050 	mov	r3, #80	; 0x50
    13f4:	e50530ff 	str	r3, [r5, #-255]	; 0xffffff01
	/* Enable USART IT error and AT91C_US_ENDRX */
	AT91F_US_EnableIt((AT91PS_USART) AT91C_BASE_DBGU, AT91C_US_RXRDY);

	/* open interrupt */

	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS, USART_SYS_LEVEL,
    13f8:	e59f3038 	ldr	r3, [pc, #56]	; 1438 <AT91F_DBGU_Init+0x88>
static inline void AT91F_US_EnableIt (
	AT91PS_USART pUSART, // \arg pointer to a USART controller
	unsigned int flag)   // \arg IT to be enabled
{
	//* Write to the IER register
	pUSART->US_IER = flag;
    13fc:	e3a01001 	mov	r1, #1
    1400:	e50510f7 	str	r1, [r5, #-247]	; 0xffffff09
    1404:	e3a02004 	mov	r2, #4
    1408:	e58d3000 	str	r3, [sp]
    140c:	e59f0028 	ldr	r0, [pc, #40]	; 143c <AT91F_DBGU_Init+0x8c>
    1410:	e1a03004 	mov	r3, r4
    1414:	ebfffbd0 	bl	35c <AT91F_AIC_ConfigureIt>
static inline void AT91F_AIC_EnableIt (
	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
	unsigned int irq_id ) // \arg interrupt number to initialize
{
    //* Enable the interrupt on the interrupt controller
    pAic->AIC_IECR = 0x1 << irq_id ;
    1418:	e3a02002 	mov	r2, #2
    141c:	e3e03c0f 	mvn	r3, #3840	; 0xf00
    1420:	e5832021 	str	r2, [r3, #33]	; 0x21
			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
			      DBGU_irq_handler);
	AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);

}
    1424:	e8bd403e 	pop	{r1, r2, r3, r4, r5, lr}
    1428:	e12fff1e 	bx	lr
    142c:	fffff200 	.word	0xfffff200
    1430:	02db4000 	.word	0x02db4000
    1434:	0001c200 	.word	0x0001c200
    1438:	00001488 	.word	0x00001488
    143c:	fffff000 	.word	0xfffff000

00001440 <AT91F_DBGU_Printk>:

void AT91F_DBGU_Printk(char *buffer)
{
	while (*buffer != '\0') {
    1440:	ea000004 	b	1458 <AT91F_DBGU_Printk+0x18>
//* \brief Return 1 if a character can be written in US_THR
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_US_TxReady (
	AT91PS_USART pUSART )     // \arg pointer to a USART controller
{
    return (pUSART->US_CSR & AT91C_US_TXRDY);
    1444:	e3e02c0d 	mvn	r2, #3328	; 0xd00
    1448:	e51210eb 	ldr	r1, [r2, #-235]	; 0xffffff15
		while (!AT91F_US_TxReady((AT91PS_USART) AT91C_BASE_DBGU)) ;
    144c:	e3110002 	tst	r1, #2
    1450:	0afffffb 	beq	1444 <AT91F_DBGU_Printk+0x4>
//*----------------------------------------------------------------------------
static inline void AT91F_US_PutChar (
	AT91PS_USART pUSART,
	int character )
{
    pUSART->US_THR = (character & 0x1FF);
    1454:	e50230e3 	str	r3, [r2, #-227]	; 0xffffff1d

}

void AT91F_DBGU_Printk(char *buffer)
{
	while (*buffer != '\0') {
    1458:	e4d03001 	ldrb	r3, [r0], #1
    145c:	e3530000 	cmp	r3, #0
    1460:	1afffff7 	bne	1444 <AT91F_DBGU_Printk+0x4>
		while (!AT91F_US_TxReady((AT91PS_USART) AT91C_BASE_DBGU)) ;
		AT91F_US_PutChar((AT91PS_USART) AT91C_BASE_DBGU, *buffer++);
	}
}
    1464:	e12fff1e 	bx	lr

00001468 <AT91F_DBGU_Get>:
//* \brief Return 1 if a character can be read in US_RHR
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_US_RxReady (
	AT91PS_USART pUSART )     // \arg pointer to a USART controller
{
    return (pUSART->US_CSR & AT91C_US_RXRDY);
    1468:	e3e03c0d 	mvn	r3, #3328	; 0xd00
    146c:	e51320eb 	ldr	r2, [r3, #-235]	; 0xffffff15

int AT91F_DBGU_Get(char *val)
{
	if ((AT91F_US_RxReady((AT91PS_USART) AT91C_BASE_DBGU)) == 0)
    1470:	e2122001 	ands	r2, r2, #1
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
static inline int AT91F_US_GetChar (
	const AT91PS_USART pUSART)
{
    return((pUSART->US_RHR) & 0x1FF);
    1474:	151330e7 	ldrne	r3, [r3, #-231]	; 0xffffff19
		return (0);
    1478:	01a00002 	moveq	r0, r2
	else {
		*val = AT91F_US_GetChar((AT91PS_USART) AT91C_BASE_DBGU);
    147c:	15c03000 	strbne	r3, [r0]
		return (-1);
    1480:	13e00000 	mvnne	r0, #0
	}
}
    1484:	e12fff1e 	bx	lr

00001488 <DBGU_irq_handler>:
{
	while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY)) ;
}

static void DBGU_irq_handler(void)
{
    1488:	e92d4010 	push	{r4, lr}
	static char value;

	AT91F_DBGU_Get(&value);
    148c:	e59f4038 	ldr	r4, [pc, #56]	; 14cc <DBGU_irq_handler+0x44>
    1490:	e1a00004 	mov	r0, r4
    1494:	ebfffff3 	bl	1468 <AT91F_DBGU_Get>
	switch (value) {
    1498:	e5d43000 	ldrb	r3, [r4]
    149c:	e3530039 	cmp	r3, #57	; 0x39
    14a0:	1a000006 	bne	14c0 <DBGU_irq_handler+0x38>
	case '9':
		AT91F_DBGU_Printk("Resetting SAM7\n\r");
    14a4:	e59f0024 	ldr	r0, [pc, #36]	; 14d0 <DBGU_irq_handler+0x48>
    14a8:	ebffffe4 	bl	1440 <AT91F_DBGU_Printk>
//*----------------------------------------------------------------------------
static inline void AT91F_RSTSoftReset(
        AT91PS_RSTC pRSTC,
        unsigned int reset)
{
	pRSTC->RSTC_RCR = (0xA5000000 | reset);
    14ac:	e59f2020 	ldr	r2, [pc, #32]	; 14d4 <DBGU_irq_handler+0x4c>
    14b0:	e3e03c02 	mvn	r3, #512	; 0x200
    14b4:	e50320ff 	str	r2, [r3, #-255]	; 0xffffff01
				   AT91C_RSTC_PERRST|AT91C_RSTC_EXTRST);
		break;
	default:
		AT91F_DBGU_Printk("\n\r");
	}
}
    14b8:	e8bd4010 	pop	{r4, lr}
    14bc:	e12fff1e 	bx	lr
		AT91F_DBGU_Printk("Resetting SAM7\n\r");
		AT91F_RSTSoftReset(AT91C_BASE_RSTC, AT91C_RSTC_PROCRST|
				   AT91C_RSTC_PERRST|AT91C_RSTC_EXTRST);
		break;
	default:
		AT91F_DBGU_Printk("\n\r");
    14c0:	e59f0010 	ldr	r0, [pc, #16]	; 14d8 <DBGU_irq_handler+0x50>
	}
}
    14c4:	e8bd4010 	pop	{r4, lr}
		AT91F_DBGU_Printk("Resetting SAM7\n\r");
		AT91F_RSTSoftReset(AT91C_BASE_RSTC, AT91C_RSTC_PROCRST|
				   AT91C_RSTC_PERRST|AT91C_RSTC_EXTRST);
		break;
	default:
		AT91F_DBGU_Printk("\n\r");
    14c8:	eaffffdc 	b	1440 <AT91F_DBGU_Printk>
    14cc:	00201be8 	.word	0x00201be8
    14d0:	00001aac 	.word	0x00001aac
    14d4:	a500000d 	.word	0xa500000d
    14d8:	00001a79 	.word	0x00001a79

000014dc <AT91F_MC_EFC_PerformCmd.clone.3>:
//*----------------------------------------------------------------------------
static inline void AT91F_MC_EFC_PerformCmd (
	AT91PS_MC pMC, // pointer to a MC controller
    unsigned int transfer_cmd)
{
	pMC->MC_FCR = transfer_cmd;	
    14dc:	e3e03000 	mvn	r3, #0
    14e0:	e503009b 	str	r0, [r3, #-155]	; 0xffffff65
}
    14e4:	e12fff1e 	bx	lr

000014e8 <flash_page>:

static u_int16_t page_from_ramaddr(const void *addr)
{
	u_int32_t ramaddr = (u_int32_t) addr;
	ramaddr -= (u_int32_t) AT91C_IFLASH;
	return ((ramaddr >> AT91C_IFLASH_PAGE_SHIFT));
    14e8:	e1a03700 	lsl	r3, r0, #14
//* \brief Return MC EFC Status
//*----------------------------------------------------------------------------
static inline unsigned int AT91F_MC_EFC_GetStatus(
	AT91PS_MC pMC) // pointer to a MC controller
{
	return pMC->MC_FSR;
    14ec:	e3e02000 	mvn	r2, #0
				AT91C_MC_CORRECT_KEY | (page << 8));
}

void flash_page(u_int8_t *addr)
{
	u_int16_t page = page_from_ramaddr(addr) & 0x3ff;
    14f0:	e1a03b23 	lsr	r3, r3, #22
	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK |
				AT91C_MC_CORRECT_KEY | (page << 8));
}

void flash_page(u_int8_t *addr)
{
    14f4:	e92d4070 	push	{r4, r5, r6, lr}
	u_int16_t page = page_from_ramaddr(addr) & 0x3ff;
    14f8:	e1a03803 	lsl	r3, r3, #16
    14fc:	e5125097 	ldr	r5, [r2, #-151]	; 0xffffff69

static int is_page_locked(u_int16_t page)
{
	u_int16_t lockregion = LOCKREGION_FROM_PAGE(page);

	return (AT91C_BASE_MC->MC_FSR & (lockregion << 16));
    1500:	e5122097 	ldr	r2, [r2, #-151]	; 0xffffff69
				AT91C_MC_CORRECT_KEY | (page << 8));
}

void flash_page(u_int8_t *addr)
{
	u_int16_t page = page_from_ramaddr(addr) & 0x3ff;
    1504:	e1a04823 	lsr	r4, r3, #16

static int is_page_locked(u_int16_t page)
{
	u_int16_t lockregion = LOCKREGION_FROM_PAGE(page);

	return (AT91C_BASE_MC->MC_FSR & (lockregion << 16));
    1508:	e1a03a23 	lsr	r3, r3, #20
{
	u_int16_t page = page_from_ramaddr(addr) & 0x3ff;
	u_int32_t fsr = AT91F_MC_EFC_GetStatus(AT91C_BASE_MC);
	DEBUGP("flash_page(0x%x=%u) ", addr, page);

	if (is_page_locked(page)) {
    150c:	e0123803 	ands	r3, r2, r3, lsl #16

static void unlock_page(u_int16_t page)
{
	page &= 0x3ff;
	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK |
				AT91C_MC_CORRECT_KEY | (page << 8));
    1510:	11a00404 	lslne	r0, r4, #8
}

static void unlock_page(u_int16_t page)
{
	page &= 0x3ff;
	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_UNLOCK |
    1514:	1380045a 	orrne	r0, r0, #1509949440	; 0x5a000000
    1518:	13800004 	orrne	r0, r0, #4
    151c:	1bffffee 	blne	14dc <AT91F_MC_EFC_PerformCmd.clone.3>
	if (is_page_locked(page)) {
		DEBUGP("unlocking ");
		unlock_page(page);
	}

	if (!(fsr & AT91C_MC_FRDY)) {
    1520:	e3150001 	tst	r5, #1
    1524:	0a000004 	beq	153c <flash_page+0x54>
	}

	DEBUGP("performing start_prog ");

	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_START_PROG |
				AT91C_MC_CORRECT_KEY | (page << 8));
    1528:	e1a04404 	lsl	r4, r4, #8
		return;
	}

	DEBUGP("performing start_prog ");

	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_START_PROG |
    152c:	e384045a 	orr	r0, r4, #1509949440	; 0x5a000000
    1530:	e3800001 	orr	r0, r0, #1
				AT91C_MC_CORRECT_KEY | (page << 8));
}
    1534:	e8bd4070 	pop	{r4, r5, r6, lr}
		return;
	}

	DEBUGP("performing start_prog ");

	AT91F_MC_EFC_PerformCmd(AT91C_BASE_MC, AT91C_MC_FCMD_START_PROG |
    1538:	eaffffe7 	b	14dc <AT91F_MC_EFC_PerformCmd.clone.3>
				AT91C_MC_CORRECT_KEY | (page << 8));
}
    153c:	e8bd4070 	pop	{r4, r5, r6, lr}
    1540:	e12fff1e 	bx	lr

00001544 <flash_init>:
static inline void AT91F_MC_EFC_CfgModeReg (
	AT91PS_MC pMC, // pointer to a MC controller
	unsigned int mode)        // mode register 
{
	// Write to the FMR register
	pMC->MC_FMR = mode;
    1544:	e59f2008 	ldr	r2, [pc, #8]	; 1554 <flash_init+0x10>
    1548:	e3e03000 	mvn	r3, #0
    154c:	e503209f 	str	r2, [r3, #-159]	; 0xffffff61
{
	unsigned int fmcn = AT91F_MC_EFC_ComputeFMCN(MCK);

	AT91F_MC_EFC_CfgModeReg(AT91C_BASE_MC, (fmcn&0xff) << 16 | 
				AT91C_MC_FWS_3FWS);
}
    1550:	e12fff1e 	bx	lr
    1554:	00310300 	.word	0x00310300

00001558 <__aeabi_uidiv>:
    1558:	e2512001 	subs	r2, r1, #1
    155c:	012fff1e 	bxeq	lr
    1560:	3a000036 	bcc	1640 <__aeabi_uidiv+0xe8>
    1564:	e1500001 	cmp	r0, r1
    1568:	9a000022 	bls	15f8 <__aeabi_uidiv+0xa0>
    156c:	e1110002 	tst	r1, r2
    1570:	0a000023 	beq	1604 <__aeabi_uidiv+0xac>
    1574:	e311020e 	tst	r1, #-536870912	; 0xe0000000
    1578:	01a01181 	lsleq	r1, r1, #3
    157c:	03a03008 	moveq	r3, #8
    1580:	13a03001 	movne	r3, #1
    1584:	e3510201 	cmp	r1, #268435456	; 0x10000000
    1588:	31510000 	cmpcc	r1, r0
    158c:	31a01201 	lslcc	r1, r1, #4
    1590:	31a03203 	lslcc	r3, r3, #4
    1594:	3afffffa 	bcc	1584 <__aeabi_uidiv+0x2c>
    1598:	e3510102 	cmp	r1, #-2147483648	; 0x80000000
    159c:	31510000 	cmpcc	r1, r0
    15a0:	31a01081 	lslcc	r1, r1, #1
    15a4:	31a03083 	lslcc	r3, r3, #1
    15a8:	3afffffa 	bcc	1598 <__aeabi_uidiv+0x40>
    15ac:	e3a02000 	mov	r2, #0
    15b0:	e1500001 	cmp	r0, r1
    15b4:	20400001 	subcs	r0, r0, r1
    15b8:	21822003 	orrcs	r2, r2, r3
    15bc:	e15000a1 	cmp	r0, r1, lsr #1
    15c0:	204000a1 	subcs	r0, r0, r1, lsr #1
    15c4:	218220a3 	orrcs	r2, r2, r3, lsr #1
    15c8:	e1500121 	cmp	r0, r1, lsr #2
    15cc:	20400121 	subcs	r0, r0, r1, lsr #2
    15d0:	21822123 	orrcs	r2, r2, r3, lsr #2
    15d4:	e15001a1 	cmp	r0, r1, lsr #3
    15d8:	204001a1 	subcs	r0, r0, r1, lsr #3
    15dc:	218221a3 	orrcs	r2, r2, r3, lsr #3
    15e0:	e3500000 	cmp	r0, #0
    15e4:	11b03223 	lsrsne	r3, r3, #4
    15e8:	11a01221 	lsrne	r1, r1, #4
    15ec:	1affffef 	bne	15b0 <__aeabi_uidiv+0x58>
    15f0:	e1a00002 	mov	r0, r2
    15f4:	e12fff1e 	bx	lr
    15f8:	03a00001 	moveq	r0, #1
    15fc:	13a00000 	movne	r0, #0
    1600:	e12fff1e 	bx	lr
    1604:	e3510801 	cmp	r1, #65536	; 0x10000
    1608:	21a01821 	lsrcs	r1, r1, #16
    160c:	23a02010 	movcs	r2, #16
    1610:	33a02000 	movcc	r2, #0
    1614:	e3510c01 	cmp	r1, #256	; 0x100
    1618:	21a01421 	lsrcs	r1, r1, #8
    161c:	22822008 	addcs	r2, r2, #8
    1620:	e3510010 	cmp	r1, #16
    1624:	21a01221 	lsrcs	r1, r1, #4
    1628:	22822004 	addcs	r2, r2, #4
    162c:	e3510004 	cmp	r1, #4
    1630:	82822003 	addhi	r2, r2, #3
    1634:	908220a1 	addls	r2, r2, r1, lsr #1
    1638:	e1a00230 	lsr	r0, r0, r2
    163c:	e12fff1e 	bx	lr
    1640:	e3500000 	cmp	r0, #0
    1644:	13e00000 	mvnne	r0, #0
    1648:	ea000059 	b	17b4 <__aeabi_idiv0>

0000164c <__aeabi_uidivmod>:
    164c:	e3510000 	cmp	r1, #0
    1650:	0afffffa 	beq	1640 <__aeabi_uidiv+0xe8>
    1654:	e92d4003 	push	{r0, r1, lr}
    1658:	ebffffbe 	bl	1558 <__aeabi_uidiv>
    165c:	e8bd4006 	pop	{r1, r2, lr}
    1660:	e0030092 	mul	r3, r2, r0
    1664:	e0411003 	sub	r1, r1, r3
    1668:	e12fff1e 	bx	lr

0000166c <__aeabi_idiv>:
    166c:	e3510000 	cmp	r1, #0
    1670:	0a000043 	beq	1784 <.divsi3_skip_div0_test+0x110>

00001674 <.divsi3_skip_div0_test>:
    1674:	e020c001 	eor	ip, r0, r1
    1678:	42611000 	rsbmi	r1, r1, #0
    167c:	e2512001 	subs	r2, r1, #1
    1680:	0a000027 	beq	1724 <.divsi3_skip_div0_test+0xb0>
    1684:	e1b03000 	movs	r3, r0
    1688:	42603000 	rsbmi	r3, r0, #0
    168c:	e1530001 	cmp	r3, r1
    1690:	9a000026 	bls	1730 <.divsi3_skip_div0_test+0xbc>
    1694:	e1110002 	tst	r1, r2
    1698:	0a000028 	beq	1740 <.divsi3_skip_div0_test+0xcc>
    169c:	e311020e 	tst	r1, #-536870912	; 0xe0000000
    16a0:	01a01181 	lsleq	r1, r1, #3
    16a4:	03a02008 	moveq	r2, #8
    16a8:	13a02001 	movne	r2, #1
    16ac:	e3510201 	cmp	r1, #268435456	; 0x10000000
    16b0:	31510003 	cmpcc	r1, r3
    16b4:	31a01201 	lslcc	r1, r1, #4
    16b8:	31a02202 	lslcc	r2, r2, #4
    16bc:	3afffffa 	bcc	16ac <.divsi3_skip_div0_test+0x38>
    16c0:	e3510102 	cmp	r1, #-2147483648	; 0x80000000
    16c4:	31510003 	cmpcc	r1, r3
    16c8:	31a01081 	lslcc	r1, r1, #1
    16cc:	31a02082 	lslcc	r2, r2, #1
    16d0:	3afffffa 	bcc	16c0 <.divsi3_skip_div0_test+0x4c>
    16d4:	e3a00000 	mov	r0, #0
    16d8:	e1530001 	cmp	r3, r1
    16dc:	20433001 	subcs	r3, r3, r1
    16e0:	21800002 	orrcs	r0, r0, r2
    16e4:	e15300a1 	cmp	r3, r1, lsr #1
    16e8:	204330a1 	subcs	r3, r3, r1, lsr #1
    16ec:	218000a2 	orrcs	r0, r0, r2, lsr #1
    16f0:	e1530121 	cmp	r3, r1, lsr #2
    16f4:	20433121 	subcs	r3, r3, r1, lsr #2
    16f8:	21800122 	orrcs	r0, r0, r2, lsr #2
    16fc:	e15301a1 	cmp	r3, r1, lsr #3
    1700:	204331a1 	subcs	r3, r3, r1, lsr #3
    1704:	218001a2 	orrcs	r0, r0, r2, lsr #3
    1708:	e3530000 	cmp	r3, #0
    170c:	11b02222 	lsrsne	r2, r2, #4
    1710:	11a01221 	lsrne	r1, r1, #4
    1714:	1affffef 	bne	16d8 <.divsi3_skip_div0_test+0x64>
    1718:	e35c0000 	cmp	ip, #0
    171c:	42600000 	rsbmi	r0, r0, #0
    1720:	e12fff1e 	bx	lr
    1724:	e13c0000 	teq	ip, r0
    1728:	42600000 	rsbmi	r0, r0, #0
    172c:	e12fff1e 	bx	lr
    1730:	33a00000 	movcc	r0, #0
    1734:	01a00fcc 	asreq	r0, ip, #31
    1738:	03800001 	orreq	r0, r0, #1
    173c:	e12fff1e 	bx	lr
    1740:	e3510801 	cmp	r1, #65536	; 0x10000
    1744:	21a01821 	lsrcs	r1, r1, #16
    1748:	23a02010 	movcs	r2, #16
    174c:	33a02000 	movcc	r2, #0
    1750:	e3510c01 	cmp	r1, #256	; 0x100
    1754:	21a01421 	lsrcs	r1, r1, #8
    1758:	22822008 	addcs	r2, r2, #8
    175c:	e3510010 	cmp	r1, #16
    1760:	21a01221 	lsrcs	r1, r1, #4
    1764:	22822004 	addcs	r2, r2, #4
    1768:	e3510004 	cmp	r1, #4
    176c:	82822003 	addhi	r2, r2, #3
    1770:	908220a1 	addls	r2, r2, r1, lsr #1
    1774:	e35c0000 	cmp	ip, #0
    1778:	e1a00233 	lsr	r0, r3, r2
    177c:	42600000 	rsbmi	r0, r0, #0
    1780:	e12fff1e 	bx	lr
    1784:	e3500000 	cmp	r0, #0
    1788:	c3e00102 	mvngt	r0, #-2147483648	; 0x80000000
    178c:	b3a00102 	movlt	r0, #-2147483648	; 0x80000000
    1790:	ea000007 	b	17b4 <__aeabi_idiv0>

00001794 <__aeabi_idivmod>:
    1794:	e3510000 	cmp	r1, #0
    1798:	0afffff9 	beq	1784 <.divsi3_skip_div0_test+0x110>
    179c:	e92d4003 	push	{r0, r1, lr}
    17a0:	ebffffb3 	bl	1674 <.divsi3_skip_div0_test>
    17a4:	e8bd4006 	pop	{r1, r2, lr}
    17a8:	e0030092 	mul	r3, r2, r0
    17ac:	e0411003 	sub	r1, r1, r3
    17b0:	e12fff1e 	bx	lr

000017b4 <__aeabi_idiv0>:
    17b4:	e12fff1e 	bx	lr

000017b8 <dfu_dev_descriptor>:
    17b8:	01000112 08000000 076b16c0 00000000     ..........k.....
    17c8:	02090100                                         ..

000017ca <dfu_cfg_descriptor>:
    17ca:	00240209 80000101 00040964 01fe0000     ..$.....d.......
    17da:	04090002 fe000100 09000201 ff000321     ............!...
    17ea:	01000100 18080000                                ......

000017f0 <usb_strings>:
    17f0:	00001808 0000180c 00001874 000018b2     ........t.......
    1800:	000018e6 00001942                       ....B...

00001808 <string0>:
    1808:	04090304                                ....

0000180c <string1>:
    180c:	00620368 00740069 0061006d 0075006e     h.b.i.t.m.a.n.u.
    181c:	00610066 0074006b 00720075 0064002e     f.a.k.t.u.r...d.
    182c:	00200065 00540049 00530020 006c006f     e. .I.T. .S.o.l.
    183c:	00740075 006f0069 0073006e 00610020     u.t.i.o.n.s. .a.
    184c:	0064006e 00680020 0077006d 0063002d     n.d. .h.m.w.-.c.
    185c:	006e006f 00750073 0074006c 006e0069     o.n.s.u.l.t.i.n.
    186c:	002e0067 00650064                       g...d.e.

00001874 <string2>:
    1874:	004f033e 00650070 0050006e 00440043     >.O.p.e.n.P.C.D.
    1884:	00520020 00490046 00200044 00650052      .R.F.I.D. .R.e.
    1894:	00640061 00720065 002d0020 00440020     a.d.e.r. .-. .D.
    18a4:	00550046 004d0020 0064006f 03340065              F.U. .M.o.d.e.

000018b2 <string3>:
    18b2:	004f0334 00650070 0050006e 00440043     4.O.p.e.n.P.C.D.
    18c2:	00440020 00550046 00430020 006e006f      .D.F.U. .C.o.n.
    18d2:	00690066 00750067 00610072 00690074     f.i.g.u.r.a.t.i.
    18e2:	006e006f                                o.n.

000018e6 <string4>:
    18e6:	004f035c 00650070 0050006e 00440043     \.O.p.e.n.P.C.D.
    18f6:	00440020 00550046 00490020 0074006e      .D.F.U. .I.n.t.
    1906:	00720065 00610066 00650063 002d0020     e.r.f.a.c.e. .-.
    1916:	00410020 00700070 0069006c 00610063      .A.p.p.l.i.c.a.
    1926:	00690074 006e006f 00500020 00720061     t.i.o.n. .P.a.r.
    1936:	00690074 00690074 006e006f              t.i.t.i.o.n.

00001942 <string5>:
    1942:	004f035a 00650070 0050006e 00440043     Z.O.p.e.n.P.C.D.
    1952:	00440020 00550046 00490020 0074006e      .D.F.U. .I.n.t.
    1962:	00720065 00610066 00650063 002d0020     e.r.f.a.c.e. .-.
    1972:	00420020 006f006f 006c0074 0061006f      .B.o.o.t.l.o.a.
    1982:	00650064 00200072 00610050 00740072     d.e.r. .P.a.r.t.
    1992:	00740069 006f0069 0d0a006e 61730d0a     i.t.i.o.n.....sa
    19a2:	6664376d 202d2075 31395441 374d4153     m7dfu - AT91SAM7
    19b2:	42535520 55464420 6f6f6220 616f6c74      USB DFU bootloa
    19c2:	0a726564 2943280d 30303220 30322d36     der..(C) 2006-20
    19d2:	62203830 61482079 646c6172 6c655720     08 by Harald Wel
    19e2:	3c206574 6c657768 68406574 632d776d     te <hwelte@hmw-c
    19f2:	75736e6f 6e69746c 65642e67 540d0a3e     onsulting.de>..T
    1a02:	20736968 74666f73 65726177 20736920     his software is 
    1a12:	45455246 464f5320 52415754 696c2045     FREE SOFTWARE li
    1a22:	736e6563 75206465 7265646e 554e4720     censed under GNU
    1a32:	4c504720 56000d0a 69737265 34206e6f      GPL...Version 4
    1a42:	752d3539 656c636e 63206e61 69706d6f     95-unclean compi
    1a52:	2064656c 31313032 30313530 3036312d     led 20110510-160
    1a62:	20373039 6e207962 407a7465 62756c42     907 by netz@Blub
    1a72:	73694662 0a0d0a68 6f59000d 616d2075     bFish.....You ma
    1a82:	6f6e2079 74732077 20747261 20656874     y now start the 
    1a92:	20554644 642f7075 6c6e776f 2064616f     DFU up/download 
    1aa2:	636f7270 0d737365 6552000a 74746573     process...Resett
    1ab2:	20676e69 374d4153 00000d0a dc130000              ing SAM7......

Disassembly of section .data:

00201ac0 <_data>:
	.global _remap_call_dfu
	.func	_remap_call_dfu
_remap_call_dfu:
		led1on
		/* Remap RAM to 0x00000000 for DFU */
		ldr	r1, =AT91C_BASE_AIC
  201ac0:	e59f100c 	ldr	r1, [pc, #12]	; 201ad4 <_data+0x14>
		mov	r2, #0x01
  201ac4:	e3a02001 	mov	r2, #1
		str	r2, [r1, #AIC_MCR_RCR]
  201ac8:	e5812f00 	str	r2, [r1, #3840]	; 0xf00
		
		ldr	r4, =dfu_main
  201acc:	e59f4004 	ldr	r4, [pc, #4]	; 201ad8 <_data+0x18>
		bx	r4
  201ad0:	e12fff14 	bx	r4
  201ad4:	fffff000 	.word	0xfffff000
  201ad8:	000012d8 	.word	0x000012d8

00201adc <ptr>:
  201adc:	00104000                                .@..

00201ae0 <foo>:
  201ae0:	00003039                                90..