170 lines
6.8 KiB
Plaintext
170 lines
6.8 KiB
Plaintext
1 # 1 "lib/changebit.S"
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1 /*
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0
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0
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2 * linux/arch/arm/lib/changebit.S
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3 *
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4 * Copyright (C) 1995-1996 Russell King
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5 *
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License version 2 as
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8 * published by the Free Software Foundation.
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9 */
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10 #include <asm/linkage.h>
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1 #ifndef __ASM_LINKAGE_H
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11 #include <asm/assembler.h>
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1 /*
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2 * linux/include/asm-arm/assembler.h
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3 *
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4 * Copyright (C) 1996-2000 Russell King
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5 *
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License version 2 as
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8 * published by the Free Software Foundation.
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9 *
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10 * This file contains arm architecture specific defines
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11 * for the different processors.
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12 *
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13 * Do not include any C declarations in this file - it is included by
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14 * assembler source.
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15 */
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16 #ifndef __ASSEMBLY__
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17 #error "Only include this from assembly code"
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18 #endif
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19
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20 #include <asm/ptrace.h>
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1 /*
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21
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22 #define pull lsl
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23 #define push lsr
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24 #define get_byte_0 lsr #24
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25 #define get_byte_1 lsr #16
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26 #define get_byte_2 lsr #8
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27 #define get_byte_3 lsl #0
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28 #define put_byte_0 lsl #24
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29 #define put_byte_1 lsl #16
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30 #define put_byte_2 lsl #8
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31 #define put_byte_3 lsl #0
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32
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33 #define PLD(code...)
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34
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35 #define MODE_USR USR_MODE
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36 #define MODE_FIQ FIQ_MODE
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37 #define MODE_IRQ IRQ_MODE
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38 #define MODE_SVC SVC_MODE
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39
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40 #define DEFAULT_FIQ MODE_FIQ
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41
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42 /*
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43 * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
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44 */
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45 #ifdef __STDC__
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46 #define LOADREGS(cond, base, reglist...)\
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47 ldm##cond base,reglist
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48 #else
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49 #define LOADREGS(cond, base, reglist...)\
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50 ldm/**/cond base,reglist
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51 #endif
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52
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53 /*
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54 * Build a return instruction for this processor type.
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55 */
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56 #define RETINSTR(instr, regs...)\
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57 instr regs
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58
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59 /*
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60 * Enable and disable interrupts
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61 */
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62 .macro disable_irq
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63 msr cpsr_c, #PSR_I_BIT | SVC_MODE
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64 .endm
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65
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66 .macro enable_irq
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67 msr cpsr_c, #SVC_MODE
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68 .endm
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69
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70 /*
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71 * Save the current IRQ state and disable IRQs. Note that this macro
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72 * assumes FIQs are enabled, and that the processor is in SVC mode.
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73 */
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74 .macro save_and_disable_irqs, oldcpsr
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75 mrs \oldcpsr, cpsr
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76 disable_irq
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77 .endm
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78
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79 /*
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80 * Restore interrupt state previously stored in a register. We don't
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81 * guarantee that this will preserve the flags.
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82 */
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83 .macro restore_irqs, oldcpsr
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84 msr cpsr_c, \oldcpsr
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85 .endm
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86
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87 /*
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88 * These two are used to save LR/restore PC over a user-based access.
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89 * The old 26-bit architecture requires that we do. On 32-bit
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90 * architecture, we can safely ignore this requirement.
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91 */
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92 .macro save_lr
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93 .endm
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94
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95 .macro restore_pc
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96 mov pc, lr
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97 .endm
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98 ...
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12 #include "bitops.h"
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1 .macro bitop, instr
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2 and r2, r0, #7
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3 mov r3, #1
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4 mov r3, r3, lsl r2
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5 save_and_disable_irqs ip
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6 ldrb r2, [r1, r0, lsr #3]
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7 \instr r2, r2, r3
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8 strb r2, [r1, r0, lsr #3]
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9 restore_irqs ip
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10 mov pc, lr
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11 .endm
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12
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13 /**
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14 * testop - implement a test_and_xxx_bit operation.
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15 * @instr: operational instruction
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16 * @store: store instruction
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17 *
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18 * Note: we can trivially conditionalise the store instruction
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19 * to avoid dirting the data cache.
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20 */
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21 .macro testop, instr, store
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22 add r1, r1, r0, lsr #3
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23 and r3, r0, #7
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24 mov r0, #1
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25 save_and_disable_irqs ip
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26 ldrb r2, [r1]
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27 tst r2, r0, lsl r3
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28 \instr r2, r2, r0, lsl r3
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29 \store r2, [r1]
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30 restore_irqs ip
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31 moveq r0, #0
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32 mov pc, lr
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33 .endm
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34 ...
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13 .text
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14
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15 /* Purpose : Function to change a bit
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16 * Prototype: int change_bit(int bit, void *addr)
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17 */
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18 ENTRY(_change_bit_be)
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19 0000 180020E2 eor r0, r0, #0x18 @ big endian byte ordering
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20 ENTRY(_change_bit_le)
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21 0004 072000E2 bitop eor
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21 0130A0E3
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21 1332A0E1
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21 00C00FE1
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21 93F021E3
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DEFINED SYMBOLS
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lib/changebit.S:18 .text:00000000 _change_bit_be
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lib/changebit.S:18 .text:00000000 $a
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lib/changebit.S:20 .text:00000004 _change_bit_le
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.debug_aranges:0000000c $d
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NO UNDEFINED SYMBOLS
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