2012-10-08 18:29:22 +02:00
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Netzteil.elf: file format elf32-avr
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Sections:
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Idx Name Size VMA LMA File off Algn
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2012-10-09 18:32:06 +02:00
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0 .text 000000ae 00000000 00000000 00000054 2**1
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2012-10-08 18:29:22 +02:00
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2012-10-09 18:32:06 +02:00
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1 .stab 000006b4 00000000 00000000 00000104 2**2
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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2 .stabstr 00000085 00000000 00000000 000007b8 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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3 .debug_aranges 00000020 00000000 00000000 0000083d 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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4 .debug_pubnames 0000001b 00000000 00000000 0000085d 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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5 .debug_info 00000256 00000000 00000000 00000878 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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6 .debug_abbrev 00000106 00000000 00000000 00000ace 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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7 .debug_line 000001bc 00000000 00000000 00000bd4 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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8 .debug_frame 00000020 00000000 00000000 00000d90 2**2
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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9 .debug_str 000000f6 00000000 00000000 00000db0 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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2012-10-09 18:32:06 +02:00
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10 .debug_pubtypes 00000038 00000000 00000000 00000ea6 2**0
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2012-10-08 18:29:22 +02:00
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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00000000 <__vectors>:
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0: 10 c0 rjmp .+32 ; 0x22 <__ctors_end>
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2: 15 c0 rjmp .+42 ; 0x2e <__bad_interrupt>
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4: 14 c0 rjmp .+40 ; 0x2e <__bad_interrupt>
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6: 13 c0 rjmp .+38 ; 0x2e <__bad_interrupt>
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8: 12 c0 rjmp .+36 ; 0x2e <__bad_interrupt>
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a: 11 c0 rjmp .+34 ; 0x2e <__bad_interrupt>
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c: 10 c0 rjmp .+32 ; 0x2e <__bad_interrupt>
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e: 0f c0 rjmp .+30 ; 0x2e <__bad_interrupt>
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10: 0e c0 rjmp .+28 ; 0x2e <__bad_interrupt>
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12: 0d c0 rjmp .+26 ; 0x2e <__bad_interrupt>
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14: 0c c0 rjmp .+24 ; 0x2e <__bad_interrupt>
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16: 0b c0 rjmp .+22 ; 0x2e <__bad_interrupt>
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18: 0a c0 rjmp .+20 ; 0x2e <__bad_interrupt>
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1a: 09 c0 rjmp .+18 ; 0x2e <__bad_interrupt>
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1c: 08 c0 rjmp .+16 ; 0x2e <__bad_interrupt>
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1e: 07 c0 rjmp .+14 ; 0x2e <__bad_interrupt>
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20: 06 c0 rjmp .+12 ; 0x2e <__bad_interrupt>
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00000022 <__ctors_end>:
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22: 11 24 eor r1, r1
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24: 1f be out 0x3f, r1 ; 63
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26: cf ed ldi r28, 0xDF ; 223
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28: cd bf out 0x3d, r28 ; 61
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2a: 02 d0 rcall .+4 ; 0x30 <main>
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2012-10-09 18:32:06 +02:00
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2c: 3e c0 rjmp .+124 ; 0xaa <_exit>
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2012-10-08 18:29:22 +02:00
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0000002e <__bad_interrupt>:
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2e: e8 cf rjmp .-48 ; 0x0 <__vectors>
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00000030 <main>:
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2012-10-09 18:32:06 +02:00
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#define STP PB0
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#define NET PB1
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#define TWV PB2
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2012-10-08 18:29:22 +02:00
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int main(void) {
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2012-10-09 18:32:06 +02:00
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DDRA |= (1<<PA7) | (1<<PA3) | (1<<PA4);
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30: 8a b3 in r24, 0x1a ; 26
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32: 88 69 ori r24, 0x98 ; 152
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34: 8a bb out 0x1a, r24 ; 26
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DDRB |= (1<<STP) | (1<<NET) | (1<<TWV);
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36: 87 b3 in r24, 0x17 ; 23
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38: 87 60 ori r24, 0x07 ; 7
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3a: 87 bb out 0x17, r24 ; 23
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PORTB |= (1<<NET); //Netzteil Off!
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3c: c1 9a sbi 0x18, 1 ; 24
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2012-10-08 18:29:22 +02:00
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#else
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//round up by default
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__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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2012-10-09 18:32:06 +02:00
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3e: 8f ef ldi r24, 0xFF ; 255
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40: 94 e3 ldi r25, 0x34 ; 52
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42: ac e0 ldi r26, 0x0C ; 12
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44: 81 50 subi r24, 0x01 ; 1
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46: 90 40 sbci r25, 0x00 ; 0
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48: a0 40 sbci r26, 0x00 ; 0
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4a: e1 f7 brne .-8 ; 0x44 <__SREG__+0x5>
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4c: 00 c0 rjmp .+0 ; 0x4e <__SREG__+0xf>
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4e: 00 00 nop
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_delay_ms(500);
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PORTA |= (1<<PA3);
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50: db 9a sbi 0x1b, 3 ; 27
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52: 8f ef ldi r24, 0xFF ; 255
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54: 93 ed ldi r25, 0xD3 ; 211
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56: a0 e3 ldi r26, 0x30 ; 48
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58: 81 50 subi r24, 0x01 ; 1
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5a: 90 40 sbci r25, 0x00 ; 0
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5c: a0 40 sbci r26, 0x00 ; 0
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5e: e1 f7 brne .-8 ; 0x58 <__SREG__+0x19>
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60: 00 c0 rjmp .+0 ; 0x62 <__SREG__+0x23>
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62: 00 00 nop
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_delay_ms(2000);
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PORTB |= (1<<TWV); //12V Schiene On
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64: c2 9a sbi 0x18, 2 ; 24
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PORTB |= (1<<STP); //Stepup On
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66: c0 9a sbi 0x18, 0 ; 24
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PORTA &= ~(1<<PA3);
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68: db 98 cbi 0x1b, 3 ; 27
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6a: 8f ef ldi r24, 0xFF ; 255
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6c: 93 ed ldi r25, 0xD3 ; 211
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6e: a0 e3 ldi r26, 0x30 ; 48
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70: 81 50 subi r24, 0x01 ; 1
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72: 90 40 sbci r25, 0x00 ; 0
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74: a0 40 sbci r26, 0x00 ; 0
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76: e1 f7 brne .-8 ; 0x70 <__SREG__+0x31>
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78: 00 c0 rjmp .+0 ; 0x7a <__SREG__+0x3b>
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7a: 00 00 nop
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_delay_ms(2000);
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PORTB &= ~(1<<NET); //Netzteil An!
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7c: c1 98 cbi 0x18, 1 ; 24
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PORTA |= (1<<PA3);
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7e: db 9a sbi 0x1b, 3 ; 27
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80: 8f ef ldi r24, 0xFF ; 255
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82: 91 e1 ldi r25, 0x11 ; 17
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84: aa e7 ldi r26, 0x7A ; 122
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86: 81 50 subi r24, 0x01 ; 1
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88: 90 40 sbci r25, 0x00 ; 0
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8a: a0 40 sbci r26, 0x00 ; 0
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8c: e1 f7 brne .-8 ; 0x86 <__SREG__+0x47>
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8e: 00 c0 rjmp .+0 ; 0x90 <__SREG__+0x51>
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90: 00 00 nop
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_delay_ms(5000);
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//PORTB &= ~(1<<PB1);
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PORTB &= ~(1<<PB0); //Stepup Off!
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92: c0 98 cbi 0x18, 0 ; 24
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PORTA &= ~(1<<PA3);
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94: db 98 cbi 0x1b, 3 ; 27
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96: 8f e7 ldi r24, 0x7F ; 127
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98: 98 e3 ldi r25, 0x38 ; 56
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9a: a1 e0 ldi r26, 0x01 ; 1
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9c: 81 50 subi r24, 0x01 ; 1
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9e: 90 40 sbci r25, 0x00 ; 0
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a0: a0 40 sbci r26, 0x00 ; 0
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a2: e1 f7 brne .-8 ; 0x9c <__SREG__+0x5d>
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a4: 00 c0 rjmp .+0 ; 0xa6 <__SREG__+0x67>
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a6: 00 00 nop
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a8: f6 cf rjmp .-20 ; 0x96 <__SREG__+0x57>
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2012-10-08 18:29:22 +02:00
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2012-10-09 18:32:06 +02:00
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000000aa <_exit>:
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aa: f8 94 cli
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2012-10-08 18:29:22 +02:00
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2012-10-09 18:32:06 +02:00
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000000ac <__stop_program>:
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ac: ff cf rjmp .-2 ; 0xac <__stop_program>
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